JPS593615A - Dma control system - Google Patents

Abstract

PURPOSE:To minimize the bus occupation time of DMA by separating actual DMA bus occupation time from the preprocessing or postprocessing of DMA and releasing a bus while one I/O performs the preprocessing or postprocessing of DMA. CONSTITUTION:An MPU board interrupts its operation temporarily and is disconnected froma bus to release the bus when a signal DMAWAT signal goes down to ''L'', and restarts operating when the signal goes up to ''H''; and an MPU bus request part 16 generates a signal for the top priority of bus acquisition. An I/O board causes a conflict between the preprocessing or postprocessing of DMA and I/O access by the sequential circuit of an I/O access and DMA access priority processing part 18. If I/O access to the board itself is caused during the preprocessing or postprocessing of DMA, an I/O access accepting part 19 holds an address temporarily and the DMA is attained after the bus is released to the MPU; and the DMAWAT is held at ''H'' and I/O access to the MPU is carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to a direct memory access (DMA) control method for a microcomputer system, and particularly relates to a direct memory access (DMA) control method for a microcomputer system.
A DMA that allows the bus to be released during DMA pre-processing or post-processing when the own board is not accessed in order to minimize the bus occupation time of the MA.
Regarding control method.

(2) Background of the Technology In general computer systems such as microcomputer systems, the central processing unit (CPU) has a common bus line for the data bus or address bus, and the main memory and many other peripheral devices ( (10 devices) are connected, exchange various data, and perform predetermined data processing. In such a computer system, for example, a block of data can be transferred from an external storage device such as a disk device to the main storage device, or conversely, the contents of several pages of the main storage device can be transferred to the disk device. 2 In such cases, it is extremely inefficient to transfer a batch of data via the CPU, so transfer the data without going through the CPU.
A so-called DMA method is adopted in which data is transferred only between the 10 devices and the main storage device.

(3) Prior Art and Problems Conventionally, in this type of DMA control system, when a DMA request occurs, the CPU gives the start address and the end address to the DMA controller, and then gives the right to acquire the lotus to the DMA target device. Controls disconnection from. D.M.A.
After acquiring the bus, the T10 device starts executing DMA to transfer the address contents starting from the first address to the last address, and then receives and receives the data.The T10 device performs post-processing. However, in this case, the bus is continuously occupied during the DMA pre-processing or post-processing time as well as the DMA execution period. As the number of T10 devices that perform DMA increases, it is necessary to shorten the bus occupation time for each DMA as much as possible, but this conventional method has the disadvantage of slow DMA processing. Ta.

(4) Purpose of the Invention The present invention aims to eliminate the drawbacks of the prior art described above and to minimize the DMA bus occupation time.
During pre-processing or post-processing for MA, the bus is released, and DMA is performed during pre-processing or post-processing only if the same Ilo happens to be accessed.T10
This provides a DMA control method that allows a device to occupy a lotus.

(5) Structure of the Invention The feature of the present invention is that in a computer system consisting of a central processing unit and a plurality of T10 devices,
When access target and DMA target functions coexist, DMA pre-processing or DMA post-processing and actual DM
The A bus occupancy time is separated, and the bus is released while one Ilo is performing pre- or post-DMA processing, and if there is an I10 access to the 110 during this time,
Temporary reception at the I10, and the I10 at the central processing unit
The method is characterized by comprising means for notifying temporary suspension of access, and means for giving bus priority to the central processing unit when the DMA processing in the I10 is completed and executing at the previously accepted I10 address. This is based on the DMA control method.

(6) Examples of the invention Next, embodiments of the present invention will be described with reference to the drawings.

The block diagram in FIG. 1 shows the DMA control that minimizes the bus occupation time of the present invention and also allows access to the I10 device that performs pre-processing or post-processing as desired from the program. 1 is a block diagram of a microcomputer system including a method.

In the block diagram of FIG. 1, the microprocessor unit (MPU) section 1 is as follows:
0 to #n) and the main memory MEM3' (by data bus, access bus, control bus, etc.). A circuit 12, an MPU bus control circuit 13 which receives an MPU control signal and controls the bus, an address sofa 14 which receives an address of the MPU and transfers the address to the address bus, or an address bus control circuit 14 which receives an MPU address and transfers the address to the address bus, or an MPU bus control circuit 13 which receives an MPU control signal and transfers the address to the address bus. The control section of the T10 device includes a data buffer 15 for receiving bus control lines, an MPU bus request circuit 16, etc. As shown inside I10#0, a bus control circuit 17 for receiving bus control lines, I10 access, DMA access, priority control, etc. Processing circuit unit 18, I connected to the address bus
10. The access reception section 19 is composed of a timing generation circuit section 20 that generates the timing of a control signal, a DMA request element section 21 consisting of an LSI connected thereto, and other gate circuits. It is assumed that the other T10 devices #1 to Qn have almost the same configuration.

The operation of the MPU board is such that when the input DMAWAT signal becomes "L", it is confirmed that there is a DMA request from the T10 device, so the MPU temporarily stops its operation, and the MPU is stopped by the address Hanofa 14 and data buffer 15. It is placed in a high impedance state and disconnected from the bus to open the lotus for DMA. Conversely, when the DMAWAT signal becomes "H", the MPU resumes its operation, and the MPU lotus request unit 16 creates a signal giving the highest priority for lotus acquisition.

On the I10 board, DMA memory write and DMA
Although the operation is different for memory read, I10 access and DM
I10 access DMA that determines priority with A access
The sequential circuit of the access priority processing unit 18 causes DMA pre-processing or post-processing to compete with I10 access, so that when a 110 access occurs on the own board during DMA pre-processing or post-processing, the I10 access reception is performed by the unit 19 that specifies the address. The priority processing unit 18 temporarily holds the I10 access and makes it wait.
DMAWAT is sent to the MPU as "L" through the DMAWAT, the lotus is opened to the MPU, DMA is performed, and DMAWAT is then set to "H" to perform 110 access of the MPU.

First, the timing chart of FIG. 2 will be used to explain the operation of turning on a DMA memory write.

During DMA memory write, data is transferred from the I10 device to the memory without going through the MPU.

DMA from the I10 board by the DMA request element section 21, etc.
When the request signal DRQ becomes "H", the access priority processing unit 18 determines the processing order of I10 access and DMA request. That is, flip-flops 180 and 1
When the 110 access is to be processed due to the state of 81, the lower recent terminals of flip-flops 180 and 181 are "0" and "1", respectively, so NA is
The output of the ND gate 183 becomes "0" and the DMA request is masked.

Conversely, when DMA is to be processed, the lower recent terminals of Furi, Pflosop 180 and 181 are each set to "1".
and becomes "0", and I10 access is masked. If the I10 access is accepted first, DMA processing will be performed after the I10 access. However, D.M.A.
If there is an I10 access after the request is accepted, the output of the flip-flop 1180 is "0" and the output of the flip-flop 181 is "I", so the I10 access is N A
Masked with N D 182, I
10 For access reception, the command and address are temporarily held in the unit 19, and when a DMA request is received, the timing generation unit sets the read signal R to “H” to the DMA request element unit to read data and set the address at a certain address time. After waiting, a bus request B is sent to the bus via the bus control unit 17.
There is pre-processing before sending PRO.

In other words, after the DMA request is accepted, the
If there is an I10 access, the MPU cannot communicate with other Ilo because of this I10 access, but the MPU has no I10 access on its own board and the MPU cannot communicate with other Ilo.
When the PU accesses another Ilo, the output of the I10 access reception section 19 is aO'', so DMAWAT becomes H'', allowing the MPU to operate, and the MPU bus requesting section 16 sends the highest priority signal for bus acquisition. Accordingly, it is possible to access other Ilo, so I1 is
This will speed up 0 access. I10 on own board
If there is an access, the DMAM
N due to the AND condition of D and own board I10 access
Set the output of AND32 to aO'' and perform DMA for 7MPU.
Set WAT to "L" to temporarily release the bus. This confirms that the MPU has received a DMA request, so the MPU
U temporarily suspends its operation, puts its output in a high impedance state, and disconnects the MPU from the bus. Bus request BPRO
In contrast, a BtJSY signal is generated. That is, when the own board has priority and is able to acquire the lotus, DMA between the memory and the own board, that is, DMA in which data of the own board is transferred to the memory without going through the MPU is performed. Of course, during this time, a DMA address is being generated on the address bus.

When the memory response AcK signal is returned, the DMA
will end. When DMA ends, 110
An access resumption operation is performed. In other words, the DMAMD signal is set to "L" by the memory response signal AC.
F, which causes the bus request signal BPRO, DMA
The WAT signal also becomes "H" and turns off. On the MPU board, the internal flip-flop F/F is turned on at the rising edge of the DMAWAT signal, and the BMPU, which indicates the bus priority in the next cycle, is turned on. This signal is I10
By connecting to #n's BPRN, all 110s clear the bus priority. Since this BPRN signal is input to the hash control unit 13 in the MPU board, the bus request from Ilo is masked, and the MPU confirms that there is no such request, and then resumes the I10 access that was temporarily interrupted by the DMA processing. It will be restarted.
The BMPU signal is turned OFF by the response ACK from Ilo, and the I10 access ends. Although Fig. 1 shows serial connection using BPRN for bus priority determination, parallel connection is of course possible, and in this case, BM
Just connect the PU signal to the highest priority input.

Next, the operation at the time of DMA memory read will be explained with reference to the timing chart of FIG.

In case of DMA IJ- mode, data is transferred from memory I1
0 device without going through the MPU.

As shown in FIG. 3, in the read mode, when a DMA request DRQ is generated on the own board I10, the bus request signal BPRO sends out priority and when the BUSY signal becomes "L", the bus is acquired, so the timing is created. DMAMD becomes "H" and is sent out from the unit 20, and DMA between the memory and Ilo is performed. Of course, while DMA is being performed, the DMA address is on the bus.

The access priority processing unit 18 confirms that DMAMD is ON, gives priority to DMA processing, and starts executing DMA. Then, the DMA execution ends with a response ACK from the memory. Even after the DMA ends, the own board I10 performs a write operation by the W signal that enters the DMA request element section 21 in order to perform post-processing for writing data, and DMAMD remains ON for a certain period of time until this ends. I'm here.

If your own board Ilo is accessed during this time,
Set the DMAWAT signal to “L” to temporarily interrupt the DMA
After confirming that the D signal is OFF, that is, the post-processing of its own board has been completed, the MPU enables all I10 devices to resume post-processing according to the priority order. Therefore, even when reading this DMA memory, the own board Il
While o is performing DMA post-processing, the same own board I1
When an I10 access is made to 0, the I10 access is made to wait, but during this t& processing, when another Ilo is accessed by I10, it can be accessed immediately, resulting in a corresponding increase in speed.

(7) Effect of the invention As described above, according to the configuration of the present invention, DMA is required.
Regardless of the Ilo access time, the DMA bus occupation time can be minimized, and for I10 boards where I10 access and DMA are mixed, even if one Ilo is performing DMA pre-processing or post-processing, it can be done to another Ilo. This has the effect of allowing arbitrary access.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the DMA control circuit of the present invention, FIG. 2 is a timing chart showing operations during DMA memory write, and FIG. 3 is a timing chart showing operations during DMA memory read. . 1...Microprocessor unit section, 2...
I10 device, 3...main storage device, 11...
Microprocessor unit, 12... Response control circuit, 13... MjU bus control circuit, 14...
address buffer, 15... data buffer,
16... MPU bus request circuit, 17... Bus control circuit, 18... I10 access, DMA access, priority processing circuit, 19... I10 access reception unit, 20... Timing creation circuit, 21 ...
DMA request element section. Patent applicant Fujitsu Limited

Claims (1)

[Claims] In a computer system consisting of a central processing unit and multiple I10 devices, when I10 access targets and DMA target functions coexist, DMA preprocessing or DMA postprocessing and actual DMA bus occupancy time are separated. The bus is released while one Ilo is performing pre- or post-DMA processing, and if there is an I10 access to the I10 during this time, the I10 temporarily accepts the I10 access and the I10 access is sent to the central processing unit. A DMA characterized in that it includes means for notifying temporary suspension, and means for giving bus priority to the central processing unit at the time when the DMA processing in the I10 is completed, and executing it at the previously accepted I10 address. control method.