JPH07219836A - Memory control system - Google Patents

Abstract

PURPOSE:To arbitrate the cycles so as to interrupt the continuous cycles as much as possible in a memory access system when a request is produced for a memory cycle (prescribed period cycle) that must be carried out within a prescribed time in the continuous cycles. CONSTITUTION:In reference to the prescribed period cycle requests, the request means are prepared for the requests of levels 1 of the priority lower than the continuous cycles and levels 2 of the priority higher than the continuous cycle. A prescribed period cycle request device outputs first a request of level 1. If the continuous cycles are under execution, a memory controller keeps the request of level 1 waiting. When the continuous cycles end in a prescribed period, the memory controller carries out the prescribed period cycle. If the continuous cycles are not finished in a prescribed period, the device requesting the prescribed period cycle outputs a request of level 2. Then the memory controller carries out the prescribed period cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to memory control,
The present invention relates to a memory control method that determines the execution timing of a transfer cycle having a high priority in continuous cycles.

[0002]

2. Description of the Related Art In a conventional memory control method, when controlling the order of activating memory transfer cycles, priorities are set for the memory cycle requests and the memory transfer cycles are set in descending order of priority of the memory cycle requests. It is a memory control method that arbitrates the cycles to execute and prevents contention of memory cycles.

FIG. 1 shows a cycle which must be executed within a predetermined period during the execution of a conventional cycle for continuously accessing a memory (hereinafter referred to as a continuous cycle) (hereinafter referred to as a predetermined period cycle). ) Is a timing chart when a request occurs.

In the figure, a cycle request is output for a predetermined period during the execution of the continuous cycle.
Since the priority is higher than this continuous cycle, the memory control device interrupts the continuous cycle being executed, and restarts the interrupted continuous cycle after executing the cycle for a predetermined period.

As a means for solving this problem, a cycle request for a predetermined period that must be executed within a predetermined period,
A memory cycle request for continuously accessing a predetermined number of memory data, which has the property of always ending within a predetermined period for the purpose of speeding up, and a memory cycle request for continuously accessing the memory is There is a method of increasing the speed by making a cycle request wait for a predetermined period until the end. As such a memory control method, Japanese Patent Laid-Open No. 3-147035 "Memory control method" is known.
Is mentioned.

[0006]

In a continuous cycle of the memory, the first access to the memory requires a processing time longer than the second and subsequent memory accesses because the cycle start processing is included. At the end of the cycle, cycle end processing is entered.

In the conventional method of performing arbitration in descending order of priority, when a cycle request is generated for a predetermined period during a continuous cycle, the memory control device interrupts the continuous cycle, and after the execution of the cycle for the predetermined period is completed, the above-mentioned interruption is performed. In order to execute the continuous transfer cycle, the cycle end process for interrupting the continuous cycle and the cycle start process for restarting the continuous cycle take extra time compared to the case without executing the interrupt. Efficiency is reduced.

Further, in the "memory control method" disclosed in Japanese Patent Laid-Open No. 3-147035, which is shown as a method for preventing the transfer efficiency from decreasing, the memory cycle for continuously accessing the memory must be completed within a certain period. We did not consider the case where the property does not have the above.

The object of the present invention is to remedy the above-mentioned problems,
(EN) Provided is a memory control device capable of executing a continuous cycle for a memory as continuously as possible, saving time generated by suspending and restarting the continuous cycle, and preventing deterioration in memory access processing performance. is there.

[0010]

SUMMARY OF THE INVENTION In order to enable continuous cycles to be accessed as continuously as possible for accessing a memory, the present invention provides means for executing continuous cycles for continuously accessing a memory. A means for requesting the continuous cycle, a means for requesting a cycle for a predetermined period that must be executed within a predetermined period, a means for arbitrating between the continuous cycle and the cycle for the predetermined period, and receiving a memory cycle request. A means for reporting and a means for reporting that a continuous cycle is in progress are provided. The cycle request for a predetermined period is provided with two levels of request means, ie, a level 1 request having a lower priority than a continuous cycle and a level 2 request having a higher priority than a continuous cycle. When the level 1 request is output during a continuous cycle and the continuous cycle ends within a predetermined period, the means for arbitrating the cycle executes the cycle for a predetermined period after the execution of the continuous cycle, and the continuous cycle within the predetermined period. When the processing is not completed, the requesting means for the predetermined period cycle outputs the level 2 request, so that the memory control device interrupts the continuous cycle, restarts the continuous cycle after executing the predetermined period cycle. To do.

[0011]

The level 1 request, which has a lower priority than the continuous cycle among the predetermined period cycle requests, requests the predetermined period cycle, but since it is within the predetermined period, it indicates that the predetermined period cycle can wait. The higher priority level 2 request indicates that the predetermined period cycle cannot wait because the predetermined period cycle wait period has elapsed.

From the cycle request means for a predetermined period, level 1
While the level 2 request is output and the level 2 request is not output yet, the cycle arbitration means waits for the execution of the predetermined period cycle until the end of the continuous cycle, and then executes the predetermined period cycle after the end of the continuous cycle. Since it is not necessary to perform the interruption process of the continuous cycle, it is possible to prevent the transfer efficiency from decreasing.

If the level 1 request is output from the cycle requesting means for a predetermined period, and the continuous cycle does not end even if the period during which the cycle can wait for the predetermined period has elapsed, the cycle cannot be waited for the predetermined period. Since the level 2 request is output from the period cycle request unit, the cycle arbitration unit interrupts the continuous cycle, executes the predetermined period cycle, and restarts the interrupted continuous cycle, as in the conventional method. Therefore, the transfer efficiency becomes equal to that of the conventional method, but the predetermined period cycle can be surely executed within the predetermined period.

[0014]

Embodiment An embodiment of the present invention will be described with reference to the drawings.

In FIG. 2, during a cycle of continuously accessing a memory according to the present invention (hereinafter referred to as a continuous cycle), a request for a cycle (hereinafter referred to as a predetermined period cycle) that must be executed within a predetermined period is generated. It is an example of a timing chart in the case.

FIG. 2A shows the timing in the case where the continuous cycle ends within the period in which the cycle must be executed for the predetermined period. In the figure, when a request for a level 1 predetermined period cycle is made during access to a memory in continuous cycles, the predetermined period cycle waits until the continuous cycle ends, and when the continuous cycle ends Run a period cycle. As a result, since the interruption processing of the continuous cycle due to the high-priority predetermined period cycle does not occur, it is not necessary to perform the cycle start processing and the cycle end processing of the continuous cycle, and the transfer efficiency does not decrease.

FIG. 2B shows the timing when the continuous cycle does not end within the period in which the cycle must be executed for the predetermined period. In the figure, even if a cycle request of level 1 for a predetermined period is generated during the continuous cycle, the continuous cycle does not end, so the memory control device does not execute the cycle for the predetermined period and waits. Then, after a lapse of a predetermined period of time, the device that outputs the cycle request of the level 1 for the predetermined period of time outputs to the memory controller 2
The cycle request is output for a predetermined period. Upon receiving the level 2 predetermined period cycle request, the memory control device interrupts the continuous cycle, executes the predetermined period cycle, and then restarts the interrupted continuous cycle, as in the conventional method. In this case, the transfer efficiency is equal to that of the conventional method, but the predetermined period cycle is executed reliably within the waiting time.

Next, embodiments of the present invention will be described with reference to specific examples.

In the present embodiment, it is assumed that a high speed page mode access to the memory is possible and an image dual port memory provided with two data input / output ports is used. Further, as an example of a cycle that must be executed within a predetermined period, a read transfer cycle for transferring from the image dual port memory to the display buffer will be taken up.

FIG. 3 shows the configuration of a computer system for implementing the present invention. Reference numeral 1 is a CPU for controlling the entire system, 2 is a main storage device, 3 is a CPU 1 and a main storage 2
And a drawing control device 4 for transmitting and receiving data, a drawing control device 4 for controlling the drawing according to the present embodiment, 5 a fast page mode accessible image memory, and 6 a storage in the image memory. A RAMDAC, 7 for converting the stored data into data for display output is a display device.

When the drawing control device 4 receives the drawing request output from the CPU 1, the drawing control device 4 outputs the control signal of the image memory 5, the address and the data in order to execute the image memory cycle for the drawing request. Since the image memory 5 can be accessed in the high speed page mode transfer cycle, when the drawing control device 4 receives a high speed page mode accessible drawing request, the drawing control device 4
The image memory 5 is accessed in the fast page mode transfer cycle.

The display device 7 displays the contents of the image memory 5. In order to realize this, a read transfer cycle in which transfer to the display buffer is performed at regular intervals is necessary. The drawing control device 4 holds this cycle, and the read transfer cycle is performed at each cycle. Performs control for execution. What is the control to execute the read transfer cycle?
The drawing control device 4 requests the circuit that arbitrates the cycle inside the device for each read transfer cycle to request level 1 which has a lower priority than the fast page mode cycle and level 2 which has a higher priority than the fast page mode cycle. This is performed by arbitrating the execution timing of the drawing request from the CPU 1 and the 2-level read transfer cycle request by using the function of outputting the 2-level read transfer request.

FIG. 4 shows the construction of an embodiment of the drawing control device 4 of the present invention.

Reference numeral 40 is a system bus control unit for inputting / outputting data between the system bus 3 and the internal blocks of the drawing control device 4, 41 is a drawing sequencer for controlling the entire inside of the drawing control device 4, and 42 is a read transfer cycle. Holds
A read transfer counter requesting execution of a read transfer cycle, 43 is a control for converting an address received from the system bus 3 into an address for accessing the image memory control unit 5, and a data transfer between the system bus 3 and the image memory 5. An address / data control unit for performing transmission / reception processing of 44, a 44 is a cycle priority determination unit for receiving a memory cycle request signal generated from the drawing sequencer 41 and the read transfer counter 42, and performing priority determination, and 45 is an image for controlling the image memory. It is a memory control unit.

When the system bus control unit 40 receives the address and data transmitted from the CPU 1, the system bus control unit 40 transmits the received address and data to the drawing sequencer 41. The drawing sequencer 41 is a system bus control unit 40.
The drawing type is determined based on the address and the data transmitted from, and an image memory cycle request signal for the drawing type is output to the cycle priority determination unit 44.

The read transfer counter 42 stores a read transfer cycle, and outputs a read transfer request signal to the cycle priority determination section 44 for each cycle. The read transfer request signal is provided with two request signals, a level 1 request signal having a lower priority than the high speed page mode cycle and a level 2 request signal having a higher priority than the high speed page mode cycle. When the read transfer cycle is executed, the address for performing the read transfer cycle is output to the address / data control unit 43.

The cycle priority determination section 44 includes a drawing memory cycle request signal output from the drawing sequencer 41,
The priority of the read transfer cycle request signal output from the read transfer counter 42 is determined. The cycle priority determination unit also uses the signal output from the drawing sequencer 41 and indicating that the high speed page mode is being accessed for the cycle priority determination processing.

When the cycle priority determination is completed, the cycle priority determination unit 44 outputs a cycle request for the priority-determined image memory to the image memory control unit 45, and when the selected request is received, the drawing sequencer 41 and the read transfer counter 42. The address / data control unit outputs the address / data for the selected image memory cycle request to the image memory control unit.

The image memory control unit which has received the cycle request and the address / data issues an image memory cycle corresponding to the cycle request, and the data is stored in the image memory 5.

Next, FIG. 5 shows an embodiment of the cycle priority judging section 44 which is a block in the drawing control apparatus of the present invention described above.

Reference numeral 440 denotes a level 2 read transfer cycle request regardless of whether a level 1 read transfer cycle request is generated when the high speed page mode cycle is not executed or whether the high speed page mode cycle is being executed. Is generated and a read transfer cycle is activated to activate a read transfer cycle. 441 is a priority determination section other than read transfer that determines priority of a cycle request other than the read transfer cycle. 442 is a read transfer. This is a cycle arbitration unit that detects that the request signal that is prioritized by the priority determination unit 441 other than the read transfer is output without outputting the cycle activation signal.

When the level 1 read transfer cycle request is generated, the read transfer cycle determination unit 440 activates the read transfer cycle request with the highest priority unless the high speed page mode cycle is being executed. If the fast page mode cycle is being executed, after the fast page mode cycle ends,
Alternatively, the read transfer cycle is activated when a level 2 read transfer cycle request is generated. When a cycle request other than the read transfer cycle occurs, the priority determination circuit 4
Reference numeral 41 determines the priority of the image memory cycle with respect to the drawing request from the CPU 1, detects that the cycle transfer unit 442 is not executing the read transfer cycle, and activates the image memory cycle request for which the priority determination has been performed.

FIG. 6 shows the drawing control device of the present invention.
9 is a timing chart of a read transfer cycle during a high-speed page mode cycle when the display buffer has a single buffer configuration.

In the figure, a level 1 read transfer cycle request is output at the end of the display period, but the read transfer cycle is not executed immediately because it is in the high-speed page mode cycle. Since the display data needs to be transferred to the display buffer before the next display starts, if the fast page mode cycle ends before the next display starts, the fast page mode cycle ends. If the fast page mode cycle does not end before the next display is started, a read transfer cycle request of level 2 is issued,
Execute a read transfer cycle. At this time, the fast page mode cycle is interrupted, and the fast page mode cycle is restarted after the end of the read transfer cycle.

In the drawing memory control method described above, the read transfer cycle can be executed only during the non-display period. However, in order to execute the read transfer cycle even during the display period, two or more display buffer configurations are provided. An example of the drawing memory control method in the case of setting is shown below.

FIG. 7 shows the drawing control device of the present invention.
7 is a timing chart of a read transfer cycle during a high-speed page mode cycle when the display buffer has a double buffer configuration. In the figure, initially, display data is stored in the buffer 0, and the display data is displayed. At that time, a read transfer cycle request of level 1 is output to the buffer 1 to fetch the next display data into the display buffer 1, but it is not executed immediately because it is in the high-speed page mode cycle.
Before the display of data in buffer 1 is started, buffer 1
Although the display data must be fetched into the buffer 1, the fast page mode cycle is completed before the data display in the buffer 1 is started. Good. Also, before the next display starts,
If the fast page mode cycle is not completed, a level 2 read transfer cycle request is issued to the buffer 1 to execute the buffer 1 read transfer cycle.
At this time, the fast page mode cycle is interrupted, and the fast page mode cycle is restarted after the end of the read transfer cycle. The above display data processing is performed in buffer 0 and buffer 1.
Will be alternated with.

This embodiment is an example, and the present memory cycle control system can be applied to the control of the refresh cycle of the main memory device or the image memory.

[0038]

As described above, in the memory control method according to the present invention, a cycle for continuously accessing a memory (hereinafter referred to as a continuous cycle) and a memory cycle that must be executed within a predetermined period (hereinafter, a predetermined cycle). (Referred to as a period cycle) conflicts with a predetermined period cycle request,
By providing a two-level transfer request including a level 1 request having a lower priority than the continuous cycle and a level 2 request having a higher priority than the continuous cycle, the continuous cycle can be executed as continuously as possible, and It is possible to reliably execute a cycle for a predetermined period within a predetermined period, reduce the probability of interrupt processing of continuous cycles, and prevent the decrease in transfer efficiency to the memory system. There is.

[Brief description of drawings]

FIG. 1 is a timing chart of a predetermined period cycle in a conventional continuous cycle.

FIG. 2 is a timing chart of a predetermined period cycle in a continuous cycle of the present invention.

FIG. 3 is a diagram showing a computer system for implementing the present invention.

FIG. 4 is a configuration diagram of a drawing control device.

FIG. 5 is a configuration diagram of a cycle priority determination unit.

FIG. 6 is a diagram showing a read transfer cycle (single buffer configuration) during a high speed page cycle of the present invention.

FIG. 7 is a diagram showing a read transfer cycle (double buffer configuration) during a high speed page cycle of the present invention.

[Explanation of symbols]

1 ... CPU, 2 ... Main memory, 3 ... System bus, 4 ... Drawing control device, 5 ... Image memory, 6 ... RAM DAC, 7 ...
Display device, 40 ... System bus control unit, 41 ... Drawing sequencer, 42 ... Refresh / read transfer counter, 4
3 ... Address / data control unit, 44 ... Cycle priority determination unit, 45 ... Image memory control unit, 440 ... Read transfer cycle determination unit for processing read transfer request, 441 ... Priority determination unit other than read transfer, 442 ... Read A cycle arbitration unit that activates cycles other than transfer cycles.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobutaka Kato 810 Shimoimaizumi, Ebina City, Kanagawa Prefecture Office Systems Division, Hitachi, Ltd. (72) Inventor Takashi Toma 810 Shimoimaizumi, Ebina City, Kanagawa Hitachi, Ltd. (72) Inventor Yasuhiro Furukawa 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi Micro Software Systems Ltd. (72) Hideo Haruta 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi Micro Software Co., Ltd. Inside Systems (72) Inventor Norihiro Kurokawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock Company Hitachi Systems Development Laboratory

Claims (3)

[Claims] 1. A memory has a cycle for continuously accessing a memory (hereinafter, referred to as a continuous cycle) and a memory cycle that must be executed within a predetermined time (hereinafter, referred to as a predetermined period cycle). In a memory control device which takes longer time to execute without interruption when it is resumed after interruption, the means for requesting the cycle for the predetermined period requests the level 1 request having a lower priority than the continuous cycle and the request from the continuous cycle. 2 of level 2 requests with high priority
A level requesting means is provided so that the level 1
When the continuous cycle ends within a predetermined period, the predetermined period cycle is executed after the continuous cycle ends, and when the continuous cycle does not end within the predetermined period, the predetermined period cycle requesting means When the level 2 request is output from the memory controller, the memory control device interrupts the continuous cycle, executes the cycle for a predetermined period, and then restarts the continuous cycle. 2. A cycle according to claim 1, which has a display data storage memory and a buffer for temporarily storing display data (hereinafter referred to as a temporary buffer), and transfers the display data from the display memory to the temporary buffer. (Hereinafter referred to as buffer transfer cycle) is executed, and the data transferred to the temporary buffer is displayed by outputting it from the temporary buffer to the display device.While displaying, the displayed data is stored. The drawing control device that cannot execute the buffer transfer cycle to the temporary buffer is provided with means for indicating a non-display period and means for requesting execution of the buffer transfer cycle. A two-level request signal with a level 1 request with a lower priority and a level 2 request with a higher priority than a continuous cycle. The provided, in order to perform the buffer transfer cycles within a period not displayed, the buffer transfer cycle request means outputs the request signal of the level 1 in response to the detection of the period of non-display, the level 1
If the continuous cycle is being executed when the request signal of is output, the drawing control device waits for the buffer transfer cycle, and when the continuous cycle ends within the period of not displaying, after the continuous cycle ends, When the buffer transfer cycle is executed and the continuous cycle does not end within the period of no display, the drawing control device outputs the level 2 request from the buffer transfer cycle requesting means. A drawing memory control method characterized by suspending and executing a buffer transfer cycle and then restarting a continuous cycle. 3. The structure according to claim 2, wherein two or more temporary buffer configurations are provided, and display data is stored in a buffer to be used next before all display data stored in the temporary buffer currently in use is displayed. The drawing memory control method is characterized in that the transfer is controlled so that it can be transferred from the display memory to the temporary buffer even during the display period.