JPH10228418A - Memory controller and memory controlling method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a standby time of each processor which is generated at the time of access competition without bringing about the transfer efficiency drop of a memory bus due to overhead which is accompanied with interruption and restart of data transfer by suspending a shared memory access based on an access request from a processor that is in the process of data transfer and interrupting data transfer to any cache memory to which a page address agrees. SOLUTION: A page address for a shared memory part 5 in transfer through a common memory bus 3 is held. With this, a page address for the part 5 which is desired by an access request to cache memory that is different from a cache memory which is in a transfer state is detected. When a page address that is in the process of transfer coincides with a page address that is desired by the access request, data transfer to cache memory that agrees to the page address is interrupted in a state where access to shared memory during data transfer is held.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory control device and a memory control method for controlling access to a dedicated cache memory of each processor and a shared memory in which each cache memory transfers data through a common bus. is there.

[0002]

2. Description of the Related Art Conventionally, in a multiprocessor system including a dedicated cache memory of each processor and a shared memory constituting a DRAM in which each cache memory transfers data through a common bus, each cache memory is transmitted from a processor. Generates an access request signal to the shared memory to the memory bus controller due to occurrence of a mishit or the like due to the access of the memory bus. The memory bus controller detects an access request signal from each cache memory to the shared memory, arbitrates the access request from each cache memory according to the bus usage, and as a result, allows access to the shared memory. An access permission signal is generated for the cache memory.

[0003] The cache memory, which has obtained the access right by the arbitration of the memory bus controller, drives the memory bus and starts accessing the shared memory.
Cache line data is transferred at high speed in a burst transfer mode in units of blocks of a predetermined size.

On the other hand, each cache memory which has not been able to obtain the access right due to the arbitration result of the bus controller while issuing the access request continues to hold the access request until it obtains the access right. Further, the processor accessing this cache memory holds the wait state by the wait cycle during this time.

However, in a shared memory system that follows such a memory access sequence, in an access collision occurring between a plurality of cache memories, the common memory bus is accessed by only one cache memory permitted to access (cache line = cache line). (Fixed block size data).

Accordingly, the increase in the number of competing access requests increases the access wait time of each cache memory due to the contention and the access wait time of the processor which causes the cache memory access request, resulting in a total processing efficiency of the system. Will be reduced.

As a method of avoiding such a decrease in processing efficiency, the above-described decrease in processing efficiency is improved by temporarily stopping access to the shared memory during transfer and interrupting data transfer in response to a transfer request to be prioritized. It is possible to do. This method will be described below.

As is well known, memory access by a processor or DMA has continuity and locality, and the cache memory utilizes this property to substantially improve access efficiency. Here, paying attention to the actual transfer of cache line data, the data desired to access the cache memory, which is the cause of the occurrence of a mishit, tends to be transferred at the beginning of the cache line data transfer. It is clear that this property results from the continuity of the memory access described above.

Therefore, even if the temporary transfer is interrupted when the initial data of the cache line is transferred, it can be said that the influence on the cache memory access which caused the transfer is extremely small. The above-described method for improving processing efficiency uses such a property to reduce the loss due to the waiting of each processor at the time of contention for access to the shared memory.

[0010]

However, access contention control using a plurality of cache memories according to the above-described method involves an increase in the memory bus occupation time per cache line due to the addition of an overhead cycle accompanying the interruption and restart of data transfer. Things.

Here, the overhead cycle is a precharge cycle indispensable for DRAM access and a memory access cycle corresponding to a time required for re-outputting a row address at the time of resuming transfer.

Since the overhead cycle is indispensable at the time of interrupting and resuming the data transfer due to the interrupt access as described above, the overhead cycle increases with the contention frequency, and consequently reduces the transfer efficiency of the memory bus.

A conventional memory control operation will be described below with reference to timing charts shown in FIGS.

FIGS. 3 and 4 are timing charts for explaining the operation of the conventional memory control device. FIG. 3 is an explanation of an access to a shared memory (DRAM) in the case where no interrupt is performed, decomposed into respective memory states. FIG. 4 shows a timing chart for performing a transfer operation using four words as a cache line, as in FIG. 3, and temporarily suspends the transfer at the end of the transfer of the second word of the first cache line. This corresponds to a timing chart in which a cache line is interrupted and accessed.

Note that the time required for each state is expressed equally for the sake of simplicity.

In FIG. 3, a memory access is composed of six states [RA], [C0] to [C3], and [PR], and has a cache line size of 4 words.
Actually, a state for the refresh cycle is separately generated, but the description will be omitted here.

A memory access is started from a state [RA] for giving a row address to a memory, and is started from a state [C].
0] follows. The head data of the cache line is [data A0] read in this [C0] state.

In the burst transfer mode, states [C1] to [C3] are successively applied, [Data A1] to [Data A3] are read, and the transfer of the first cache line (4 words) is completed. .

When the next transfer is performed on the DRAM for which the transfer has been completed, a precharge state [PR] must be inserted. Therefore, the state [PR] is always required before the transfer of the second cache line is started.

Thereafter, similarly to the first cache line, the transfer is completed by the states [RA] to [C3].

Next, referring to FIG. 4, a description will be given of a shared memory access in the case where interruption and interruption access shown in the conventional example are performed.

As shown in FIG. 4, in the transfer using four words as a cache line as in FIG. 3, the transfer is temporarily interrupted at the end of the transfer of the second word of the first cache line, and the second cache line is stopped. When the access is performed by assuming that the desired data at the address that caused the cache mishit that causes the first and second cache line transfer was both the first data of the respective cache line transfer [Data A0] in the first cache line, and [Data B0] in the second cache line.

Here, focusing on [data B0] of the second cache line, it can be seen that the data is read out two states earlier in FIG. 4 than in FIG.

In other words, this indicates that the desired data of the processor access which caused the second cache line transfer is read into the cache two states earlier, resulting in a reduction in the waiting time of the processor. I have.

However, the timing at which the transfer of the first and second cache lines ends is reversed by two states earlier in FIG. As is clear from the comparison of the access timing between FIG. 3 and FIG. 4, this corresponds to an increase of two states of the precharge state [PR] and the row address re-output state [RA] due to interruption and restart. This is the above-mentioned overhead state, and this state increases in proportion to the interruption and resumption that occurs in the cache line, and causes a reduction in transfer efficiency.

As described above, according to the above-described method, the interruption during the transfer of the cache line is enabled to transfer the data to another cache memory. Although it is possible to shorten the transfer time, on the other hand, there is a problem that the transfer efficiency of the memory bus is reduced due to the overhead caused by the interruption and restart of the transfer.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to change the page address of data transfer to another processor during data transfer from one of the processors to the shared memory. From the shared memory, the access right to the shared memory is issued to the processor, the data transfer is interrupted to the processor currently transferring the data, and the page address is generated to the processor having the access right. Is omitted, and the data read from the shared memory is continuously transferred to the cache memory, so that the transfer efficiency of the memory bus does not decrease due to the overhead due to the interruption and restart of the data transfer, and each of the occurrences at the time of access conflict occurs. A memory control device capable of improving the data transfer processing efficiency by reducing the standby time of the processor And to provide a memory control method.

[0028]

According to a first aspect of the present invention, there is provided a memory control device having a control means for controlling memory access to a shared memory from a plurality of processors each having a cache memory. Holding means for holding a page address of the shared memory accessed by a processor; detecting means for detecting a page address of the shared memory requested by each processor; holding the page address detected by the detecting means and the holding means Determining means for determining whether the page addresses coincide with each other, respectively, corresponding to each processor. When the determining means determines that the respective page addresses match, the control means determines whether or not each page address matches. The shared memory access based on an access request from a processor during transfer It interrupted, but to interrupt the data transfer to either of the cache memory page addresses match.

A second invention according to the present invention is a memory control method for controlling memory access to a shared memory from a plurality of processors each having a cache memory, wherein a page address of the shared memory accessed by any one of the processors is provided. Is stored in a buffer memory, a page address of the shared memory requested by each processor is detected, and it is determined whether or not the detected page address matches a page address stored in the buffer memory. Is determined to match, the shared memory access based on the access request from the processor during the data transfer is interrupted, and the data transfer to one of the cache memories having the same page address is interrupted.

[0030]

FIG. 1 is a block diagram illustrating a configuration of a memory control device according to an embodiment of the present invention.
For example, this corresponds to a case where a multiprocessor system in which four processors each have a cache memory is configured.

In FIG. 1, the cache memory control unit 6
a to 6d hold partial copies of the data stored in the shared memory unit 5 in the buffer memories (cache memories) 2a to 2d in block units. The cache memory control units 6a to 6d request access to the shared memory unit 5,
In response to the access request, the cache memory controllers 6a to 6d determine whether or not a copy of the data desired by the processors 1a to 1d exists in the buffer memories 2a to 2d. If a copy exists on 2d (a cache hit), the corresponding data is immediately read from the buffer memories 2a to 2d and given to the processors 1a to 1d as desired data.

If no copy exists (a cache mishit), a request is made to the shared memory control unit 4 to read a block containing desired data from the shared memory unit 5 (cache line transfer).

The shared memory controller 4 arbitrates with the access requests from the respective cache memory controllers generated at the same time, and distributes the access right to the shared memory unit 5 so that each buffer is transferred from the shared memory unit 5 to each buffer. Memory 2a
To 2d.

The shared memory control unit 4 controls the shared memory unit 5
One of the cache memory control units, for example, the cache memory control unit 6a to which the access right to the access is given generates a desired data address in the order of a page (row) address and a column address. When the page (row) address is generated, the cache memory control units 6a to 6d transmit the page (row) address to the control units 6a to 6d.
d or latched on the buffer memories 2a to 2d.

On the other hand, the cache memory control units 6b other than the cache memory control unit 6a to which no access right is given
6 to 6d determine whether or not the page address held by the buffer memories 2b to 2d holding the page (row) address matches the page address desired by the access request. Notify.

The shared memory control unit 4 notifies the page address of the shared memory access being transferred based on the notification of the determination result and the cache memory control units 6b to 6d that request the access right and wait for the access requested by the other cache memory control units 6b to 6d. The presence / absence of a page address match is determined, and if the page address match is detected, the cache memory controller 6a during transfer is determined.
Cache memory control units 6b to 6b that instruct transfer interruption and notify of page address match.
The interrupt access right is given to any of d. And
The cache memory control unit 6a instructed to suspend suspends the generation of the column address and waits until an access resume is instructed.

Further, the cache memory control unit 6b given the interrupt access right omits the generation of the page (row) address and, instead of the cache memory control unit 6a instructed to be interrupted, transfers from the generation of the column address to the transfer. Start.

The cache memory controllers 6c and 6d other than the cache memory controller 6a and the cache memory controller 6b continue in the standby state.

On the other hand, the cache memory control unit 6a waiting for the access restart receives an access restart instruction due to the interruption or termination of the access of the cache memory control unit 6b to which the interrupt access right has been given.

As a result, the cache memory control unit 6a given the instruction to restart the access continues the access similarly to the cache memory control unit 6b given the interrupt access right. By controlling each of the cache memory control units 6a to 6d in this manner, data can be transferred to each of the cache memory control units 6a to 6d without temporarily terminating the page mode.

Hereinafter, a characteristic configuration of the present embodiment will be described with reference to FIG.

In the memory control device configured as described above, that is, a control means (shared memory control unit 4) for controlling memory access to the shared memory unit 5 from the plurality of processors 1a to 1d each having a cache memory is provided. In the memory control device, holding means for holding a page address of the shared memory accessed by one of the processors (the cache memory control units 6a to 6a).
6d), detecting means for detecting the page address of the shared memory requested by its own processor (by functional processing of the cache memory control units 6a to 6d), and the page address detected by the detecting means Determination means (cache memory control unit 6a) for determining whether or not the page address stored in the storage means matches
6d) corresponding to each processor, and the shared memory control unit 4 determines whether each of the page addresses matches, and if any of the determination means determines that the page addresses match, the shared memory control unit 4 The access to the shared memory based on the access request is interrupted, and the data transfer to any one of the cache memories having the same page address is interrupted.

More specifically, a page address for the shared memory unit 5 in the transfer via the common memory bus 3 is held, and a shared memory unit where an access request to a cache memory different from the cache memory in the transfer state is desired. 5 is detected, and when the page address being transferred matches the page address desired by this access request, the access to the shared memory during the data transfer to the cache memory is held and the page address of this page address is held. A parallel cache memory control device capable of shortening the waiting time of a processor due to access competition by causing data transfer to a coincident cache memory to be interrupted, without causing a reduction in transfer efficiency of a memory bus due to overhead caused by interruption and restart of transfer. To configure.

Next, a characteristic memory access control method of this embodiment will be described with reference to the timing chart shown in FIG.

FIG. 2 is a timing chart for explaining the memory access timing of the memory control device shown in FIG. 1. In the transfer using four words as a cache line in the same manner as in FIG. This shows a state in which the transfer is interrupted once at the end of the transfer of the second word of the line, and the second cache line is interrupted by the cache memory B for access.

In the upper part of the figure, the shared memory unit 5, the middle part is the cache memory A (for example, the cache memory 2a), and the lower part is the cache memory B (for example, the cache memory 2).
The memory access timing in b) is shown. Also,
In FIG. 2, the present embodiment will be described by taking as an example a case where an access conflict occurs between the two cache memory controllers 6a and 6b for the cache memories A and B.

As shown in FIG. 2, in an access conflict between the cache memories A and B,
“Access permission” for the shared memory unit 5 is given to the cache memory A as the first cache line, and “standby” is held for the cache memory B.

Then, the cache memory A to which the “access permission” is given generates the row address A to start accessing the shared memory unit 5. Further, a column address is sequentially generated from “A0”, and data read from the shared memory unit 5 is sequentially taken into the buffer memory 2a from the column address A0.

On the other hand, the cache memory B holding "standby" holds the row address A issued from the cache memory A to which "access permission" is given, and compares the row address A with the address requesting access. , And notifies the shared memory control unit 4 of the comparison result. At this time, if the comparison result indicates that the page addresses match, “access suspended” is given to the cache memory A to which “access permission” has been given, and at the same time, "Interrupt permission" is given to the memory B.

On the other hand, the cache memory A detecting the “interruption of access” generates a column address and stores the
Interrupts the reading of read data from.

On the other hand, the cache memory B given "interrupt permission" sequentially generates column addresses from B0,
The data read from the shared memory unit 5 is sequentially taken into the buffer memory 2b from B0.

In FIG. 2, the access right is given to the cache memory A again when the interrupt access of the cache memory B is completed for two words. The cache memory A held by the “interruption of access”
Is given "access resume", and resumes access from the suspended column address A2.

At the same time, "access interruption" is given to the cache memory B, and the access is temporarily suspended in the same manner as the interruption processing for the cache memory A. The cache memory A that has resumed access terminates the access when it reaches the prescribed cache line, and at the same time, gives “access resume” to the cache memory B again.
Thereafter, similarly to the cache memory A, the access ends with the prescribed cache line size.

As is clear from the above description, according to the parallel cache memory control method shown in FIG. 2 showing the present embodiment, that is, the page address of the shared memory accessed by any processor is buffered. Held in memory, detects the page address of the shared memory requested by each processor, determines whether the detected page address matches the page address held in the buffer memory, and determines whether each page address matches. If it is determined that, the shared memory access based on the access request from the processor during data transfer is interrupted,
By interrupting data transfer to any of the cache memories having the same page address, FIG.
As compared with any of the access timing charts shown in FIG. 4, desired data of each processor can be quickly loaded into the buffer memory, and as a result, the processing efficiency of the entire system can be improved.

[0055]

As described above, according to the memory control device of the present invention, the holding means for holding the page address of the shared memory accessed by any of the processors and the shared memory requested by the respective processors are provided. Detecting means for detecting a page address of the memory, and determining means for determining whether or not the page address detected by the detecting means matches the page address held in the holding means, for each processor. The control means interrupts the shared memory access based on an access request from the processor during data transfer when any of the determination means determines that each page address matches, and determines whether any of the page addresses match. Interrupts data transfer to the cache memory of the Without causing transfer efficiency reduction of the memory bus, to shorten the waiting time of each processor generated during access contention can improve the data transfer performance by overhead associated with.

According to the memory control method of the present invention, there is provided a memory control method for controlling memory access to a shared memory from a plurality of processors each having a cache memory, wherein the shared memory is accessed by any one of the processors. The page address of the shared memory requested by each processor is detected, and it is determined whether or not the detected page address matches the page address stored in the buffer memory. If it is determined that each page address matches, interrupt the shared memory access based on an access request from the processor during data transfer,
Since the data transfer to any one of the cache memories having the same page address is interrupted, the waiting time of each processor which occurs at the time of access conflict can be reduced without causing a decrease in the transfer efficiency of the memory bus due to the overhead due to the interruption and restart of the data transfer. There is an effect that the data transfer processing efficiency can be improved by shortening.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a memory control device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining memory access timing of the memory control device shown in FIG. 1;

FIG. 3 is a timing chart illustrating the operation of a conventional memory control device.

FIG. 4 is a timing chart illustrating an operation of a conventional memory control device.

[Explanation of symbols]

 1a processor 1b processor 1c processor 1d processor 2a cache memory 2b cache memory 2c cache memory 2d cache memory 3 common memory bus 4 shared memory control unit 5 shared memory unit

Claims (2)

[Claims] 1. A memory control device comprising control means for controlling memory access to a shared memory from a plurality of processors each having a cache memory, wherein the holding device holds a page address of the shared memory accessed by any one of the processors. Means, a detecting means for detecting a page address of the shared memory requested by its own processor, and determining whether or not the page address detected by the detecting means matches the page address held in the holding means. Means for each of the processors. The control means, when any of the determination means determines that the respective page addresses match, the shared memory access based on an access request from the processor during data transfer. Is interrupted and the page address matches Memory controller, characterized in that to interrupt the data transfer to Kano cache memory. 2. A memory control method for controlling memory access to a shared memory from a plurality of processors each having a cache memory, wherein a page address of the shared memory accessed by any one of the processors is stored in a buffer memory, and The page address of the shared memory requested by the processor is detected, it is determined whether the detected page address matches the page address held in the buffer memory, and when it is determined that each page address matches, A memory control method, comprising interrupting the shared memory access based on an access request from a processor during data transfer, and interrupting data transfer to any cache memory having a matching page address.