JPS62259295A - Refresh control system - Google Patents

Abstract

PURPOSE:To prevent a CPU from the drop of processing capacity due to refreshing operation by refreshing banks other than an objective one and then refreshing the objective bank when an access request exists after the passage of a prescribed time, and when there is no request, refreshing all the bank. CONSTITUTION:When there are 20 memory addresses 2<0>-2<19>, 2<1>, 2<3> bits are decoded and the memory is divided into 4 sections to uniform access to respective banks. Receiving a signal indicating the passage of a regulated time from a counter 9, a control device executes the refreshing operation every memory banks 0-3. The control device is controlled by a processor 1, and when an access request is outputted from the processor to respective banks after the passage of the regulated time, the control device refreshes the banks other than an objective one and then refreshes the objective bank. If there is no access request from the processor, the control device holds the processor and refreshes all the banks after the passage of the prescribed time. Thereby, the simultaneous generation of both requests for access and refresh can be suppressed and the CPU can be prevented from the drop of processing capacity due to the refreshing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a refresh control method, and particularly to a refresh control method suitable for refreshing a dynamic memory without reducing CPU processing performance.

(Prior art) Conventionally, dynamic memory refresh was performed after a specified period of time had elapsed, and when there was basically no memory access, the refresh was activated.However, in reality, a memory access request and a refresh request may occur at the same time. When there is contention, memory access is generally made to wait and refresh is performed with priority.As an example of a device that performs such refresh control, for example, Japanese Patent Laid-Open No. 58-29
As described in Publication No. 197, a memory refresh request signal is periodically applied to the highest priority channel of the DMA control device, and the CPU is held and refreshed.
something is known. Also, JP-A-58-171788
As described in the above publication, in order to avoid a decrease in processing performance due to a memory access request waiting until the refresh operation is completed due to a conflict between a memory access request and a refresh request, memory access requests are made in microinstructions. There is a known device that outputs a refresh request after determining that the execution of an instruction will not occur.

[Problem to be Solved by the Invention J] However, in the former conventional example, there is a problem in terms of system throughput that the overhead of holding the CPU each time during refresh is large and the CPU processing capacity is reduced. In addition, in the latter conventional example, there are actually many types of software, and it is impossible to add unnecessary steps to the software.6 The purpose of the present invention is to solve such conventional IXiJg points. Another object of the present invention is to provide a refresh control method that can avoid conflict between a refresh request and a memory access request and avoid a decrease in CPU processing capacity due to refreshing when refreshing a dynamic memory.

[Means for solving problems]

In order to solve the above problems, the present invention provides a data processing system that includes a memory device configured with a dynamic memory and a processor that outputs a memory access request to the memory device. It has a memory bank configuration in which it is divided into multiple memory banks in order, and a counter for refreshing at a predetermined time (constant period), and a signal indicating the elapse of a predetermined time from the counter, and each memory bank is refreshed. and control means for controlling the execution of memory banks, and when a memory access request is generated from the processor to each memory bank after a predetermined period of time has elapsed, the control means refreshes memory banks other than those accessed at the time of the memory access request. and after executing the refresh,
Refreshing the accessed memory bank, and if the processor receives a stop command and no memory access request is generated, after a predetermined period of time has elapsed, holding the processor and refreshing all memory banks. There are characteristics.

[Effect]

To refresh the memory device, after a predetermined period of time has elapsed, memory banks other than those accessed when a memory access request was issued from the processor are refreshed, and after the refresh is executed, the memory banks that were accessed are refreshed, and the processor is stopped. If no memory access occurs in response to an instruction, the processor is held and all memory banks are refreshed after a predetermined period of time has elapsed.

As a result, conflicts between memory access requests and memory refresh requests can be avoided, and CP due to memory refresh can be avoided.
A decrease in processing capacity can be avoided.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In this embodiment, memory refresh control is performed by dividing the dynamic memory into a plurality of parts and forming banks. FIG. 2 shows a bank selection method for a dynamic memory according to this embodiment.

In FIG. 2, for example, the memory address is between 2° and 21°.
Assuming that there are 20 lines, the 2' and 2'' bits of the lower address are decoded, and the memory is divided into four according to these values.

One of them is called a memory bank, and each is divided into memory bank 1 → memory bank 1 ° memory bank 2 . It is called memory bank 3. According to this division method, since a program is normally executed sequentially, memory access is executed sequentially from memory bank 0 to memory bank 1 → memory bank 2 to memory bank 3 due to the prefetch operation of the object code of the processor. As a result, accesses to each memory bank can be made uniform without concentration of accesses to a certain memory bank.

FIG. 1 is a flowchart of a dynamic memory refresh control operation showing an example of the present embodiment. Hereinafter, it is assumed that a data processing system having a memory device configured with a dynamic memory, which will be explained according to the flowchart of FIG. 1, is powered on. Further, the period (regular time) for controlling memory refresh is, for example, 14t1s.

First, check whether the specified time has elapsed (Step 1)
00). After a predetermined period of time has elapsed, a memory access from the processor is detected (step 101), and if there is a memory access, refreshing of memory banks other than those accessed during the access is performed (step 102), and after the memory access is completed (step 102), 103), perform a refresh of the accessed memory bank (step 1
04).

However, even though the specified time has elapsed, if the next specified time comes without any memory access (steps 101, 105), a hold request signal is output to the processor (step 106). is held (held by the arrival of a hold permission signal) (step 107). If a memory access occurs before the processor is held (step 108), refreshing of memory banks other than those accessed during that access is performed (step 109);
After completing the memory access (step 11o), refresh the accessed memory bank in step 1.
11) Wait for the processor to be held. When a hold permission signal indicating that the processor is held is received from the processor (step 107), the processor is held and no memory access occurs, so refresh all memory banks. (Step 112) If the processor receives a stop command and no HALTL or memory access request occurs, the processor is held at regular intervals and refreshes all memory banks.

Also, during this refresh control operation, the memory bank that has been accessed is not refreshed, and if the processor receives a stop command and no memory access occurs, the processor is held after a specified period of time has elapsed.
All memory banks may be refreshed.

FIG. 3 is a hardware configuration diagram for realizing the refresh control of this embodiment. This shows the configuration of a data processing system having a memory device configured with a dynamic memory.

Further, FIG. 4 shows the prescribed time counter output pulse (signal).

In FIG. 3, ■ indicates a memory access request signal 2, a hold permission signal 3. Send processor address 5 etc.
A processor that controls various devices; 6 a data bus that transfers data between the processor l and memory banks 29 to 32; 8 a clock 7 for a specified time (here, 14
11 is a refresh activation device that outputs a refresh activation signal 12.13.34.

14 is a refresh cycle end signal 10. Refresh signal 15. 17 is a decoder that decodes the address from processor l and outputs signal 18; 20 is a control signal generator that outputs memory control signals 21 to 24 that control memory banks; 25 is a refresh address counter that counts refresh addresses according to refresh address update signal 16 and outputs refresh address 26; 27 is an address selector that selects memory refresh address 26 and processor address 5 and outputs memory address 28; 29; ~3
Reference numeral 2 represents a memory bank, and reference numeral 33 represents a memory control signal generator that generates the memory control signal 19.

To access memory banks 29 to 32 from processor 1, when a memory access request signal (memory read signal or memory write signal) 2 is generated, memory control signal generator 33 generates memory control signal 19, and processor address 5 is generated. Based on the result of decoding the lower address of , by the decoder 17, the control signal sending device 20 determines to which memory bank 29-32 the output is to be made, and one memory bank is given through the memory control signals 21-24. , processor address 5 is selected by address selector 27 and provides memory address 28 to the memory, and data transfer between processor 1 and memory banks 29 to 32 is performed through data bus 6.

A method of refreshing memory banks 0 to 3 (29 to 32) will be described below. The specified time counter 8 counts based on the clock 7, and transmits a pulse signal 9 shown in FIG. 4 to the refresh starting device 11 when 1411 seconds have elapsed. The refresh activation device 11 activates the following three types of refresh.

First, when a memory access request 2 comes after 141Li has elapsed, a refresh activation signal 12 is output. Second
outputs the refresh start signal 13 when the memory access request signal 2 ends after 1411 seconds have elapsed.

The third method is to output a hold request signal 4 to the processor 1, wait for the processor 1 to be held, and wait for the processor 1 to be held. If the memory access request signal 2 comes before the memory access request signal 2 is held, the refresh activation signal 12 is output, and when the access is completed, the refresh activation signal 13 is output, the processor l is held, and the hold permission signal 3 is output from the processor 1. When it returns, a refresh activation signal 34 is output.

These refresh activation signals are cleared by signal 10 indicating the end of the refresh cycle. The above three refreshes will hereinafter be referred to as a first refresh, a second refresh, and a third refresh.

The refresh signal generator 14 receives the refresh activation signals 12, 13, and 34 as input, and generates the refresh signal 15 based on these refresh activation signals, as well as a refresh cycle end signal lO for clearing the refresh activation signal, and a refresh cycle end signal lO for clearing the refresh activation signal. A refresh address update signal 16 that updates the value of the address counter 25 is output.

The control signal sending device 20 generates a memory control signal generating device 33 based on the refresh signal 15 and the memory access request signal 2 of the processor 1 based on the contents decoded by the decoder 17 of the lower address 2' and 2'' bits of the processor address 5. To which memory bank the memory control signal 19 generated in
5 is output, and the refresh by the refresh start signal 13 outputs the refresh signal 15 to the memory bank where the memory access was made after the memory access is completed, and the refresh by the refresh start signal 34 gives the refresh signal 15 to all memory banks. , a memory control signal 19 resulting from a memory access from processor l is given to the memory bank to which the memory was accessed. Note that refresh signals and memory control signals for each memory bank 29-32 are provided through memory control signals 21-24.

FIG. 5 is a schematic timing chart of the first and second refreshes according to this embodiment. Here, all signals are assumed to be "H" and valid. The first and second refreshes will be explained below using the timing chart of FIG.

After the specified time 14t1s has elapsed, signal 9 becomes valid, and then memory access request 2 becomes valid, refresh activation signal 12 becomes valid, refresh activation signal 15 is output, and memory bank 0 is accessed by decoder 17. If so.

Memory bank 0 (29) is memory accessed, and other memory banks 1 to 3 (30 to 32) are refreshed. When the memory access to memory bank 0 (29) is completed, the refresh activation signal 13 becomes valid, the refresh activation signal 15 is output, and the memory bank 0 (29) is activated.
29) Execute the refresh. After execution of the first and second refreshes, the refresh start signal is cleared by the refresh cycle end signal 10, and the refresh address is updated by the refresh address update signal 16.

FIG. 6 is a schematic timing chart of the third refresh according to this embodiment. Here, all signals are "H" and valid. The third refresh will be explained below using the timing chart of FIG.

After the first specified time 1411s has elapsed, when another 14IIs has elapsed without any memory access request, the refresh activation device 11 outputs the hold request signal 4 to the processor 1, and the hold permission signal 3 is returned from the processor l. When this occurs, the refresh start signal 34 is enabled, the refresh signal 15 is output, and all memory banks are refreshed. After the refresh is executed, the hold request signal 4 and refresh start signal 34 are cleared by the refresh cycle end signal 10, and the refresh address is updated by the refresh address update signal 16.

In this way, in this embodiment, dynamic memory refresh refreshes memory banks other than the accessed memory bank when a memory access request occurs, so that there is no conflict between the memory access request and the refresh request. After the memory access is completed, the memory bank that was accessed is refreshed, so even if there are consecutive accesses to the same memory bank, if the refresh is executed between the next memory access, there will be no conflict with memory access requests. , when the processor receives a stop command and goes into HALTL, the processor is held and refreshed, but there are 0 or more things that do not affect the processing capacity of the processor.Refresh control that does not reduce the processing capacity of the processor It becomes possible.

〔Effect of the invention〕

As described above, according to the present invention, conflict between a refresh request and a memory access request can be avoided in dynamic memory refresh, and refresh control can be performed without reducing CPU processing capacity due to refresh.

[Brief explanation of drawings]

FIG. 1 is a flowchart of refresh control operation showing one embodiment of the present invention, FIG. 2 is a diagram for explaining a memory bank selection method, and FIG. 3 is hardware for realizing refresh control of this embodiment. FIG. 5 is a schematic timing chart of the first and second refresh according to the present embodiment; FIG. 6 is a schematic timing chart of the third refresh according to the present embodiment. It is. 1: Processor, 8: Prescribed time counter, 11: Refresh activation device, 14: Refresh signal generation device, 17: Decoder, 2o: Control signal sending device, 25: Refresh address counter. 27: Address selector, 29-32: Memory bank,
33: Memory control signal generator. Figure 2

Claims (1)

[Claims] 1. In a data processing system having a memory device constituted by a dynamic memory and a processor that outputs a memory access request to the memory device, the dynamic memory is divided into a plurality of memory banks in order according to lower address values. and a counter for counting a predetermined time, and a control means for controlling the execution of refresh for each memory bank in response to a signal from the counter indicating the elapse of a predetermined time, and the control means controls each memory bank from the processor. When a memory access request to a memory bank occurs, refresh of the memory bank other than the one accessed at the time of the memory access request is executed, and if the processor receives a stop instruction and no memory access request occurs, a predetermined period of time elapses. After that, the refresh control method is characterized in that the processor is held and all memory banks are refreshed.