JP2008210513A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To operate an external access in an access time of apparently one time of memory core operation, even when a refresh operation conflicts an external access request. <P>SOLUTION: This semiconductor memory is equipped with: a memory core for dividing a plurality of bit data of the same address into a plurality of memory cell blocks and storing them; an internal commend generating circuit for outputting an internal command signal based on an external command; a first core control signal generating circuit for outputting the first core control signal to activate the memory core based on the internal command signal; and a control circuit which can control the refresh operation for the plurality of memory cell blocks independently of each other and controls one memory cell block and another memory cell block so that they perform the refresh operation with different timing. The control circuit outputs a second core control signal for activating the memory core based on the refresh request signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that performs a refresh operation.

  As long as a dynamic random access memory (DRAM) memory core is used, the refresh operation must be performed when necessary. During the refresh operation, the operation area cannot be accessed. As a result, when performing a refresh operation, if it is desired to access, it must wait until the refresh operation is completed.

  If an attempt is made to operate with SRAM (static random access memory) control in which a refresh request is not input from the outside, a refresh request is periodically generated internally. At this time, if there is an access request from the outside, the requested access is performed after the refresh operation is performed, so that it seems that it takes time equivalent to two memory core operations even with one access.

JP 2001-093277 A Japanese Patent Laid-Open No. 04-132093 Japanese Patent Laid-Open No. 2000-076871

  An object of the present invention is to allow external access to operate with an access time equivalent to one memory core operation even when a refresh operation and an external access request at that time compete.

  According to one aspect of the present invention, a memory core for distributing and storing a plurality of bit data of the same address in a plurality of memory cell blocks, and an internal command generation circuit for outputting an internal command signal based on an external command And a first core control signal generating circuit for outputting a first core control signal for activating the memory core based on the internal command signal, and independently for each of the plurality of memory cell blocks A control circuit that can control a refresh operation and controls one memory cell block and another memory cell block to perform refresh operations at different timings, and the control circuit is based on a refresh request signal And a second core control signal generating circuit for outputting a second core control signal for activating the memory core. When a read request signal is input to a memory cell block during a refresh operation, the second core control signal is deactivated after the refresh operation is completed, and a read operation is performed based on the read request signal. A semiconductor memory device is provided.

  According to another aspect of the present invention, a memory core for distributing and storing a plurality of bit data of the same address in a plurality of memory cell blocks, and an internal command generation for outputting an internal command signal based on an external command A circuit, a first core control signal generating circuit for outputting a first core control signal for activating the memory core based on the internal command signal, and activating the memory core based on a refresh request signal A second core control signal generating circuit for outputting a second core control signal for generating a memory cell block, and a memory cell block for outputting a select signal for selecting a memory cell block to be refreshed to the selector in response to the refresh request signal A memory that selectively selects a first control signal and the second core control signal based on a selection circuit and the select signal; And a selector for outputting the second core control signal to the memory of the first memory cell block in a refresh operation for the first memory cell block of the plurality of memory cell blocks. And supplying the first core control signal to a memory core of a memory cell block other than the first memory cell block in a read operation for a memory cell block other than the first memory cell block. A featured semiconductor memory device is provided.

  As described above, since a plurality of memory cell blocks can be independently refreshed, an external access request and a refresh operation can be processed simultaneously. That is, it is possible to perform a refresh operation on some memory cell blocks at the same timing and to access other memory cell blocks from the outside. Thereby, a read operation can be realized with a high-speed access time for one memory core operation.

FIG. 1 shows a schematic diagram of a memory core of a semiconductor memory device of the present invention.
The memory core stores a plurality of bit data at the same address in a plurality of memory cell blocks (hereinafter referred to as blocks) BLK1 to BLK4. For example, 16 bits can be stored in the same address, and each of the four blocks BLK1 to BLK4 can store 4 bits. Blocks BLK1 to BLK4 are memory cell arrays for storing external data. Each of the blocks BLK1 to BLK4 includes a memory cell 104, a word decoder 103, a column decoder 102, and a selector 101 for an input signal. Each block BLK1 to BLK4 is further divided into a set of a plurality of word decoders 103 and memory cells 104.

  The block BLK5 is a memory cell array for storing operation results for a plurality of bit data having the same address. Details of the calculation method will be described later with reference to FIGS. Similarly to the blocks BLK1 to BLK4, the block BLK5 includes a memory cell 104, a word decoder 103, a column decoder 102, and a selector 101 for an input signal.

  There are two control signals, the first control signal SIG1 and the second control signal SIG2, which are respectively input to the selectors 101 of the blocks BLK1 to BLK5. Select signals SEL1 to SEL5 are input to each selector 101, respectively. When the select signals SEL1 to SEL5 are low level, the output of the selector 101 is the first control signal SEL1, and when the select signals SEL1 to SEL5 are high level, the output of the selector 101 is the second control signal SIG2. . The select signals SEL1 to SEL5 are independent signals.

  The control signals SIG1 and SIG2 include a write request signal, a read request signal, an address, data, and the like, respectively. For example, the write request signal and the read request signal are expressed by a chip enable signal and a write enable signal.

  The word decoder 103 specifies a row address according to the address supplied from the selector 101. The column decoder 102 specifies the column address according to the address supplied from the selector 101. The memory cell 104 can write / read data to / from the specified row address and column address.

  Normally, the second control signal SIG2 is inactive, and only the first control signal SIG1 controls the memory core. During normal reading, the select signals SEL1 to SEL4 are at a low level, the select signal SEL5 is at a high level, and the block BLK5 is inactive. During normal writing, all the select signals SEL1 to SEL5 are at a low level, and writing is performed to all the blocks BLK1 to BLK5.

  When performing the refresh operation, the blocks BLK1 to BLK5 are sequentially refreshed in units of blocks, and only the select signal corresponding to the block becomes high level. The refresh operation is given by the second control signal SIG2, and only the block whose select signal is at a high level performs the refresh operation.

  Further, if a write signal other than refresh is applied to the second control signal SIG2 asynchronously with the first control signal SIG1, only the block whose select signal is at the high level operates according to the second control signal SIG2, and the other blocks Operates according to the first control signal.

  In the present embodiment, a plurality of control signals for activating and controlling each block are provided. The selector 101 can select a control signal system for each block. Further, a plurality of blocks can be activated by a control signal having the same or different timing, and the activation timing and / or activation time of each block can be controlled to be different.

FIG. 2A shows a diagram of a write parity operation sequence at the time of data writing.
An example will be described in which 1-bit data DQ01 to DQ04 are written in the blocks BLK1 to BLK4, respectively. Write data DQ01 to DQ04 input from the outside are written to the blocks BLK1 to BLK4, respectively.

  The exclusive OR circuit (Exclusive-OR) 201 inputs data DQ01 and DQ02, calculates exclusive OR, and outputs the result. The exclusive OR circuit 202 inputs the data DQ03 and DQ04, calculates the exclusive OR, and outputs the result. The exclusive OR circuit 203 receives the output of the exclusive OR circuit 201 and the output of the exclusive OR circuit 202, calculates the exclusive OR, and outputs the result. The output of the exclusive OR circuit 203 is written in the block BLK5.

  FIG. 2B shows a circuit diagram of the exclusive OR circuits 201 to 203. The first input signal IN1 is input to a logic negation circuit (inverter) 211. The input of the inverter 212 is connected to the output of the inverter 211. The second input signal IN2 is input to the inverter 215. In the p-channel MOS transistor 213, the gate is connected to the output of the inverter 212, the source is connected to the line of the second input signal IN2, and the drain is connected to the line of the output signal OUT. The n-channel MOS transistor 214 has a gate connected to the output of the inverter 211, a drain connected to the line of the second input signal IN2, and a source connected to the line of the output signal OUT. In the p-channel MOS transistor 216, the gate is connected to the output of the inverter 211, the source is connected to the output of the inverter 215, and the drain is connected to the line of the output signal OUT. The n-channel MOS transistor 217 has a gate connected to the output of the inverter 212, a drain connected to the output of the inverter 215, and a source connected to the line of the output signal OUT.

  FIG. 2C shows a truth table of the exclusive OR circuit shown in FIG. The output signal OUT becomes 0 when the input signals IN1 and IN2 are the same, and becomes 1 when they are different.

  In FIG. 2A, two-stage 2-input exclusive OR circuits 201 to 203 output 1-bit operation results based on 4-bit input data DQ01 to DQ04. At this time, if there is an odd number of “1” data in the 4-bit input data DQ01 to DQ04, “1” is output, and if it is an even number, “0” is output. Hereinafter, this calculation result is referred to as write parity.

  The data DQ01 to DQ04 are, for example, “0”, “1”, “0”, “0”. In this case, the exclusive OR circuits 201 to 203 output “1”, “0”, and “1”, respectively. In the block BLK5, “1” that is the output of the exclusive OR circuit 203 is written as a write parity.

FIG. 3A shows a data correction sequence at the time of data reading.
An example will be described in which 1-bit data DQ01 to DQ04 are read out from the blocks BLK1 to BLK4 and corrected. Two inputs of the exclusive OR circuit 311 are connected to a data line (bit line) of the block BLK1 and a data line of the block BLK2. Two inputs of the exclusive OR circuit 312 are connected to the data line of the block BLK3 and the data line of the block BLK4. Two inputs of the exclusive OR circuit 313 are connected to the output of the exclusive OR circuit 311 and the output of the exclusive OR circuit 312. Two inputs of the exclusive OR circuit 314 are connected to the output of the exclusive OR circuit 313 and the data line of the block BLK5. Hereinafter, the output of the exclusive OR circuit 313 is referred to as read parity. The exclusive OR circuit 314 compares the read parity and the write parity. Both the read parity and the write parity are obtained by the same calculation using an exclusive OR circuit.

  The data correction circuit 301 will be described. The data line 307 of the block BLK3 is connected to the input of the inverter 306. The three-point switch 302 has a common terminal 303, a first terminal 305, and a second terminal 304. The first terminal 305 is connected to the data line 307 of the block BLK3. The second terminal 304 is connected to the output of the inverter 306. The inverter 306 is an inverting circuit that performs logical inversion of input data. The common terminal 303 outputs 1-bit data DQ03. The switch 302 connects the common terminal 303 to either the first terminal 305 or the second terminal 304 in accordance with the output signal 308 of the exclusive OR circuit 314.

  For example, when the block BLK3 is refreshing, reading is performed on the blocks BLK1, BLK2, BLK4, and BLK5. At this time, read data is not output from the block BLK3, and the data line 307 retains the level at the previous access. Therefore, the value of only that bit is uncertain at the same address. Therefore, the write parity of the same address previously written in the block BLK5 at the time of writing is simultaneously read. The exclusive OR circuit 314 compares the read parity and the write parity. If the read parity and the write parity match, the data on the data line 307 is output to the outside as data DQ03. If they do not match, it can be seen that only one bit of the blocks BLK1 to BLK4 is missing (indeterminate). That bit should be the bit of the block BL3 performing the refresh operation. Therefore, the bit data of the data line 307 of the block BLK3 is inverted by the data correction circuit 301 to perform data correction and output to the outside as data DQ03. The other data DQ01, DQ02, and DQ04 are data read from the blocks BLK1, BLK2, and BLK4.

  For example, it is assumed that “0”, “1”, “0”, and “0” are written in the blocks BLK1 to BLK4, respectively. In these data, since the number of “1” is an odd number, “1” is written as write parity in the block BLK5. Here, it is assumed that the data line 307 of the block BLK3 maintains indefinite data “1”. In this case, the exclusive OR circuit 313 outputs “0” as the read parity because the number of data “1” on the four data lines is an odd number. Since the read parity and the write parity are different, the exclusive OR circuit 314 outputs “1” as the output signal 308. As a result, the switch 302 connects the common terminal 303 and the second terminal 304. As a result, the data “1” on the data line 307 is logically inverted by the inverter 306 and the data “0” is output as the data DQ03.

  As described above, even if the block BLK3 is being refreshed and data cannot be read from the block BLK3, the write parity is read from the block BLK5, and the correct data is corrected by correcting the data DQ03 of the block BLK3 as necessary. DQ01 to DQ04 can be output. Thereby, even when the block BLK3 is being refreshed, the read data can be output to the outside at high speed without waiting for the read.

  Note that when the block BLK5 in which the write parity is written is performing the refresh operation, the data correction circuit 301 does not perform data correction. The data DQ01 to DQ04 are data read from the blocks BL1 to BL4.

  FIG. 3B is a circuit diagram illustrating a specific configuration of the data correction circuit 301. Inverter 320 outputs a logic inversion signal of select signal SEL5. A negative logical product (NAND) circuit 321 inputs the signal 308, the select signal SEL3, and the output of the inverter 320, and outputs a negative logical product. The inverter 322 outputs a logic inversion signal of the NAND circuit 321. The input of the inverter 325 is connected to the data line 307. The p-channel MOS transistor 323 has a gate connected to the output of the inverter 322, a source connected to the data line 307, and a drain connected to the output data line 328. The n-channel MOS transistor 324 has a gate connected to the output of the NAND circuit 321, a drain connected to the data line 307, and a source connected to the output data line 328. The p-channel MOS transistor 326 has a gate connected to the output of the NAND circuit 321, a source connected to the output of the inverter 325, and a drain connected to the output data line 328. The n-channel MOS transistor 327 has a gate connected to the output of the inverter 322, a drain connected to the output of the inverter 325, and a source connected to the output data line 328. The output data line 328 outputs data DQ03 (FIG. 3A).

  FIG. 4 is a block diagram of a control signal generation circuit related to the output from the memory core. This control signal generation circuit is connected to the left of the memory core in FIG. A data correction circuit 401 is connected to each of the blocks BLK1 to BLK4. The data correction circuit 401 corresponds to the data correction circuit 301 in FIG. The data operation circuit 402 corresponds to the exclusive OR circuits 311 to 313 in FIG. The data comparison circuit 403 corresponds to the exclusive OR circuit 314 in FIG. The data correction circuit 401 of each block BLK1 to BLK4 performs data correction of the data lines of each block BLK1 to BLK4 in response to the select signals SEL1 to SEL4. Among the select signals SEL1 to SEL4, the blocks BLK1 to BLK4 corresponding to the high level perform refresh. Therefore, the data correction circuit 401 is subject to data correction if the input select signal is at a high level, and performs data correction if the write parity and the read parity do not match by comparison of the data comparison circuit 403. The data correction circuit 401 outputs read data to the outside.

  FIG. 5A is a schematic diagram illustrating the operation of the semiconductor memory device. A case where an external write command WR0 is input at timing t1 and an internal refresh request signal is generated at timing t11 will be described. Since the write command WR0 is earlier than the refresh request, data is written to the blocks BLK1 to BLK4 according to the write command WR0. Write parity is written in the block BLK5. In the period T1 after the timing t11, the refresh request is held. This write control is performed by the control signal SIG1 in FIG. In the block BLK2, the refresh operation 501 starts when the operation of the write command WR0 is completed.

  Thereafter, external write commands WR1, WR2 and external read command RD0 are input at times t2, t3, t4, respectively. Blocks BLK1, BLK3 to BLK5 perform operations of external commands WR1, WR2, RD0. The block BLK2 performs the operations of the external commands WR1 and WR2 after the refresh operation 501 is completed. When the read command RD0 is input, the block BLK2 is in the operation of the write command WR2. Therefore, the write parity is read from the block BLK5, and if the write parity and the read parity do not match, the data on the data line of the block BLK2 is corrected. Hereinafter, the reading using the write parity and the read parity is referred to as pseudo reading.

  In block BLK2, dummy read 502 is performed after the write command WR2 is operated. The dummy read 502 is a dummy operation performed in the control signal generation circuit of FIG. 6 described later, and the block BLK2 does not perform a read operation. Details will be described later. In the period T2 from the above refresh operation 501 to the dummy read 502, only the block BLK2 is controlled by the second control signal SIG2, and the other blocks are controlled by the first control signal SIG1.

  Next, a case where the external read command RD1 is input at timing t5 will be described. In the block BLK2, the immediately preceding dummy read 502 is performed by the second control signal SIG2. At this time, if the start of the read command RD1 is detected at the timing t5 and the second control signal SIG2 is switched to the first control signal SIG1, a malfunction may occur in the block BLK2 or an operation delay may occur. . Therefore, for the read command RD1, pseudo reading is performed without reading the block BLK2. Then, the end of the operation of the read command RD1 is detected, and switching from the second control signal SIG2 to the first control signal SIG1 is performed. As a result, the read command RD2 at the next timing t6 can be read from the blocks BLK1 to BLK4 at high speed and appropriately. Details of this will be described later with reference to FIGS. If the read operation does not compete with the refresh operation, the operation result storage block BLK5 is deactivated and reading is performed from other memory cell blocks.

  Next, at timing t12, an internal refresh request is generated, and the block BLK3 performs a refresh operation 503. A case where the external read command RD3 is input at the timing t7 during the refresh operation 503 will be described. In this case, pseudo reading is performed, and data of the data line of the block BLK3 is corrected as necessary. In the block BLK3, the dummy read 504 is performed after the refresh operation 503. In the period T3 from the refresh operation 503 to the dummy read 504, only the block BLK3 is controlled by the second control signal SIG2.

  When a write request signal for the block BLK3 is input during the pseudo read operation, the write request signal is held, and the write request held after the pseudo read operation is completed. Perform the operation corresponding to the signal.

  FIG. 5B is a schematic diagram illustrating another operation of the semiconductor memory device. A case where an external read command RD4 is input at timing t21 and an internal refresh request is generated at timing t31 will be described. Since the read command RD4 is earlier than the refresh request, data is read from the blocks BLK1 to BLK4 according to the read command RD4. In the period T11 after the timing t31, the refresh request is held. In the block BLK2, the refresh operation 511 starts when the operation of the read command RD4 is completed.

  Thereafter, external read commands RD5 and RD6 are input at times t22 and t23, respectively. Blocks BLK1, BLK3 to BLK5 correspond to external commands RD5 and RD6 and perform pseudo reading. The block BLK2 performs two dummy reads 512 and 513 after the refresh operation 511 is completed. In the period T12, only the block BLK2 is controlled by the second control signal SIG2.

  Next, a case where the external write command WR3 is input at timing t24 will be described. Data is written to the blocks BLK1 to BLK4, and write parity is written to the block BLK5.

  Next, at timing t32, an internal refresh request is generated, and the block BLK3 performs a refresh operation 514. The case where the external write command WR4 is input at the timing t25 during the refresh operation 514 and then the external write commands WR5 and WR6 are input at the timings t26 and t27 will be described. At this time, corresponding to the commands WR4, WR5 and WR6, data is written to the blocks BLK1, BLK2 and BLK4, and write parity is written to the block BLK5. In the block BLK3, after the refresh operation 514 is completed, a write operation corresponding to the write commands WR4 to WR6 is performed. The generation cycle time of the external write commands WR4 to WR6 is longer than the execution cycle time of the corresponding blocks BLK1 to BLK5. Therefore, in the block BLK3, the operations of the commands WR4 and WR5 are delayed from the operations of the other blocks, but the operation of the command WR6 catches up with the operations of the other blocks. Even when the refresh operation 514 is performed, writing can be performed at high speed without delay from an external command. In the period T13, only the block BLK3 is controlled by the second control signal SIG2.

  FIG. 6 shows a block diagram of a control signal generation circuit related to the input to the memory core. This control signal generation circuit assumes an asynchronous SRAM interface and is connected to the left of the memory core in FIG. An internal refresh request (OSC) signal generation circuit 604 automatically generates a refresh request periodically using a ring oscillator.

  During normal writing, an external command EXTC, an address ADR, mask information MSK, and write data IND are input from the outside. The mask information MSK is information for selectively instructing an upper byte and / or a lower byte. The external command EXTC is input to the internal command generation circuit 601. The internal command generation circuit 601 generates a first internal command INTC1 and outputs it to the first core control signal generation circuit 602. The first core control signal generation circuit 602 generates a first core control signal COC1 (corresponding to the first control signal SIG1 in FIG. 1) and outputs it to the selector 621 (same as the selector 101 in FIG. 1). Control the memory core.

  At this time, the selectors 621 of the respective blocks all select the first core control signal COC1 as described with reference to FIG. At this time, the first core control signal generation circuit 602 outputs the first core activation state signal COS1 while the core is activated by the first core control signal COC1. The mask information MSK has a role of invalidating the writing operation at that time, and is supplied to the buffer 607 and the first core control signal generation circuit 602 as the first mask information MSK1. The first core control signal generation circuit 602 outputs a core control signal COC1 and a core activation state signal COS1 according to the internal command INTC1 and mask information MSK1. The address ADR is supplied to the selector 622 as the first address ADR1 through the buffer 607. The first address ADR1 is a set with the first core control signal COC1, and designates an address at the time of writing. The data operation circuit 609 receives the input data IND, calculates the write parity (see FIG. 2A), and supplies the first input data IND1 to the selector 623. The first input data IND1 is written into the memory cell at the first address ADR1. At this time, the data operation circuit 609 performs the write parity operation based on the input data IND, and writes the result in the operation memory cell block BLK5.

  The selector 621 selects the first core control signal COC1 or the second core control signal COC2 according to the select signals SEL1 to SEL5, and outputs it to the memory core. The selector 622 selects the first address ADR1 or the second address ADR2 according to the select signals SEL1 to SEL5, and outputs it to the memory core. The selector 623 selects the first data IND1 or the second data IND2 according to the select signals SEL1 to SEL5, and outputs it to the memory core. The three selectors 621 to 623 correspond to one selector 101 in FIG. There are three sets of selectors 621 to 623 corresponding to the number of blocks BLK1 to BLK5.

  Next, the refresh operation will be described. A refresh request (OSC) signal generation circuit 604 periodically outputs a refresh request signal OSC. Internal command generation circuit 601 outputs signal ATD when external command EXTC is input. At this time, assuming that the timings of the refresh request signal OSC and the execution of the external command EXTC overlap, the command-refresh comparison circuit 603 always determines which of the signal ATD and the signal OSC is earlier.

  If the command-refresh comparison circuit 603 determines that the refresh request signal OSC is earlier, it generates a refresh request signal REF. When the refresh request signal REF is input, the second core control signal generation circuit 606 outputs the second core activation state signal COS2 and outputs the second core control signal COC2 (the second control signal in FIG. 1). (Corresponding to SIG2) is output to the selector 621. The refresh request signal REF is input to the refresh block selection circuit 611 at the same time. The refresh block selection circuit 611 sets one of the select signals SEL1 to SEL5 for the selectors 621, 622, and 623 to a high level. Thus, only one block BLK1 to BLK5 selected by the select signals SEL1 to SEL5 performs the refresh operation. For example, the blocks BLK1 to BLK5 are sequentially refreshed. If it is determined that the refresh request signal OSC is later than the external command EXTC, the command-refresh comparison circuit 603 waits for the output of the refresh request signal REF until the first core activation state signal COS1 is reset.

  Next, a case where there is a write request command EXTC from the outside during the refresh will be described. During the refresh, similarly to the first core control signal generation circuit 602, the second core control signal generation circuit 606 outputs the second core activation state signal COS2. The second core activation state signal COS2 is input to the internal command holding circuit 605. While the second core activation state signal COS2 is being output, the internal command holding circuit 605 holds the first internal command INTC1 generated during the refresh. The internal command holding circuit 605 outputs the held command as the second internal command INTC2 when the refresh operation is completed and the second core activation state signal COS2 is reset.

  At this time, when the internal command holding circuit 605 outputs the held internal command INTC2, there is a case where the next external command EXTC is generated and the corresponding internal command INTC1 must be held. Since one holding circuit cannot simultaneously output and hold two commands, two holding circuits are used. The counter counts the held command and selects which of the two holding circuits holds it. The other counter counts the output signal and then selects which holding circuit to output from.

  FIG. 7 is a circuit diagram of an internal command holding circuit 605 including two holding circuits, and FIG. 8 shows its operation waveform. The internal command holding circuit 605 has two holding circuits 701 and 702. The counter 721 outputs a signal / CNTA that inverts the state every time the pulses 501 and 502 of the first internal command INTC1 are input. Inverter 723 outputs signal CNTA obtained by logically inverting signal / CNTA. The counter 722 outputs / CNTB whose state is inverted every time the pulses 506 and 507 of the second internal command INTC2 are input. Inverter 724 outputs a signal CNTB obtained by logically inverting signal / CNTB.

  First, the holding circuit 701 will be described. A NAND circuit (NAND) circuit 711 receives the second core activation state signal COS2 and the signal CNTB, and outputs a NAND. The NAND circuit 712 receives the first internal command INTC1, the signal CNTA, and the output of the NAND circuit 711, and outputs a negative logical product. The NAND circuit 713 receives the output of the NAND circuit 712 and the output of the NAND circuit 714 and outputs a signal n01. The delay line 717 delays the signal n03 and outputs it to the NAND circuit 714. The NAND circuit 714 inputs the signal n01 and the output of the delay line 717, and outputs a negative logical product. The NAND circuit 715 receives the output of the NAND circuit 711 and the output signal n03 of the NAND circuit 716, and outputs a negative logical product. The NAND circuit 716 receives the signal n01 and the output of the NAND circuit 715, and outputs a signal n03.

  Next, the holding circuit 702 will be described. The holding circuit 702 has a configuration similar to that of the holding circuit 701. A difference between the holding circuit 702 and the holding circuit 701 will be described. The NAND circuit 711 receives the second core activation state signal COS2 and the signal / CNTB. The NAND circuit 712 receives the first internal command INTC1, the signal / CNTA, and the output of the NAND circuit 711. The output signal of the NAND circuit 713 is n02, and the output signal of the NAND circuit 716 is n04.

  A negative logical sum (NOR) circuit 725 receives the signal n03 and the signal n04 and outputs a second internal command INTC2. The counter 721 controls the timing at which the holding circuits 701 and 702 hold commands alternately. The counter 722 controls the timing at which the holding circuits 701 and 702 alternately output commands.

  In FIG. 8, a first internal command INTC1, pulses 501 and 502 are, for example, write commands. In the second core activation state signal COS2, refresh is performed in the period 503, a write operation corresponding to the write command 501 is performed in the period 504, and a write operation corresponding to the write command 502 is performed in the period 505.

  The operation will be described with reference to FIGS. The first internal command INTC1 and the second core activation state signal COS2 are input to the internal command holding circuit 605 in FIG. Signals CNTA and / CNTA are the outputs of the counter 721 counted by the first internal command INTC1. Signals n03 and n04 are the outputs of the two holding circuits 701 and 702, respectively. The second internal command INTC2 is a signal obtained by synthesizing the signals n03 and n04 by the NOR circuit 725. Signals CNTB and / CNTB are outputs of the counter 722 counted by the second internal command INTC2. The second core activation state signal COS2 is a low level signal in the activation period. When the first internal command INTC1 is generated while this signal is at a low level, one of the signals CNTA and / CNTA becomes a high level. The holding circuit 701 or 702 that has become high level holds the first internal command INTC1, and the signal n01 or n02 becomes high level. In this state, when the second core activation state signal COS2 becomes high level, the held command becomes the signal n03 or n04 and becomes the second internal command INTC2. The second internal command INTC2 inverts the signals CNTB and / CNTB.

  Next, a description will be given with reference to FIG. While the second core activation state signal COS2 is output, the address and mask information holding circuit 608 holds the address ADR and mask information MSK used by the first internal command INTC1 itself, and the data holding circuit 610 Holds input data IND. When the second internal command INTC2 is output, the information held in the address and mask information holding circuit 608 and the data holding circuit 610 is received as the second address ADR2, the second mask information MSK2, and the second mask information MSK2, respectively. 2 is output as data IND2. The second core control signal generation circuit 606 outputs a second core control signal COC2 and a second core activation state signal COS2 in response to the second internal command INTC2 and the second mask information MSK2. While the second core activation state signal COS2 is output, the refresh block selection circuit 611 maintains and outputs the select signals SEL1 to SEL5. Following the refresh operation, the blocks BLK1 to BLK5 selected by the select signals SEL1 to SEL5 perform the operation of the second internal command INTC2, the second address ADR2, the second mask information MSK, and the second data IND2. To do.

  When the next external write command EXTC is generated during the operation of the second internal command INTC2, each information is similarly held, and after the operation being executed at that time is finished, the second internal write command EXTC is held. Command INTC2 is executed. Therefore, as long as the external write command EXTC is generated while the second core activation state signal COS2 is output, the blocks BLK1 to BLK5 selected by the select signals SEL1 to SEL5 are different from the first internal command INTC1. The second internal command INTC2 is continuously executed asynchronously. If the execution cycle of the second internal command INTC2 is shorter than the generation cycle of the external command EXTC, the execution of the second internal command INTC2 will eventually end (see FIG. 5B).

  The reading time will be described. Until the control signal is input to the memory core, it is almost the same as that at the time of writing. The difference is that a signal corresponding to the second core control signal COC2 at the time of writing is not output except during the refresh operation. At this time, the second core control signal generation circuit 606 itself is operating. This state is a dummy lead (see FIGS. 5A and 5B). In addition, during the period when the second core activation state signal COS2 is not output, the refresh block selection circuit 611 puts the select signal SEL5 for the operation result writing block BLK5 into a non-selected state.

  Next, the operation of FIG. 5A will be described. In the block BLK2, a write operation by the second core control signal COC2 after the refresh operation 501 is performed. Then, consider a case where the signal for controlling the block BLK2 is switched from the second core control signal COC2 to the first core control signal COC1. After that, when the read command RD1 is generated immediately from the outside at timing t5, normally, the access from the read command to the memory core must be performed at the fastest speed, so that the core control signal may not be switched in time.

  Therefore, the refresh block selection circuit 611 in FIG. 6 is configured as shown in FIG. According to this configuration, the block BLK2 is controlled by the second core control signal COC2 until the next one read command RD1 is completed.

  FIG. 9 is a circuit diagram of the refresh block selection circuit 611, and FIG. 10 shows its operation waveform. The circuit configuration will be described with reference to FIG. The delay line 901 delays the second core activation state signal COS2. The NAND circuit 902 inputs the second core activation state signal COS2 and the output of the delay line 901, and outputs a negative logical product. The inverter 903 logically inverts the output of the NAND circuit 902 and outputs a signal n01.

  The RS flip-flop 904 includes NAND circuits 905 and 906. Inverter 907 logically inverts signal CL. The NAND circuit 905 receives the signal n01 and the output of the NAND circuit 906, and outputs a negative logical product. The NAND circuit 906 receives the output of the NAND circuit 905 and the output of the inverter 907 and outputs a negative logical product. The inverter 908 receives the output of the NAND circuit 905 and outputs a signal n02.

  The NAND circuit 909 receives the signal RS and the signal n02 and outputs a negative logical product. The NAND circuit 910 receives the signal WR and the output of the NAND circuit 909 and outputs a negative logical product. The NAND circuit 911 inputs the signal n01 and the output of the NAND circuit 910, and outputs a negative logical product.

  The RS flip-flop 912 includes NAND circuits 913 and 914. The NAND circuit 913 inputs the signal n03 and the output of the NAND circuit 911, and outputs a negative logical product. The NAND circuit 914 receives the signal REF and the output of the NAND circuit 913, and outputs a signal n03.

  The NAND circuit 919 receives the signal n03 and the signal PSEL1 and outputs them to the inverter 922. The inverter 922 outputs the select signal SEL1. The NAND circuit 920 receives the signal n03 and the signal PSEL4 and outputs them to the inverter 923. The inverter 923 outputs the select signal SEL4.

  Inverter 915 outputs a logic inversion signal of signal PSEL5. The NAND circuit 917 receives the signal n03 and the output of the inverter 915 and outputs a negative logical product. The NOR circuit 916 receives the signal n03 and the signal RD and outputs them to the inverter 918. The NAND circuit 921 receives the output of the NAND circuit 917 and the output of the inverter 918 and outputs the input to the inverter 924. The inverter 924 outputs a select signal SEL5.

  Next, the operation of the circuit will be described. The signal RS is a core reset signal of the first core control signal COC1, and resets the memory core when it becomes high level. During the core operation, the signal RS becomes low level. The signal WR is a state signal that becomes a low level when the first core control signal COC1 is written. The signal CL is a CL signal of the first core control signal COC1 (a pulse for reading data from the memory cell and amplifying the data from the sense amplifier after being amplified by the sense amplifier). The signal REF is a refresh request signal. The signal RD is a state signal that is at a high level when the first core control signal COC1 is read, and holds the state until a write request is generated. Signals PSEL1 to PSEL5 are signals indicating blocks to be refreshed, and are output from the internal counter and the decoder. The signals finally input to the selector are select signals SEL1 to SEL5.

  Here, it is assumed that the signal PSEL1 is at a high level and the signals PSEL2 to PSEL5 are at a low level. When the refresh operation is started by the refresh request signal REF at timing t1, the signal n03 becomes high level, the select signal SEL1 becomes high level, and the control signal of the block BLK1 is switched to the second core control signal COC2. In the second core activation state signal COS2, it is assumed that refresh is performed in the period T1 and writing is performed in the period T2. When a write request is generated from the outside during the refresh period T1, the held write operation is performed on the block BLK1 after the refresh operation.

  The second core activation state signal COS2 is synthesized by the delay line 901 into one state signal such as the signal n01. The signal n01 sets the RS flip-flop 904 and holds the state of the RS flip-flop 912 before the refresh request signal REF becomes high level.

  In the signal RS, it is assumed that reading is performed in the periods T3 and T4. The output signal n02 of the flip-flop 904 holds the state until the signal CL of the first core control signal COC1 of the next read operation is output at the timing t2. The timing of the signal CL is set so that the signal CL is always output during a period when the signal RS is at a low level. After the signal n02 receives the signal CL and becomes high level, at time t3, the signal RS changes to high level, the signal n03 becomes low level, and the select signal SEL1 becomes low level. If no write request is subsequently generated, since the signal RD is at a high level, the select signal SEL5 is set at a high level and the write parity block BLK5 is deactivated. Thus, even after the operation of the second core control signal COC2 is completed, data correction using the calculation result is performed for the next reading once. When a write request is generated after the operation of the second core control signal COC2 is completed, the select signal SEL1 is set to the low level without waiting once by the signal WR. Of course, this requires that the write operation does not have to be as fast as the read operation. In order to speed up writing, writing may be performed without switching the control signal system, as in reading.

  FIG. 11 shows another configuration example of the word decoder 103 and the memory cell 104 constituting one block of FIG. By using the mask information MSK in FIG. 6, the upper byte and / or the lower byte can be selectively accessed. One block includes a main word decoder 1101, a sub word decoder 1102, an upper byte memory cell 1103, a sub word decoder 1104, and a lower byte memory cell 1105.

  Consider a case where there are four blocks BLK1 to BLK4 for storing 16-bit data at the same address. One block stores 4-bit data for the same address. In the same address, the upper byte is the upper 8 bits and the lower byte is the lower 8 bits. The upper byte memory cell 1103 stores two bits in the upper byte. The lower byte memory cell 1105 stores two bits in the lower byte.

  The main word decoder 1101 decodes according to a row address supplied from the outside. The sub word decoder 1102 specifies the row address of the upper byte memory cell 1103 according to the output of the main word decoder 1101. The sub word decoder 1104 specifies the row address of the lower byte memory cell 1105 according to the output of the main word decoder 1101. The upper byte and the lower byte can be read and written by separate control. In one block, the upper byte memory cell 1103 and the lower byte memory cell 1105 can be simultaneously refreshed.

  If a main word decoder is provided for each of the upper byte memory cell 1103 and the lower byte memory cell 1105, the layout area increases. By layering word lines by the main word decoder 1101 and the sub word decoders 1102 and 1104 and sharing the main word line of the main word decoder 1101, the area of the main word decoder 1101 can be reduced.

  As described above, according to the present embodiment, an external access request and an internal refresh operation can be processed at the same time, and even a SRAM interface that does not receive an external refresh request can be accessed at a high speed for one memory core operation. Read operation can be realized in time.

  Also, the activation area of the memory core is divided to limit one refresh area. A plurality of control signals for the memory core are prepared, and control signals of different systems are used for the refresh block and the other blocks. As a result, different control can be performed on the bits of the same address depending on the block in which they exist. Apparently, a read operation can be performed with an access time equivalent to one memory core operation.

  A plurality of blocks in the memory core may be divided in the row address direction, the column address direction, or both address directions.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

The embodiment of the present invention can be applied in various ways as follows, for example.
(Supplementary note 1) a memory core for distributing and storing a plurality of bit data of the same address in a plurality of memory cell blocks;
A refresh circuit can be controlled independently for each of the plurality of memory blocks, and has a control circuit for controlling one memory cell block and another memory cell block to perform refresh operations at different timings Semiconductor memory device.
(Supplementary Note 2) The control circuit causes one memory cell block of the plurality of memory cell blocks to perform a refresh operation at the same timing and writes data to the other memory cell block or The semiconductor memory device according to appendix 1, which can be controlled to perform reading.
(Supplementary Note 3) The memory core can store data having a larger number of bits than the number of bits that can be externally input to the same address,
The semiconductor memory according to claim 1, wherein the control circuit writes a plurality of bit data of an external input to the memory core, performs a logical operation based on the plurality of bit data of an external input, and writes the operation result to the memory core. apparatus.
(Appendix 4) A plurality of memory cell blocks in the memory core are divided in the row address direction and / or the column address direction, and a plurality of bits at the same address are distributed to the plurality of memory cell blocks. Exists,
The semiconductor memory device according to appendix 1, wherein the control circuit can independently control the plurality of memory blocks.
(Supplementary note 5) The semiconductor memory device according to supplementary note 1, wherein the control circuit can activate and control a plurality of memory cell blocks with the same row address or column address.
(Supplementary Note 6) The control circuit has a plurality of control signals for activating and controlling each memory cell block, and includes a selection circuit that selects the control signal system for each memory cell block. The semiconductor memory device described.
(Supplementary Note 7) The control circuit has a plurality of control signals for activating and controlling each memory cell block, and all or the timings of the control signals for each memory cell block are the same, or The semiconductor memory device according to appendix 1, wherein a part thereof may be different.
(Supplementary Note 8) The control circuit activates a plurality of the memory cell blocks by a control signal having the same or different timing, and controls the activation timing and / or activation time of each memory cell block to be different. The semiconductor memory device according to appendix 1, wherein
(Supplementary Note 9) The memory core includes a memory cell block for storing an operation result in addition to a plurality of memory cell blocks for storing a plurality of bit data for the same address,
The control circuit includes a calculation circuit that calculates calculation result data indicating that the number of high-level or low-level bits of a plurality of bits of write data of the same address at the time of data writing is an even number or an odd number. The semiconductor memory device according to appendix 1, wherein the memory cell block for storing the operation result is written.
(Additional remark 10) The said control circuit calculated the calculation result data which shows the number of high level or low level bits of the read data of the several bits of the same address at the time of data reading even number or odd number, and this calculation The semiconductor memory device according to appendix 9, further comprising a comparison circuit that compares the operation result data with the operation result data read from the operation result storage memory cell block.
(Supplementary Note 11) When a plurality of memory cell blocks are activated by reading or writing, the control circuit performs an activation operation when a refresh request is generated for some of the activated memory cell blocks. 2. The semiconductor memory device according to appendix 1, wherein control is performed so that the refresh operation is preferentially performed even if a next read or write request occurs after completion.
(Supplementary Note 12) When a read request signal is input to the memory cell block in the refresh operation, the control circuit does not read the data from the memory cell block, and the two operation result data do not match due to the comparison by the comparison circuit. If there is, the semiconductor memory device according to appendix 10, which has an inversion circuit for inverting the data of the data line of the memory cell block during the refresh operation.
(Supplementary Note 13) When a write request signal for a memory cell block during a refresh operation is input, the control circuit holds the write request signal, and adds the write request signal held after the refresh operation is completed. 13. The semiconductor memory device according to appendix 12, which performs a corresponding write operation.
(Supplementary note 14) The control circuit according to supplementary note 13, wherein when the next write request signal is input during execution of the write operation corresponding to the held write request signal, the control circuit holds the write request signal. Semiconductor memory device.
(Supplementary note 15) The semiconductor memory according to supplementary note 14, wherein the control circuit starts a write operation corresponding to the held write request signal when an activation signal output during execution of the write operation is reset. apparatus.
(Supplementary Note 16) The control circuit has a plurality of control signals for activating and controlling each memory cell block, and has a selection circuit for selecting the control signal system for each memory cell block,
When the next write request signal is not input to the memory cell block during the write operation of the held write request signal, the selection circuit ends the write operation being performed at that time 14. The semiconductor memory device according to appendix 13, wherein the control signal system before the refresh operation is selected.
(Supplementary Note 17) When a write request signal for a memory cell block during a refresh operation is input, the control circuit holds the write request signal, and adds the write request signal held after the refresh operation is completed. 14. The semiconductor according to appendix 12, wherein the inversion circuit inverts data in accordance with a comparison result of the comparison circuit when a corresponding write operation is performed and a read request signal for the memory cell block is input during the write operation. Storage device.
(Supplementary Note 18) When a read request signal is input during a refresh operation, the control circuit inverts data in accordance with the comparison result of the comparison circuit, holds the read request signal, and performs a refresh operation. 14. The semiconductor according to appendix 13, wherein when the read operation is performed after the data is terminated, data is not read from the memory cell block, and the inversion circuit performs the data inversion according to the comparison result of the comparison circuit. Storage device.
(Supplementary Note 19) When a write request signal is input to the memory cell block while the pseudo read operation is being performed, the control circuit holds the write request signal, and the pseudo read operation is performed. 19. The semiconductor memory device according to appendix 18, wherein an operation corresponding to the held write request signal is performed after completion.
(Supplementary Note 20) If a read request signal is input to the memory cell block while the pseudo read operation is being performed, the control circuit holds the read request signal, and the pseudo read operation is performed. 19. The semiconductor memory device according to appendix 18, wherein, in response to the read request signal held after completion, data is not read from the memory cell block, and the inversion circuit performs data inversion according to a comparison result of the comparison circuit.
(Supplementary note 21) The control circuit has a plurality of control signals for activating and controlling each memory cell block, and has a selection circuit for selecting the control signal system for each memory cell block,
During the write operation corresponding to the held write request signal, even if the next write request signal is not input to the memory cell block, the next one read operation is performed by the inverting circuit according to the comparison result. Pseudo-reading by performing data inversion,
14. The semiconductor memory device according to appendix 13, wherein the selection circuit selects a control signal system before the refresh operation when the pseudo read operation is completed.
(Supplementary note 22) The semiconductor memory device according to supplementary note 1, wherein each of the memory cell blocks has a word line hierarchized by an upper byte and a lower byte, and both the upper byte and the lower byte can be simultaneously selected by a main word line. .
(Additional remark 23) The said memory cell block is a semiconductor memory device of Additional remark 22 which performs refresh operation | movement simultaneously with respect to a high-order byte and a low-order byte.
(Supplementary note 24) The semiconductor memory device according to supplementary note 9, wherein when the read operation does not compete with the refresh operation, the control circuit inactivates the memory cell block for storing the operation result and reads from the other memory cell block.
(Supplementary note 25) The semiconductor memory device according to supplementary note 1, wherein each of the plurality of memory cell blocks has a word decoder.
(Supplementary note 26) The semiconductor memory device according to supplementary note 12, wherein the control circuit has two holding circuits for holding an input write request signal or read request signal.
(Supplementary note 27) The semiconductor memory device according to supplementary note 26, wherein the two holding circuits store the request signal alternately using a counter.
(Supplementary note 28) The control circuit controls the two holding circuits alternately by controlling the holding of the signals to the two holding circuits and the time of outputting the held signals with different counters. 28. The semiconductor memory device according to appendix 27, which is used.

It is a memory core schematic diagram. 2A to 2C are diagrams showing a write parity calculation sequence. 3A and 3B are diagrams showing a data correction sequence. It is a block diagram of a control signal generation circuit related to an output from a memory core. 5A and 5B are schematic views showing the overall operation of the semiconductor memory device. 3 is a block diagram of a control signal generation circuit related to an input to a memory core. FIG. It is a circuit diagram of an internal command holding circuit. It is an operation | movement waveform diagram of an internal command holding circuit. It is a circuit diagram of a refresh block selection circuit. It is an operation waveform diagram of the refresh block selection circuit. It is a figure which shows the structure of the block of a memory core.

Explanation of symbols

101 selector 102 column decoder 103 word decoder 104 memory cell SIG1 first control signal SIG2 second control signals SEL1 to SEL5 select signals BLK1 to BLK5 memory cell block

Claims (7)

A memory core for distributing and storing a plurality of bit data of the same address in a plurality of memory cell blocks;
An internal command generation circuit for outputting an internal command signal based on the external command;
A first core control signal generating circuit for outputting a first core control signal for activating the memory core based on the internal command signal;
A control circuit capable of independently controlling a refresh operation for each of the plurality of memory cell blocks, and controlling the refresh operation of one memory cell block and the other memory cell block at different timings; Prepared,
The control circuit includes:
A second core control signal generating circuit for outputting a second core control signal for activating the memory core based on a refresh request signal;
When a read request signal is input to a memory cell block during a refresh operation, the second core control signal is deactivated after the refresh operation is completed, and a read operation is performed based on the read request signal. A semiconductor memory device. A refresh request signal generating circuit for outputting a refresh request signal;
A command-refresh comparison circuit that determines which of the external command and the refresh request signal is early and outputs the refresh request signal to the second core control signal generation circuit when it is determined that the refresh request signal is early The semiconductor memory device according to claim 1, further comprising: The semiconductor memory device according to claim 1, further comprising a selector that selectively outputs the first core control signal and the second core control signal to the memory core. The control circuit includes:
The semiconductor memory device according to claim 3, further comprising: a memory cell block selection circuit that outputs a select signal for selecting a memory cell block to be refreshed to the selector in response to the refresh request signal. The control circuit includes:
When a write request signal is input to the memory cell block during the refresh operation, the write request signal is held, and the next write request signal is input during the write operation corresponding to the held write request signal. The semiconductor memory device according to claim 1, wherein the write request signal is held when the write request signal is received. A memory core for distributing and storing a plurality of bit data of the same address in a plurality of memory cell blocks;
An internal command generation circuit for outputting an internal command signal based on the external command;
A first core control signal generating circuit for outputting a first core control signal for activating the memory core based on the internal command signal;
A second core control signal generating circuit for outputting a second core control signal for activating the memory core based on a refresh request signal;
A memory cell block selection circuit that outputs a select signal for selecting a memory cell block to be refreshed to the selector in response to the refresh request signal;
A selector that selectively outputs the first control signal and the second core control signal to the memory core based on the select signal;
The selector is
In the refresh operation for the first memory cell block among the plurality of memory cell blocks, the second core control signal is supplied to the memory core of the first memory cell block;
In a read operation for a memory cell block other than the first memory cell block, the first core control signal is supplied to a memory core of a memory cell block other than the first memory cell block. apparatus. 7. The first core control signal is deactivated after completion of the refresh operation when a read request is input to the first memory cell block during the refresh operation. The semiconductor memory device described.

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