CN112102859B - Pseudo-static random access memory and data writing method thereof - Google Patents
Pseudo-static random access memory and data writing method thereof Download PDFInfo
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- CN112102859B CN112102859B CN201910521105.4A CN201910521105A CN112102859B CN 112102859 B CN112102859 B CN 112102859B CN 201910521105 A CN201910521105 A CN 201910521105A CN 112102859 B CN112102859 B CN 112102859B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a pseudo-static random access memory and a data writing method thereof. The data writing method comprises the following steps: providing a basic clock signal with a basic period; enabling the chip enable signal to execute the writing operation, and receiving the writing data in the enabled time interval of the chip enable signal; sequentially generating a plurality of internal clock signals at intervals of a basic period according to a write command enable signal; receiving a refresh conflict signal and judging whether the refresh conflict signal is enabled or not; and delaying the internal clock signal when the refresh collision signal is enabled, and writing the write data to the selected sense amplifier according to the delayed internal clock signal.
Description
Technical Field
The present invention relates to a memory control method, and more particularly, to a pseudo-static random access memory and a data writing method thereof.
Background
In recent years, as the level of integration of semiconductor memory devices becomes higher and there is a demand for higher speeds, there is a continuing increase in the demand for pseudo-static random access memory (Pseudo Static Random Access Memory) having the advantages of both static random access memory (Static Random Access Memory) and dynamic random access memory (Dynamic Random Access Memory), particularly for use in mobile devices.
Pseudo-static random access memory is a memory element having a cell structure of dynamic random access memory and peripheral circuitry of static random access memory. Although pseudo-static random access memory has the advantages of large capacity and low cost, the need to periodically perform refresh operations needs to be considered. When a refresh operation collides with a write operation, the conventional pseudo-static random access memory always maintains the reliability of data in a manner of shortening the refresh period, but the above manner causes an increase in current during standby, thereby having a problem of increased power consumption.
Disclosure of Invention
The invention provides a pseudo-static random access memory and a data writing method thereof, which can adjust an internal clock signal to avoid conflict between refresh operation and writing operation.
The data writing method is suitable for the pseudo-static random access memory. The data writing method comprises the following steps: providing a basic clock signal with a basic period; enabling the chip enable signal to execute the writing operation, and receiving the writing data in the enabled time interval of the chip enable signal; sequentially generating a plurality of internal clock signals at intervals of a basic period according to a write command enable signal; receiving a refresh conflict signal and judging whether the refresh conflict signal is enabled or not; and delaying the internal clock signal when the refresh collision signal is enabled, and writing the write data to the selected sense amplifier according to the delayed internal clock signal.
The pseudo-static random access memory of the invention comprises a controller, an internal clock generator and a write buffer. The controller is used for receiving a basic clock signal with a basic period and a chip enabling signal. The internal clock generator is coupled to the controller for sequentially generating a plurality of internal clock signals at intervals of a basic period according to a write command enable signal transmitted by the controller. The write buffer is coupled to the controller and the internal clock generator for writing the write data to the selected sense amplifier according to the internal clock signal. Wherein the internal clock generator delays the internal clock signal when the refresh collision signal is enabled.
Based on the above, the pseudo-static random access memory of the present invention can sequentially generate a plurality of internal clock signals at intervals of a basic cycle. When the refresh operation and the write operation conflict, the pseudo-static random access memory of the invention can delay the time of the write operation by delaying the internal clock signal without shortening the refresh period, so as to smoothly execute the refresh operation and the write operation.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a block diagram of a pseudo-static random access memory according to one embodiment of the invention;
FIG. 2 is a block diagram of a controller according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a refresh collision determination circuit according to an embodiment of the present invention;
FIG. 4 is a block diagram of an internal clock generator according to an embodiment of the invention;
FIG. 5 is a block diagram of a write buffer according to an embodiment of the invention;
FIGS. 6A and 6B are schematic waveforms of a data writing method according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a delay circuit according to an embodiment of the invention;
FIG. 8 is a schematic diagram of an enable signal generation circuit according to an embodiment of the invention;
FIG. 9 is a schematic diagram of a portion of an internal clock generation circuit according to an embodiment of the invention;
FIG. 10 is a flow chart of a method for writing data into a pseudo-static random access memory according to an embodiment of the invention.
Reference numerals illustrate:
100: pseudo-static random access memory
110: controller for controlling a power supply
120: internal clock generator
130: write buffer
210: control logic circuit
220: clock buffer
230: refresh conflict judging circuit
310: latch circuit
320. 720: switching circuit
330: buffer circuit
340. 740-746: delay unit
410: enabling signal generating circuit
420: internal clock generating circuit
430: delay circuit
510: even write buffer
520: odd write buffer
710 to 718: long delay cell
730: conversion circuit
810-880, 910-960: switch
A1 to A3, W: address data
ADj: address data signal
CCLK1 to CCLK4: single pulse clock signal
Ce#, CE0: chip enable signal
CLK: basic clock signal
CLKCE: enable single pulse signal
CSL: control signal
CWE: write command enable signal
Cwred: write command enable delay signal
Din, D0 to D7: writing data
Din_ E, dout _e: even data
Din_ O, dout _o: odd data
Dout: output data
ICKE1 to ICKE4: internal clock enable signal
ICLK1 to ICLK4: internal clock signal
ICLK1D to ICLK4D: internal clock delay signal
ICLKB: anti-reference clock signal
ICLKT: positive reference clock signal
INV1 to INV64: inverter with a high-speed circuit
NAND1 to NAND19: inverse gate
NOR1 to NOR4: OR gate
RASB: sub word line driving signal
REF: refresh signal
REFC: refresh collision signal
S1010 to S1050: step (a)
Detailed Description
Referring now to fig. 1, fig. 1 is a block diagram illustrating a pseudo-static random access memory according to an embodiment of the invention. The pseudo-static random access memory 100 includes a controller 110, an internal clock generator 120, and a write buffer 130. The controller 110 is configured to receive a basic clock signal CLK having a basic period and a chip enable signal ce#.
The controller 110 may be a logic circuit (but not limited thereto) composed of a plurality of logic gates. For example, fig. 2 is a block diagram of a controller according to an embodiment of the invention. In fig. 2, the controller 110 includes a control logic circuit 210, a clock buffer 220, and a refresh collision determination circuit 230. The control logic 210 may generate the chip enable signal CE0 for internal use in the memory according to the chip enable signal ce#. Moreover, the control logic 210 can trigger and generate the enable single pulse signal CLKCE according to the chip enable signal ce#. In addition, when a write operation is to be performed, the control logic 210 may enable the write command enable signal CWE and output the control signal CSL to control the write operation.
The clock buffer 220 is coupled to the control logic 210. The clock buffer 220 generates the positive reference clock signal ICLKT and the negative reference clock signal ICLKB in the enabled time interval of the chip enable signal CE0 according to the chip enable signal CE0 and the basic clock signal CLK.
The refresh collision determination circuit 230 is coupled to the control logic circuit 210. The refresh collision determination circuit 230 is configured to receive a refresh signal REF indicating that a refresh operation is performed and an enable single pulse signal CLKCE. The refresh signal REF is enabled, for example, by a timer (not shown) to periodically perform refresh operations of the pseudo-static random access memory 100. In addition, the refresh conflict judging circuit 230 enables the refresh conflict signal REFC when the enable single pulse signal CLKCE is generated according to the chip enable signal CE0 and the refresh signal REF.
For example, fig. 3 is a schematic diagram of a refresh collision determination circuit according to an embodiment of the present invention. Referring to fig. 3, the refresh collision determination circuit 230 includes a latch circuit 310, a switch circuit 320, and a buffer circuit 330. The buffer circuit 330 includes a delay unit 340. The latch circuit 310 receives the refresh signal REF and the chip enable signal CE0. When the enable single pulse signal CLKCE is generated, the switch circuit 320 is turned on. At this time, if the chip enable signal CE0 corresponding to the write operation and the refresh signal REF corresponding to the refresh operation are simultaneously enabled (for example, the chip enable signal CE0 is pulled down to a low logic level and the refresh signal REF is raised to a high logic level), the refresh conflict signal REFC can be enabled through the buffer circuit 330 by the configuration of the latch circuit 310.
Referring back to fig. 1, in fig. 1, an internal clock generator 120 is coupled to the controller 110. The internal clock generator 120 is configured to sequentially generate 4 internal clock signals ICLK1 to ICLK4 at intervals of a basic period according to the write command enable signal CWE transmitted from the controller 110. Wherein each of the internal clock signals ICLK 1-ICLK 4 has the same period and is an integer multiple (e.g., 8 times) of the fundamental period. The internal clock generator 120 converts the internal clock signals ICLK1 to ICLK4 into 4 single pulse clock signals CCLK1 to CCLK4.
For example, FIG. 4 is a block diagram of an internal clock generator according to an embodiment of the invention. The internal clock generator 120 includes an enable signal generating circuit 410, an internal clock generating circuit 420, and a delay circuit 430. The enable signal generating circuit 410 is configured to sequentially generate 4 internal clock enable signals ICKE 1-ICKE 4 at intervals of a basic period according to the write command enable signal CWE and the inverted reference clock signal ICLKB.
The internal clock generating circuit 420 is coupled to the enable signal generating circuit 410. The internal clock generating circuit 420 is used for generating the internal clock signals ICLK 1-ICLK 4 according to the internal clock enable signals ICKE 1-ICKE 4 and the positive reference clock signal ICLKT.
The delay circuit 430 is coupled to the internal clock generating circuit 420. When the refresh conflict signal REFC is enabled, the delay circuit 430 may delay the internal clock signals ICLK 1-ICLK 4. Specifically, the delay circuit 430 receives the refresh conflict signal REFC and the write command enable signal CWE, and determines whether the internal clock signals ICLK 1-ICLK 4 and the write command enable signal CWE need to be delayed according to the refresh conflict signal REFC.
When the refresh collision signal REFC is enabled, the delay circuit 430 can greatly delay the internal clock signals ICLK 1-ICLK 4 and the write command enable signal CWE, and convert the delayed internal clock signals ICLK 1-ICLK 4 into 4 single pulse clock signals CCLK 1-CCLK 4. Then, the delay circuit 430 may transmit the single pulse clock signals CCLK 1-CCLK 4 to the write buffer 130.
When the refresh collision signal REFC is not enabled, the delay circuit 430 does not greatly delay the internal clock signals ICLK 1-ICLK 4 and the write command enable signal CWE, but directly converts the undelayed internal clock signals ICLK 1-ICLK 4 into the 4 single pulse clock signals CCLK 1-CCLK 4. Then, the delay circuit 430 may transmit the single pulse clock signals CCLK 1-CCLK 4 to the write buffer 130.
Referring back to fig. 1, in fig. 1, the write buffer 130 is coupled to the controller 110 and the internal clock generator 120. The write buffer 130 is used for outputting the write data Din as the output data Dout according to the single pulse clock signals CCLK1 to CCLK4 converted from the internal clock signals ICLK1 to ICLK4 and the control signal CSL, and writing the output data Din into at least one selected sense amplifier (not shown) in the memory array.
For example, FIG. 5 is a block diagram of a write buffer according to an embodiment of the invention. The write buffer 130 includes an even write buffer 510 and an odd write buffer 520. The write data Din may include odd data din_o and even data din_e. The write buffer 130 can write the odd data dout_o and the even data dout_e to the selected sense amplifier in the memory array according to the internal single pulse clock signals CCLK1 to CCLK4 and the control signal CSL through the even write buffer 510 and the odd write buffer 520.
Fig. 6A and 6B are schematic waveforms of a data writing method according to an embodiment of the present invention. The operation and timing of the various signals used in the embodiments of fig. 1-5 are described in detail below with reference to fig. 6A and 6B. Regarding the working details of the pseudo-static random access memory 100, the pseudo-static random access memory 100 receives the basic clock signal CLK and the chip enable signal ce#, through the controller 110. In this embodiment, the chip enable signal ce# is a low active signal, that is, a low logic level when the chip enable signal ce# is in an enabled state. Of course, in other embodiments of the present invention, the chip enable signal ce# may be a high active signal, without limitation.
In fig. 6A, the chip enable signal ce# is enabled at the first time point TA1, and at the same time, the controller 110 receives the chip enable signal ce# enabled at the first time point TA1 to perform the first write operation, and receives an address data signal ADj in a time interval in which the chip enable signal ce# is enabled, so that the address data W, A1-A3 and the write data Din (the write data D0-D7) can be sequentially received.
As shown in fig. 6A, the control logic 210 in the controller 110 can generate the chip enable signal CE0 for internal use in the memory according to the chip enable signal ce#. In addition, the clock buffer 220 in the controller 110 can generate the positive reference clock signal ICLKT and the negative reference clock signal ICLKB in the enabled time interval of the chip enable signal CE0 according to the chip enable signal CE0 and the basic clock signal CLK.
When a write operation or a refresh operation is to be performed, the control logic 210 in the controller 110 may enable the sub-word line driving signal RASB to activate the corresponding sub-word line in the memory array.
As shown in fig. 6A, when the first write operation is to be performed, the control logic circuit 210 may trigger the generation of the enable single pulse signal CLKCE according to the chip enable signal ce#. At this time, the refresh collision determination circuit 230 in the controller 110 may determine whether the write operation collides with the refresh operation according to the refresh signal REF indicating that the refresh operation is performed.
In fig. 6A, after the generation of the single pulse signal CLKCE at the second time point TA2, the refresh collision signal REFC is not enabled by the refresh collision determination circuit 230. That is, the first write operation does not conflict with any refresh operation. Accordingly, as shown in fig. 6A and 6B, the delay circuit 430 in the internal clock generator 120 does not significantly delay the internal clock signals ICLK1 to ICLK4 and the write command enable signal CWE, but directly converts the internal clock signals ICLK1 to ICLK4 into the 4 single pulse clock signals CCLK1 to CCLK4. The write buffer 130 can write the odd data dout_o and the even data dout_e into the selected sense amplifier of the memory array according to the internal single pulse clock signals CCLK1 to CCLK4 through four pulses of the control signal CSL.
For convenience of description, the internal clock delay signals ICLK1D to ICLK4D and the write command enable delay signal CWE represent delayed cases in addition to the internal clock signals ICLK1 to ICLK4 and the write command enable signal CWE representing the original waveforms in fig. 6A and 6B. Therefore, after the single pulse signal CLKCE at the second time point TA2 is generated, the internal clock signals ICLK 1-ICLK 4 and the write command enable signal CWE do not have to be delayed for the first write operation, and the waveforms of the internal clock delay signals ICLK 1-ICLK 4 and the internal clock delay signals ICLK 1D-ICLK 4D are the same, and the waveforms of the write command enable signal CWE and the write command enable delay signal CWE are the same.
On the other hand, in fig. 6A, the chip enable signal ce# is enabled at the third time point TA3, and at the same time, the controller 110 receives the chip enable signal ce# enabled at the third time point TA3 to perform the second write operation.
However, as shown in fig. 6A, after the generation of the single pulse signal CLKCE at the fourth time point TA4, the refresh collision signal REFC is enabled by the refresh collision determination circuit 230. That is, the second write operation may collide with the refresh operation. Accordingly, as shown in fig. 6A and 6B, the delay circuit 430 in the internal clock generator 120 greatly delays the internal clock signals ICLK1 to CLK4 and the write command enable signal CWE (shown as the internal clock delay signals ICLK1D to ICLK4D and the write command enable delay signal cwred in fig. 6A and 6B) to smoothly complete the refresh operation.
Furthermore, the write buffer 130 can sequentially write the odd data dout_o and the even data dout_e to the selected sense amplifier in the memory array according to the internal single pulse clock signals CCLK1 to CCLK4 converted by the delayed internal clock signals ICLK1 to ICLK4 (denoted as the internal clock delay signals ICLK1D to ICLK4D in fig. 6B) through four pulses of the control signal CSL, so as to delay the write operation.
The detailed structure of the delay circuit 430 is illustrated below. Fig. 7 is a schematic diagram of a delay circuit according to an embodiment of the invention. Referring to fig. 7, the delay circuit 430 includes long delay units 710 to 718, a switch circuit 720 and a conversion circuit 730. Delay circuit 430 may receive internal clock signals ICLK 1-ICLK 4 and write command enable signal CWE. In FIG. 7, the internal clock signals ICLK 1-ICLK 4 and the write command enable signal CWE reach the long delay cells 710-718 and the switch circuit 720 via inverters INV 1-INV 5.
In fig. 7, the switching circuit 720 includes a plurality of switches and an inverter INV6. The refresh collision signal REFC may reach the switching circuit 720 through the inverter INV7, thereby performing switching control on the switching circuit 720. As shown in fig. 7, the switches in the switching circuit 720 may be divided into path switches passing through the long delay units 710 to 718 and path switches not passing through the long delay units 710 to 718. The long delay cells 710-718 are used to substantially delay the internal clock signals ICLK 1-CLK 4 and the write command enable signal CWE. When the refresh conflict signal REFC is not enabled, the path switches through the long delay cells 710-718 are turned off, and the path switches not through the long delay cells 710-718 are turned on. At this time, the internal clock signals ICLK 1-ICLK 4 and the write command enable signal CWE do not pass through the long delay units 710-718, and the delay circuit 430 does not substantially delay the internal clock signals ICLK 1-ICLK 4 and the write command enable signal CWE. Conversely, when the refresh conflict signal REFC is enabled, the path switches through the long delay cells 710-718 are turned on, and the path switches not through the long delay cells 710-718 are turned off. At this time, the internal clock signals ICLK 1-ICLK 4 and the write command enable signal CWE pass through the long delay units 710-718, and the delay circuit 430 delays the internal clock signals ICLK 1-ICLK 4 and the write command enable signal CWE substantially.
The conversion circuit 730 includes inverters INV8 to INV24, NAND gates NAND1 to NAND12, NOR gates NOR1 to NOR4, and delay cells 740 to 746. In the circuit configuration shown in fig. 7, the conversion circuit 730 can convert the internal clock signals ICLK1 to ICLK4 into the 4 single pulse clock signals CCLK1 to CCLK4, and generate the signal waveforms shown in fig. 6A and 6B.
The detailed structure of the enable signal generation circuit 410 is illustrated below. FIG. 8 is a schematic diagram of an enable signal generation circuit according to an embodiment of the invention. Referring to fig. 8, the enable signal generating circuit 410 includes inverters INV25 to INV44, NAND gates NAND13 to NAND16, and switches 810 to 880.
The enable signal generating circuit 410 receives the inverted reference clock signal ICLKB, the write command enable signal CWE and the chip enable signal CE0 generated by the control logic circuit 210, and inputs the inverted reference clock signal ICLKB, the write command enable signal CWE and the chip enable signal CE0 to the inverters INV25 to INV27, respectively.
As shown in fig. 8, switches 810 to 880 are controlled by an inverted reference clock signal ICLKB. In the circuit configuration shown in fig. 8, the enable signal generating circuit 410 can generate the 4 internal clock enable signals ICKE1 to ICKE4 sequentially at intervals of a basic period according to the write enable signal CWE and the chip enable signal CE0 by controlling the switches 810 to 880, so as to generate the signal waveforms shown in fig. 6A and 6B.
The clock generating circuit 420 may generate the internal clock signals ICLK 1-ICLK 4 according to the internal clock enable signals ICKE 1-ICKE 4 and the positive reference clock signal ICLKT. The following fig. 9 exemplifies the structure of the internal clock generating circuit 420 taking the circuit structure for generating the internal clock signal ICLK1 as an example. In addition, the circuit structure for generating the other internal clock signals ICLK 2-ICLK 4 may be similarly generalized.
FIG. 9 is a schematic diagram of a portion of an internal clock generation circuit according to an embodiment of the invention. Referring to fig. 9, the internal clock generating circuit 420 includes inverters INV45 to INV64, NAND gates NAND17 to NAND19, and switches 910 to 960.
The internal clock generating circuit 420 receives the positive reference clock signal ICLKT and the internal clock enable signal ICKE1. The switches 910-960 are controlled by a positive reference clock signal ICLKT. In the circuit configuration shown in fig. 9, the enable signal generating circuit 410 can generate the internal clock signal ICLK1 with a period 8 times the basic period according to the internal clock enable signal ICKE1 by controlling the switches 910 to 960, so as to generate the signal waveforms shown in fig. 6A and 6B.
FIG. 10 is a flow chart of a method for writing data into a pseudo-static random access memory according to an embodiment of the invention. Referring to fig. 10, the data writing method of the pseudo-static random access memory in the present embodiment includes the following steps. A base clock signal having a base period is provided (step S1010). The chip enable signal is enabled to perform a write operation, and write data is received during an enabled time interval of the chip enable signal (step S1020). And sequentially generating a plurality of internal clock signals at intervals of a basic period according to the write command enable signal, wherein each internal clock signal has the same period and is an integer multiple of the basic period (step S1030). Then, the refresh collision signal is received, and it is determined whether the refresh collision signal is enabled (step S1040). Finally, when the refresh collision signal is enabled, the internal clock signal is delayed, and the write data is written to the selected sense amplifier according to the delayed internal clock signal (step S1050). The order of steps S1010, S1020, S1030, S1040 and S1050 is for illustration, but the embodiment of the invention is not limited thereto. The details of steps S1010, S1020, S1030, S1040 and S1050 can be referred to the embodiments of fig. 1 to 9, and will not be repeated here.
In summary, the pseudo-static random access memory of the present invention can perform a write operation according to a plurality of internal clock signals. When the refresh operation and the write operation generated regularly collide, the pseudo-static random access memory can delay the time of the write operation by delaying the internal clock signal without shortening the refresh period. Thus, the refresh operation and the write operation can be smoothly performed without increasing power consumption.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.
Claims (13)
1. A data writing method, suitable for a pseudo-static random access memory, comprising:
providing a basic clock signal with a basic period;
enabling a chip enable signal to perform a write operation, and receiving write data in an enabled time interval of the chip enable signal;
sequentially generating a plurality of internal clock signals at intervals of the basic period according to a write command enable signal, wherein falling edges of the plurality of internal clock signals occur simultaneously;
receiving a refresh conflict signal and judging whether the refresh conflict signal is enabled or not; and
when the refresh collision signal is enabled, the internal clock signals are delayed, and a plurality of data contained in the write data are written into at least one selected sense amplifier in sequence according to the delayed internal clock signals.
2. The data writing method according to claim 1, wherein a period of each internal clock signal is the same and is an integer multiple of the basic period.
3. The data writing method according to claim 1, wherein after the step of determining whether the refresh collision signal is enabled, further comprising:
when the refresh collision signal is not enabled, the write data is written into the at least one selected sense amplifier according to the undelayed internal clock signals.
4. The data writing method according to claim 1, further comprising: generating a positive reference clock signal and a negative reference clock signal in an enabled time interval of the chip enable signal according to the chip enable signal and the base clock signal.
5. The data writing method according to claim 4, wherein sequentially generating the plurality of internal clock signals at intervals of the basic period according to the write command enable signal comprises:
sequentially generating a plurality of internal clock enable signals at intervals of the basic period according to the write command enable signal and the anti-reference clock signal; and
generating the plurality of internal clock signals according to the plurality of internal clock enable signals and the positive reference clock signal.
6. The data writing method according to claim 1, wherein before the step of receiving the refresh collision signal, further comprising:
receiving a refresh signal representing refresh action and an enabling single pulse signal triggered and generated by the chip enabling signal; and
enabling the refresh conflict signal when the enable single pulse signal is generated according to the chip enable signal and the refresh signal.
7. The data writing method according to claim 1, wherein the write data includes odd data and even data, and sequentially writing a plurality of data included in the write data to the at least one selected sense amplifier according to the delayed internal clock signals, respectively, comprises:
converting the delayed plurality of internal clock signals into a plurality of single pulse clock signals; and
and writing the odd data and the even data into the at least one selected sense amplifier according to the single pulse clock signals.
8. A pseudo-static random access memory, comprising:
a controller for receiving a basic clock signal having a basic period and a chip enable signal to perform a write operation;
an internal clock generator, coupled to the controller, for sequentially generating a plurality of internal clock signals at intervals of the basic period according to a write command enable signal transmitted by the controller, wherein falling edges of the plurality of internal clock signals occur simultaneously; and
a write buffer coupled to the controller and the internal clock generator for sequentially writing a plurality of data contained in the write data to at least one selected sense amplifier according to the plurality of internal clock signals,
wherein the internal clock generator delays the plurality of internal clock signals when the refresh collision signal is enabled.
9. The pseudo-static random access memory of claim 8, wherein the period of each internal clock signal is the same and an integer multiple of the base period.
10. The pseudo-static random access memory of claim 8, wherein the controller comprises a clock buffer that generates a positive reference clock signal and a negative reference clock signal during an enabled time interval of the chip enable signal in accordance with the chip enable signal and the base clock signal.
11. The pseudo-static random access memory of claim 10, wherein the internal clock generator comprises:
an enable signal generating circuit for sequentially generating a plurality of internal clock enable signals at intervals of the basic period according to the write command enable signal and the anti-reference clock signal;
an internal clock generating circuit coupled to the enable signal generating circuit for generating the internal clock signals according to the internal clock enable signals and the positive reference clock signal; and
and a delay circuit coupled to the internal clock generation circuit for delaying the internal clock signals when the refresh collision signal is enabled.
12. The pseudo-static random access memory of claim 11, wherein the write data comprises odd data and even data, the delay circuit converts the plurality of internal clock signals to a plurality of single pulse clock signals and transfers the plurality of single pulse clock signals to the write buffer,
the write buffer writes the odd data and the even data to the at least one selected sense amplifier according to the plurality of single pulse clock signals.
13. The pseudo-static random access memory of claim 8, wherein the controller further comprises:
the control logic circuit is used for triggering and generating an enabling single pulse signal according to the chip enabling signal; and
the refresh collision judging circuit is coupled to the control logic circuit, and is used for receiving a refresh signal representing a refresh action and the enabling single pulse signal, and enabling the refresh collision signal when the enabling single pulse signal is generated according to the chip enabling signal and the refresh signal.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003187576A (en) * | 2001-12-18 | 2003-07-04 | Hitachi Ltd | Semiconductor memory |
| JP2007066517A (en) * | 1999-12-08 | 2007-03-15 | Renesas Technology Corp | Semiconductor device |
| JP2008210513A (en) * | 2008-04-17 | 2008-09-11 | Fujitsu Ltd | Semiconductor memory |
| JP2009087534A (en) * | 2009-01-26 | 2009-04-23 | Nec Electronics Corp | Semiconductor storage device |
| CN101465158A (en) * | 2007-12-19 | 2009-06-24 | 富士通微电子株式会社 | Semiconductor memory, memory system, and memory access control method |
| CN102024490A (en) * | 2009-09-23 | 2011-04-20 | 北京芯技佳易微电子科技有限公司 | Pseudo-static memory, and reading operation and refreshing operation control method thereof |
Family Cites Families (3)
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|---|---|---|---|---|
| JP4443728B2 (en) * | 2000-06-09 | 2010-03-31 | 株式会社ルネサステクノロジ | Clock generation circuit |
| JP4249412B2 (en) * | 2001-12-27 | 2009-04-02 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor memory device |
| US8717841B2 (en) * | 2012-07-20 | 2014-05-06 | Etron Technology, Inc. | Method of controlling a refresh operation of PSRAM and related device |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| JP2003187576A (en) * | 2001-12-18 | 2003-07-04 | Hitachi Ltd | Semiconductor memory |
| CN101465158A (en) * | 2007-12-19 | 2009-06-24 | 富士通微电子株式会社 | Semiconductor memory, memory system, and memory access control method |
| JP2008210513A (en) * | 2008-04-17 | 2008-09-11 | Fujitsu Ltd | Semiconductor memory |
| JP2009087534A (en) * | 2009-01-26 | 2009-04-23 | Nec Electronics Corp | Semiconductor storage device |
| CN102024490A (en) * | 2009-09-23 | 2011-04-20 | 北京芯技佳易微电子科技有限公司 | Pseudo-static memory, and reading operation and refreshing operation control method thereof |
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