JP4386657B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that always performs an internal refresh operation.
[0002]
[Prior art]
In recent mobile phones and small mobile terminal devices such as PDAs (Personal Digital (Data) Assistants), the amount of data handled has increased due to cooperation with the Internet. Along with this, high-speed and large-capacity memory is required.
[0003]
Currently, mobile phones often use SRAM (Static Random Access Memory), which consumes less power, but there is a problem that the cost increases when the degree of integration of the SRAM is low and the capacity is increased. On the other hand, since DRAM (Dynamic Random Access Memory) can be increased in capacity at low cost, an SRAM interface type DRAM is required.
[0004]
Since a DRAM is a volatile memory, it is necessary to perform a refresh operation for storing and holding at regular intervals. In the SRAM interface type DRAM, there is no need for the SRAM, so some means by the control inside the memory is required.
[0005]
As this means, internal refresh is always performed, and when a read (read) / write (write) command is input from the outside, the internal refresh command is compared with an external command signal, and the internal refresh request is more There is a control method in which read / write is executed after refresh if it is early, and refresh is performed after the command if the read / write command is earlier. By such a method, the refresh operation becomes invisible from the outside of the memory, so that a refresh command is unnecessary as in an SRAM (see, for example, Patent Document 1).
[0006]
FIG. 17 is a block diagram of a part of a conventional DRAM control system.
This control system includes a refresh / command determination circuit 950, a command decode circuit 951, a RAS system operation control circuit 952, and a command control circuit 953.
[0007]
The refresh / command determination circuit 950 determines which of the state transition detection signal atdpz generated from the chip enable signal / CE and the internal refresh request signal srtz is input first. When the state transition detection signal atdpz is later than the refresh request signal srtz, the refresh command refpz and the refresh signal refz are output.
[0008]
The command decode circuit 951 receives the state transition detection signal atdpz and the output enable signal / OE, the write enable signal / WE or the chip enable signal / CE, and receives command signals (read command rdpz, write command wrpz, active command). actpz).
[0009]
The RAS (row address strobe) system operation control circuit 952 receives a refresh signal refz, a refresh command refpz, and an active command actpz, and outputs a row address strobe signal rasz that activates the core. Further, a signal icsx for waiting for the next operation is output until the operation of the previous cycle is completed. The signal icsx is a signal delayed in reverse phase from the row address strobe signal rasz.
[0010]
The command control circuit 953 receives the command signal and the refresh signal refz, and outputs internal command signals (internal read command rdpx, internal write command wrpx).
[0011]
FIG. 18 is a timing chart showing the operation of the conventional semiconductor memory device when the refresh is performed first.
When the refresh request signal srtz (H level single pulse) is ahead of the state transition detection signal atdpz (H level single pulse), the refresh / command determination circuit 950 causes the refresh command refpz (H level single pulse). 1 pulse) is output, and the refresh signal refz rises to the H level. In synchronization with the input refresh command refpz, the RAS operation control circuit 952 raises the row address strobe signal rasz to H level to activate the core and perform a refresh operation. At this time, the signal icsx becomes the L (Low) level, and becomes the H level when the refresh is completed.
[0012]
The command decode circuit 951 detects the state transition detection signal atdpz input subsequent to the refresh request signal srtz, and outputs the active command actpz (H level single pulse). However, the read command rdpz or the write command is output. The command wrpz is waited in the command control circuit 953. When the refresh operation is finished and the signal icsx becomes H level, the refresh signal refz becomes L level. In response to this, the command control circuit 953 outputs the internal read command rdpx or the internal write command wrpx that has been waiting, raises the row address strobe signal rasz to H level, activates the core, and performs the read or write operation. Do.
[0013]
FIG. 19 is a timing chart showing the operation of the conventional semiconductor memory device when the read or write operation is performed first.
When the state transition detection signal atdpz is ahead of the refresh request signal srtz, the refresh / command determination circuit 950 delays the output of the refresh command refpz. At this time, the row address strobe signal rasz becomes H level by the active command actpz, and the read or write operation is executed according to the internal command signal. The refresh operation is executed by a refresh command refpz that is output when the signal icsx becomes H level after the read or write operation is completed.
[0014]
Note that the write cycle of the semiconductor memory device may be longer than the normal operation mode. In a semiconductor memory device having an operation mode in which the write cycle becomes longer, if the RAS write operation enters the cycle in which the next operation is to be performed, the internal operation of the next cycle is performed before the operation of the previous cycle is completed. Started and normal operation is impossible. Therefore, there is a method of detecting the end of the previous write cycle and controlling the operation of the next cycle.
[0015]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-74943 (FIG. 6)
[0016]
[Problems to be solved by the invention]
However, if the refresh command is waiting in an operation mode with a long write cycle, the read operation of the next cycle and the start of the refresh operation are both detected because the end of the write cycle is detected, resulting in a collision. There was a problem that normal operation could not be performed.
[0017]
If the chip enable signal / CE after the write cycle is sufficiently high (standby period or write recovery time), normal operation can be performed after the write operation of the previous cycle is completed.
[0018]
However, in this case, there is a problem that taking a sufficient write recovery time causes a time overhead, resulting in a decrease in system performance.
The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor memory device capable of shortening the write recovery time even in an operation mode having a long write cycle.
[0019]
[Means for Solving the Problems]
In the present invention, in order to solve the above problem, in a semiconductor memory device that performs an internal refresh operation, as shown in FIG. 1, a command control circuit 400 that generates an internal command signal for performing a command operation, Write cycle is longer than normal operation mode Write operation Is In this case, the command standby signal generation circuit 500 for generating the command standby signal bicsz for waiting for the internal command signal for performing the next command operation, the end of the write operation based on the command standby signal bicsz, and the next command operation When the start relationship is determined and the write operation does not end until the start of the next command operation, and the next command operation is a read operation, the standby refresh command refpz is output after the end of the read operation (see FIG. 100a) (referred to as a refresh / command determination circuit in FIG. 1).
[0020]
According to the above configuration, the command control circuit 400 generates an internal command signal, and the command standby signal generation circuit 500 Write cycle is longer than normal operation mode Write operation Is In this case, a command standby signal bicsz that delays generation of an internal command signal for performing the next command operation is generated. The determination circuit 100a determines the relationship between the end of the write operation and the start of the next command operation based on the command standby signal bicsz, and if the write operation does not end until the start of the next command operation, the next command If the operation is a read operation, the standby refresh command refpz is output after the end of the read operation. This Write cycle is longer than normal operation mode After the write operation, a collision between the refresh in standby and the read operation as the next command operation is prevented.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram of a part of a control system of the semiconductor memory device according to the first embodiment of the present invention.
[0022]
Hereinafter, a DRAM control system will be described as an example.
This control system includes a refresh / command determination circuit 100a, a command decode circuit 200, a RAS system operation control circuit 300, a command control circuit 400, and a command standby signal generation circuit 500.
[0023]
The refresh / command determination circuit 100a has a function of determining which of the state transition detection signal atdpz and the internal refresh request signal srtz is input first. When the state transition detection signal atdpz is later than the refresh request signal srtz, a refresh command refpz and a refresh signal refz are output. The state transition detection signal atdpz is output from a state transition detection circuit (not shown) by detecting the falling edge of the chip enable signal / CE.
[0024]
Further, the refresh / command determination circuit 100a according to the first embodiment of the present invention has a signal icsx from the RAS operation control circuit 300, an internal read command rdpx from the command control circuit 400, and a command standby signal from the command standby signal generation circuit 500. bicsz is input respectively.
[0025]
Based on these signals, the refresh / command determination circuit 100a determines the relationship between the end of the write operation and the start of the read operation of the next cycle. Here, when the write operation does not end before the start of the next read operation, that is, when the state transition detection signal atdpz is detected in the state where the command standby signal bicsz is input, if the refresh request is waiting Until the internal read command rdpx is issued by the command control circuit 400, the output of the refresh command refpz is prohibited. Then, after the read operation is completed, the refresh command refpz is output. When the write operation finishes until the start of the next read operation, the refresh command refpz and the refresh signal refz are output in response to the waiting refresh request regardless of the next command operation.
[0026]
The command decode circuit 200 receives the state transition detection signal atdpz, the output enable signal / OE, the write enable signal / WE, or the chip enable signal / CE, and receives command signals (read command rdpz, write command wrpz, active command). actpz) is generated and output to the command control circuit 400.
[0027]
The RAS operation control circuit 300 receives the refresh command refpz and the internal active command actpx generated by the command control circuit 400, and outputs a row address strobe signal rasz that activates the core (not shown). In addition, the signal icsx in which the row address strobe signal rasz is delayed and in reverse phase is output.
[0028]
The command control circuit 400 receives the command signal and the refresh signal refz, and receives an internal command signal (internal read command rdpx, internal write command wrpx, internal active command actpx) and a signal writez indicating whether or not a write operation is being performed. Is output.
[0029]
The command standby signal generation circuit 500 is a signal indicating that the write cycle becomes long, and receives a mode signal modez and a signal writez that are set and generated by a mode register or the like. Further, based on these signals, a command standby signal bicsz for waiting for the next command is output, and an internal command signal output from the command control circuit 400 is waited.
[0030]
Next, a specific operation of the control system in FIG. 1 in the case where the read operation is performed after the write operation will be described with reference to timing diagrams for each signal.
FIG. 2 is a timing chart for explaining the operation in the control system of the semiconductor memory device according to the first embodiment.
[0031]
When the chip enable signal / CE falls to L level, this is detected and a state transition detection signal atdpz (H level single pulse) is generated. The state transition detection signal atdpz is input to the refresh / command determination circuit 100a. In the refresh / command determination circuit 100a, the refresh request signal srtz (H level single pulse) is compared with the state transition detection signal atdpz, and the operation with the earlier timing is selected. In FIG. 2, since the state transition detection signal atdpz rises faster, the command operation is prioritized.
[0032]
In cycle 1, a write operation is executed. At this time, the state transition detection signal atdpz is detected, and the command control circuit 400 uses the active command actpz (H level single pulse) generated by the command decode circuit 200 to cause the internal active command actpx (L level single pulse). ) Is generated. In synchronization with this, in the RAS operation control circuit 300, the row address strobe signal rasz rises to H level and the core is activated. Further, the signal icsx is at the L level. At this time, data is written from an input buffer (not shown) to an address designated from outside the core.
[0033]
Further, in the case of a write operation, the command control circuit 400 outputs an internal write command wrpx (L level single pulse), and in synchronization with this, the signal writez becomes H level. In the case of a write operation with a long operation cycle, the command standby signal generation circuit 500 receives the input of the mode signal modez (not shown in FIG. 2) and sets the command standby signal bicsz to the H level as shown in FIG.
[0034]
When the chip enable signal / CE returns to the H level and again becomes the L level, the state transition detection signal atdpz is output, and the operation of cycle 2 is started. In cycle 2, a read operation is performed.
[0035]
As shown in FIG. 2, when the write enters cycle 2, the command standby signal bicsz is at the H level when the write operation is continuing, and the command control circuit 400 waits for the output of the internal read command rdpx. When the row address strobe signal rasz becomes L level and the signal icsx becomes H level and the write operation in cycle 1 is completed, the command waiting signal generation circuit 500 detects the rising edge of the signal icsx and sets the command waiting signal bicsz to L. To level. In synchronization with this, the command control circuit 400 outputs the internal active command actpx and outputs the standby internal read command rdpx (L level single pulse) to perform the read operation. At this time, the signal writez becomes L level in synchronization with the output of the internal read command rdpx.
[0036]
In the semiconductor memory device according to the first embodiment of the present invention, the refresh / command determination circuit 100a waits for the refresh command refpz that has been waiting even when the write that has entered cycle 2 is completed and the signal icsx becomes H level. Is not output. The refresh command refpz is output at the rising edge of the signal icsx at the end of the read operation. As a result, the refresh signal refz is set to H level, and the row address strobe signal rasz is raised to H level to perform a refresh operation.
[0037]
As described above, in the semiconductor memory device according to the first embodiment of the present invention, the refresh / command determination circuit 100a determines the relationship between the write operation and the start of the next read operation. When the operation does not end until the start of the operation, the standby refresh command is output after the end of the read operation. Thereby, it is possible to prevent the read operation and the refresh operation from colliding with each other.
[0038]
Next, details of the refresh / command determination circuit 100a will be described.
FIG. 3 is a circuit configuration diagram of an example of the refresh / command determination circuit.
The refresh / command determination circuit 100a includes a NAND circuit 101 that takes NAND logic of a command standby signal bicsz and a state transition detection signal atdpz, an FF circuit 102 having a terminal for inputting an output signal of the NAND circuit 101, and a flip-flop circuit ( (Hereinafter referred to as FF circuit) 102 has a NAND circuit 103 for inputting the output signal of 102 to one input terminal. A signal icsx is input to the other input terminal of the NAND circuit 103, and an output signal of the NAND circuit 103 is input to one input terminal of the NAND circuit 105 via the inverter 104. Further, the output signal of the NOR circuit 107 to which the state transition detection signal atdpz and the state transition detection signal atdpz delayed by the delay circuit 106 are input is connected to the other input terminal of the NAND circuit 105 via the inverters 108 and 109. Is input.
[0039]
The output signal of the NAND circuit 105 is input to the FF circuit 110 that functions as a comparison unit. The FF circuit 110 includes NAND circuits 110a and 110b, and the output signal of the NAND circuit 105 is input to one input terminal of the NAND circuit 110a. The output signal of the FF circuit 112 to which the refresh request signal srtz is input to one input terminal via the inverter 111 is input to one input terminal of the NAND circuit 110b. The FF circuit 112 includes NAND circuits 112a and 112b, and the output of the inverter 111 is input to one input terminal of the NAND circuit 112a. The output of the FF circuit 112 is output from the NAND circuit 112a.
[0040]
The output of the FF circuit 110 functioning as a comparison unit is input to the FF circuit 114 via the inverter 113. The FF circuit 114 includes NOR circuits 114a and 114b. Here, the output of the inverter 113 is input to one input terminal of the NOR circuit 114a, the output is output from the NOR circuit 114b, and this output signal becomes the refresh command refpz.
[0041]
The output signal of the FF circuit 114 is further input to the FF circuit 115. The FF circuit 115 includes NOR circuits 115a and 115b. Here, the output of the FF circuit 114 is input to one input terminal of the NOR circuit 115a, and the output is also output from the NOR circuit 115a. The output signal of the FF circuit 115 is inverted by the inverter 116 and output as the refresh signal refz to the outside of the refresh / command determination circuit 100a.
[0042]
Note that the output signal of the FF circuit 115 is input to one input terminal of the NOR circuit 114b constituting the FF circuit 114 described above via the delay circuit 117. Further, the output signal of the FF circuit 115 is input to one input terminal of the NAND circuit 112b constituting the FF circuit 112 described above via the delay circuits 117 and 118 and the inverter 119.
[0043]
The operation of the refresh / command determination circuit 100a will be described.
Here, the node A will be described below as an inverter 109, the node B as an NAND circuit 105, the node C as an FF circuit 102, and the node D as an output signal of the inverter 104.
[0044]
When the refresh request signal srtz is input and a refresh request is made, the output of the FF circuit 112 becomes H level and is input to the FF circuit 110.
The FF circuit 110 functions as a comparison unit that compares which of the state transition detection signal atdpz and the refresh request signal srtz is input first. When the state transition detection signal atdpz is input earlier than the refresh request signal srtz, the node A goes to the L level and the node B goes to the H level, so the refresh request signal srtz is input after that, and the FF circuit Even if the output of 112 becomes H level, the node B is in the hold state while the node B is at H level, the FF circuit 110 selects the command operation, and the refresh command refpz is not output.
[0045]
At this time, the refresh request signal srtz is held by the FF circuit 112, and when the node B becomes L level, the FF circuit 110 selects the refresh operation and the output of the FF circuit 110 becomes L level.
[0046]
The output of the FF circuit 110 is inverted by the inverter 113 and then input to the FF circuit 114. At this time, the output of the FF circuit 114 becomes H level, and the refresh command refpz rises to H level and is output. Further, the FF circuit 115 holds the H level only during the refresh execution time when the signal icsx becomes the L level, and the refresh signal refz is output.
[0047]
On the other hand, when the refresh request signal srtz is input prior to the state transition detection signal atdpz, if the node D is at the H level, the node B is at the L level, so that the FF circuit 110 selects the refresh operation, As described above, the refresh command refpz and the refresh signal refz are output.
[0048]
Here, the output level of the node B is determined as follows.
In the FF circuit 102, if both of the two input terminals are at the H level, the holding state is established. That is, it is a case where at least one of the command standby signal bicsz and the state transition detection signal atdpz is at L level and the internal read command rdpx is at H level.
[0049]
In the operation mode with a long write cycle, when the command standby signal bicsz is in the H level state, when the state transition detection signal atdpz becomes the H level by the start of the next read cycle, the FF circuit 102 is set. L level. At this time, the node D becomes L level and the node B becomes H level. In this state, even if the write operation is finished and the signal icsx rises and becomes H level, the node D maintains the L level and the node B remains at the H level. That is, the refresh command refpz is not output.
[0050]
When the command control circuit 400 generates a single pulse in which the internal read command rdpx becomes L level, the node C becomes H level. At this time, when the write operation is completed and the signal icsx rises and becomes H level, the node D becomes H level, and the state transition detection signal atdpz is L level, so the node B becomes L level.
[0051]
Next, the operation of the refresh / command determination circuit 100a in FIG. 3 will be specifically described with reference to a timing chart showing the timing of main signals.
FIG. 4 is a timing chart for explaining the operation of the refresh / command determination circuit.
[0052]
The timing diagram of FIG. 4 is coincident with the timing diagram of the control system of FIG.
When the chip enable signal / CE falls to L level, this is detected and a state transition detection signal atdpz which is a single pulse at H level is generated. The state transition detection signal atdpz is input to the refresh / command determination circuit 100a. In the refresh / command determination circuit 100a, the refresh request signal srtz and the state transition detection signal atdpz are compared by the FF circuit 110, and the operation of the input signal with the earlier timing is selected. In FIG. 4, the state transition detection signal atdpz is early, the node A becomes L level, and in synchronization with this, the node B that is input to the FF circuit 110 becomes H level, and the command operation is selected. The node A maintains the L level while the signal icsx is at the H level by the delay circuit 106, and then returns to the H level.
[0053]
In cycle 1, a write is executed, the row address strobe signal rasz becomes H level, and the core is activated. Further, the signal icsx is at the L level. When the falling edge of the signal icsx is detected, the node D becomes L level.
[0054]
When the chip enable signal / CE returns to the H level and again becomes the L level, the state transition detection signal atdpz is output, and the operation of cycle 2 is started. In cycle 2, a read operation is performed.
[0055]
When the operation of cycle 2 starts, the node A becomes L level in synchronization with the output of the state transition detection signal atdpz. At this time, since the write operation in cycle 1 is continuing, the command standby signal bicsz is at the H level, so that the node C that is the output signal of the FF circuit 102 is at the L level. After that, since the FF circuit 102 is in the holding state, the node C holds the L level. Therefore, the node D maintains the L level even when the write operation of the cycle 1 is completed and the rising edge of the signal icsx is detected, and the node B remains at the H level. As a result, the refresh command refpz is not output and the refresh operation is not started.
[0056]
When the internal read command rdpx output after the write operation is completed, the node C becomes H level. Here, when the read of cycle 2 is completed and the signal icsx becomes H level, the rising edge is detected, and the node D becomes H level and the node B becomes L level. Here, the refresh request held in the FF circuit 112 is selected by the FF circuit 110, the refresh command refpz is output, the refresh signal refz is set to H level, and the refresh operation is performed.
[0057]
When the refresh operation starts, the signal icsx becomes L level, and in synchronization with this, the node D also becomes L level. When the chip enable signal / CE returns to the H level and again becomes the L level, the operation of the next cycle starts. At this time, the state transition detection signal atdpz is generated, and accordingly, the node A becomes L level. At this time, the node B becomes H level.
[0058]
As described above, when the read operation of the next cycle is started before the write operation is completed, the NAND logic of the command standby signal bicsz and the state transition detection signal atdpz is taken and input to the FF circuit 102. By setting the hold state, the node C is held at the L level until the internal read command rdpx is input and the hold state is released, so that the refresh operation can be prevented from being executed. Thereby, even after a long write cycle, the collision between the read operation and the refresh operation in the next cycle can be prevented.
[0059]
Next, the command control circuit 400 and the command standby signal generation circuit 500 used in the control system of the semiconductor memory device of the present invention will be described.
FIG. 5 is a circuit configuration diagram of the command control circuit.
[0060]
The command control circuit 400 includes an FF circuit 402 that inputs an active command actpz to one input terminal via an inverter 401, an FF circuit 404 that inputs a read command rdpz to one input terminal via an inverter 403, and an inverter 405. And an FF circuit 406 for inputting the write command wrpz to one input terminal. Each of these FF circuits 402, 404, and 406 includes two NAND circuits.
[0061]
Output signals of the FF circuits 402, 404, and 406 are input to one input terminals of the NAND circuits 407, 408, and 409, respectively. Further, the output signal of the NOR circuit 410 taking the NOR logic of the refresh signal refz and the command standby signal bicsz is input to the other input terminals of the NAND circuits 407, 408, and 409. Here, the output signal of the NAND circuit 407 is output to the outside of the command control circuit 400 as the internal active command actpx, the output signal of the NAND circuit 408 is output as the internal read command rdpx, and the output signal of the NAND circuit 409 is output as the internal write command wrpx. Is done.
[0062]
The output signals of the NAND circuits 407, 408, and 409 are input to the NAND circuit 411 and input to the other input terminals of the FF circuits 402, 404, and 406 via the delay circuit 412 and the inverter 413.
[0063]
The outputs of the NAND circuits 409 and 410 are input to the FF circuit 414 including two NAND circuits, and the output signal of the FF circuit 414 is output to the outside of the command control circuit 400 as a signal writez.
[0064]
The operation of the command control circuit 400 will be briefly described.
When an active command actpz, a read command rdpz, and a write command wrpz (H level single pulse) are input, if the refresh signal refz and the command standby signal bicsz are at L level, internal command signals (L level 1 pulse). However, when any of the internal command signals is output, the FF circuits 402, 404, and 406 are in the holding state, and no other internal command signal is output. The signal writez is output at the same time when the internal write command wrpx is output.
[0065]
FIG. 6 is a circuit configuration diagram of the command standby signal generation circuit.
The command standby signal generation circuit 500 includes two inverters 501 and 502 and a NOR circuit 503. The signal icsx and the mode signal modez are passed through the inverter 501, and the signal writez is passed through the inverter 502, respectively. It is the structure inputted into.
[0066]
The output signal of the NOR circuit 503 is output to the outside of the command standby signal generation circuit 500 as a command standby signal bicksz. This command standby signal bicsz is generated when the mode signal modez output in the mode in which the write cycle is long is H level, the signal writez indicating that the write operation is being executed is H level, and the signal icsx is L level. , H level.
[0067]
Next, the external configuration of the control system in FIG. 1 will be described.
FIG. 7 is a block diagram showing an external configuration of the control system of FIG.
In addition, about the part of the control system shown in FIG.
[0068]
The control system of the semiconductor memory device according to the embodiment of the present invention includes an address latch circuit 710, an address decode circuit 720, a bit line control circuit 730, a block selection circuit 740, and a word line control circuit in addition to the control system described in FIG. 750, a word line selection circuit 760, a sense amplifier control circuit 770, and a sense amplifier selection circuit 780.
[0069]
The address latch circuit 710 temporarily latches the input external address ADD.
The address decoding circuit 720 decodes the external address ADD and supplies address information to the block selection circuit 740 and the word line selection circuit 760.
[0070]
The bit line control circuit 730 receives the row address strobe signal rasz and the internal read command rdpx or the internal write command wrpx among the internal command signals, and selects the timing signal blspz for releasing the short-circuiting of the bit line pair described later. The data is output to the circuit 740 and the word line control circuit 750.
[0071]
The block selection circuit 740 receives the timing signal blspz and outputs a bit line short control signal brsx for canceling the short circuit of the bit line pair of the selected block based on the address information from the address decoding circuit 720. Further, the block selection signal rblkz indicating the selected block is output to the word line selection circuit 760 and the sense amplifier selection circuit 780.
[0072]
The word line control circuit 750 receives the timing signal blspz, generates a word line drive timing signal wlspz, and outputs it to the word line selection circuit 760 and the sense amplifier control circuit 770. In addition, a word line reset timing signal wlrpz for resetting the word line WL is output in synchronization with the fall of the row address strobe signal rasz.
[0073]
The word line selection circuit 760 raises the word line WL to the H level at the timing of the word line drive timing signal wlspz based on the input block selection signal rblkz and the word line selection address. Further, the word line WL is lowered to the L level at the timing of the word line reset timing signal wlrpz.
[0074]
The sense amplifier control circuit 770 outputs a sense amplifier activation timing signal mlez for activating a later-described sense amplifier to the sense amplifier selection circuit 780 after a predetermined time from the input of the word line drive timing signal wlspz. Further, the sense amplifier activation timing signal mlez falls to the L level after a predetermined time from the input of the word line reset timing signal wlrpz.
[0075]
The sense amplifier selection circuit 780 receives the block selection signal rblkz and outputs the sense amplifier drive signals lez and lex at the timing of the sense amplifier activation timing signal mlez.
[0076]
FIG. 8 is a circuit diagram showing a configuration example of a part of the core circuit.
The core circuit has a large number of memories arranged in a matrix and is divided into a plurality of blocks.
[0077]
8 includes a memory cell 801, bit line precharge transistors 802 and 803, a bit line short transistor 804, a sense amplifier 806, transistors 805 and 807 for controlling the sense amplifier, and a transfer gate. Transistors 808 and 809 are included. The memory cell 801 includes a cell transistor 801a and a cell capacitor 801b, and is connected to one of a pair of bit lines BL and / BL (BL in FIG. 8).
[0078]
The pair of bit lines BL and / BL are connected to internal data buses DB and / DB via transistors 808 and 809, respectively. vpr is a bit line precharge voltage.
[0079]
Hereinafter, the operations of FIGS. 7 and 8 will be described with reference to timing charts, taking the case of performing a read operation as an example.
FIG. 9 is a timing chart showing the operation of the semiconductor memory device according to the embodiment of the present invention.
[0080]
When the command decode circuit 200 generates an active command actpz (H level single pulse), the command control circuit 400 generates an internal active command actpx (not shown in FIG. 9), and the RAS operation control circuit 300 The row address strobe signal rasz is raised to H level. Here, the bit line control circuit 730 detects the rising edge of the row address strobe signal rasz and outputs a timing signal blspz (H level single pulse).
[0081]
When the word line control circuit 750 detects the timing signal blspz, the word line control circuit 750 generates a word line drive timing signal wlspz (H level single pulse), and outputs it to the sense amplifier control circuit 770 and the word line selection circuit 760.
[0082]
On the other hand, when the block selection circuit 740 detects the timing signal blspz, on the basis of the address information from the address decoding circuit 720, the block selection circuit 740 sets the bit line short control signal brsx of the selected block to L level, and the transistor shown in FIG. Turn off 802, 803, and 804. As a result, the short circuit state of the bit lines BL and / BL is released.
[0083]
The word line selection circuit 760 raises the word line WL to the H level in synchronization with the rise of the word line drive timing signal wlspz based on the block selection signal rblkz and the address information output from the address decoding circuit 720. . When the word line WL rises, the data in the memory cell 801 is read to the bit lines BL and / BL.
[0084]
On the other hand, the sense amplifier control circuit 770 delays the input word line drive timing signal wlspz for a predetermined time and raises the sense amplifier activation timing signal mlez to the H level. Upon detecting this signal, the sense amplifier selection circuit 780 outputs sense amplifier drive signals lex and lez to the transistors 805 and 807, and turns them on. As a result, the sense amplifier 806 is activated and the potential difference between the bit lines BL and / BL is amplified. Thereafter, a column-related column selection signal CL (not shown in FIG. 7) is input from the address decode circuit 720, the transistors 808 and 809 are turned on, and the data amplified by the sense amplifier 806 is stored in the internal data bus DB, / DB is output.
[0085]
When the data reading is completed and the restoration is completed, the command decode circuit 200 sends a precharge command prepz (not shown in FIG. 7) to the RAS operation control circuit 300 in order to perform the precharge operation. In this case, the row address strobe signal rasz is lowered. Upon detecting this, the word line control circuit 750 generates a word line reset timing signal wlrpz and outputs it to the word line selection circuit 760. Detecting this, the word line selection circuit 760 causes the selected word line WL to fall to the L level.
[0086]
In addition, in response to the word line reset timing signal wlrpz, the sense amplifier control circuit 770 causes the sense amplifier activation timing signal mlez to fall to the L level after a predetermined time has elapsed. Detecting this, the sense amplifier selection circuit 780 outputs sense amplifier drive signals lex and lez, turns off the transistors 805 and 807, and deactivates the sense amplifier 806.
[0087]
Further, in synchronization with the falling edge of the sense amplifier activation timing signal mlez, the bit line control circuit 730 generates a timing signal blrpz (not shown in FIG. 7) for shorting the bit line, and blocks The data is output to the selection circuit 740. The block selection circuit 740 detects this and sets the bit line short control signal brsx to the H level to short-circuit the bit lines BL and / BL.
[0088]
In the semiconductor memory device of the first embodiment described above, when a read operation is performed after an operation mode with a long write cycle, the read operation is performed in preference to the refresh operation to prevent collision. Was composed.
[0089]
As an operation mode of the semiconductor memory device, a write operation may be performed after a write operation with a long cycle. In that case, it is necessary to perform a refresh operation before the next write operation.
[0090]
Here, the timing chart showing the timing of main signals of the refresh / command determination circuit 100a is shown for the operation of the semiconductor memory device of the first embodiment when the write operation is further performed after the long-cycle write operation. It explains using.
[0091]
FIG. 10 is a timing chart for explaining the operation of the semiconductor memory device when writing is performed after a long-cycle write operation.
When the read operation is performed after the write operation, as shown in FIG. 4 described above, when the write operation is completed and the internal read command rdpx is output, the node C becomes H level and the refresh after the write operation is prohibited. The refresh operation is performed after the read operation is completed. Therefore, when the write operation is further performed after the write operation, the node B remains at the H level even when the write operation in the cycle 1 ends and the signal icsx rises to the H level as shown in FIG. The refresh operation cannot be started indefinitely.
[0092]
The semiconductor memory device according to the second embodiment of the present invention is an improvement on this point.
The semiconductor memory device according to the second embodiment of the present invention will be described below.
[0093]
FIG. 11 is a block diagram of a part of the control system of the semiconductor memory device according to the second embodiment of the present invention.
Note that the same circuits as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0094]
This control system includes a refresh / command determination circuit 100b, a command decode circuit 200, a RAS system operation control circuit 300, a command control circuit 400, and a command standby signal generation circuit 500. Further, unlike the first embodiment, The internal write command wrpx is inputted and a write command delay circuit 600 for delaying the internal write command is provided.
[0095]
The refresh / command determination circuit 100b in the second embodiment detects a falling edge of the chip enable signal / CE and issues a state transition, similar to the refresh / command determination circuit 100a in the first embodiment. It has a function of determining which one of the detection signal atdpz and the internal refresh request signal srtz is input first. When the state transition detection signal atdpz is slower than the refresh request signal srtz, the refresh command refpz is output and the refresh signal refz is set to H level. Further, the signal icsx is input from the RAS operation control circuit 300, the internal read command rdpx is input from the command control circuit 400, and the command standby signal bicsz is input from the command standby signal generation circuit 500.
[0096]
Further, unlike the first embodiment, the refresh / command determination circuit 100b receives the internal write command wrpx.
Based on these signals, the relationship between the end of the write operation and the start of the command operation in the next cycle is determined. Here, if the write operation does not end before the start of the command operation of the next cycle, if the command operation of the next cycle is a write operation, the internal write command wrpx is input, the refresh command refpz is output, and the refresh operation is performed. The refresh operation is performed by setting the signal refz to the H level.
[0097]
When the command operation of the next cycle is a read operation, the same operation as that of the first embodiment shown in FIG. 1 is performed.
The write command delay circuit 600 delays the internal write command wrpx, and outputs the write command delay signal wrpdx in synchronization with the fall when the refresh signal refz is at L level. The write command delay signal wrpdx is input to the RAS operation control circuit 300 and the bit line control circuit 730 shown in FIG.
[0098]
FIG. 12 is a circuit diagram of the write command delay circuit.
The write command delay circuit 600 includes an inverter 601, a NAND circuit 602, an FF circuit 603, and two delay circuits 604 and 605. The FF circuit 603 includes NAND circuits 603a and 603b. The write command delay circuit 600 receives the refresh signal refz and the internal write command wrpx, and the refresh signal refz is input to one input terminal of the NAND circuit 602 via the inverter 601. The internal write command wrpx is delayed by the delay circuit 604 and is input to one input terminal of the NAND circuit 603 a constituting the FF circuit 603. The output signal of the FF circuit 603 output from the NAND circuit 603a is input to the other input terminal of the NAND circuit 602. The output signal of the NAND circuit 602 is input to one input terminal of the NAND circuit 603b included in the FF circuit 603, and is output to the outside of the write command delay circuit 600 as the write command delay signal wrpdx.
[0099]
Next, the operation of the control system in FIG. 11 will be described with reference to timing diagrams for each signal.
In the following, a case where a write operation is further performed after the write operation will be described.
[0100]
FIG. 13 is a timing chart for explaining the operation in the control system of the semiconductor memory device according to the second embodiment.
Since the operation of cycle 1 is the same as that of the first embodiment, the description thereof will be omitted, and description will be made from cycle 2.
[0101]
When the chip enable signal / CE becomes L level, the operation of cycle 2 starts. At this time, since the write operation in cycle 1 is continuing, the command standby signal bicsz is at the H level, and the output of the next internal write command wrpx is waited. When the write operation in cycle 1 is completed, the command standby signal bicsz becomes L level, and the internal write command wrpx is output.
[0102]
When the internal write command wrpx in cycle 2 is output, the refresh / command determination circuit 100b of the second embodiment detects this fall and generates a refresh request signal srtz during the write operation in cycle 1. If so, the refresh command refpz is output, the refresh signal refz is set to H level, and the refresh operation is performed.
[0103]
When the refresh operation is finished and the signal icsx becomes H level and the refresh signal becomes L level, the write command delay circuit 600 outputs the write command delay signal wrpdx in synchronization with the fall. This signal is input to the RAS system operation control circuit 300, the row address strobe signal rasz is set to H level, and the write operation in cycle 2 is started.
[0104]
Next, details of the refresh / command determination circuit 100b in the semiconductor memory device of the second embodiment will be described.
FIG. 14 is a circuit configuration diagram of a refresh / command determination circuit in the semiconductor memory device according to the second embodiment.
[0105]
The same parts as those of the refresh / command determination circuit 100a of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
Unlike the refresh / command determination circuit 100a of the first embodiment shown in FIG. 3, the refresh / command determination circuit 100b of the second embodiment receives an internal write command wrpx.
[0106]
The internal write command wrpx is input to the NAND circuit 120 together with the internal read command rdpx, and the output thereof is input to one input terminal of the NAND circuit 102b constituting the FF circuit 102 via the inverter 121. Furthermore, the inverters 104 and 109 of the refresh / command determination circuit 100a of the first embodiment are replaced with NAND circuits 122 and 123, and an internal write command wrpx is input to one input terminal of these NAND circuits 122 and 123. The configuration is entered.
[0107]
Here, the node A indicates the output signal of the inverter 108, and the node B indicates the output signal of the NAND circuit 105. Node C indicates an output signal of the FF circuit 102, and node D indicates an output signal of the NAND circuit 122.
[0108]
Next, the characteristic part of the operation of the refresh / command determination circuit 100b of FIG. 13 will be specifically described with reference to a timing chart showing the timing of main signals.
FIG. 15 is a timing chart for explaining the operation of the refresh / command determination circuit in the semiconductor memory device of the second embodiment.
[0109]
Note that the timing diagram of FIG. 15 coincides with the timing diagram of the control system of FIG.
Since the operation of cycle 1 is the same as that of the first embodiment, description thereof will be omitted, and description will be made from cycle 2.
[0110]
When the chip enable signal / CE becomes L level, the node A becomes H level in synchronization with the detection of the state transition detection signal atdpz. At this time, since the write operation in cycle 1 is continuing, the command standby signal bicsz is at the H level, so that the node C is also at the L level in synchronization with the detection of the state transition detection signal atdpz. Here, as shown in the figure, when the write operation that has entered cycle 2 is completed and the signal icsx becomes H level, the node C holds L level as in the first embodiment.
[0111]
On the other hand, when an L level single pulse of the internal write command wrpx, which is generated in synchronization with the command standby signal bicsz that becomes L level at the end of the write operation, is input, the node D is at H level in synchronization therewith. A single pulse is generated, and an L level single pulse is generated at node B.
[0112]
In synchronization with the fall of the node B, the standby refresh command refpz is output, the refresh signal refz is set to H level, and the refresh operation is performed.
[0113]
When the refresh operation is completed and the signal icsx becomes H level and the refresh signal refz becomes L level, the write command delay circuit 600 outputs the write command delay signal wrpdx in synchronization with the fall. This signal is input to the RAS system operation control circuit 300, the row address strobe signal rasz is set to H level, and the write operation in cycle 2 is started.
[0114]
As described above, according to the second embodiment of the present invention, when the write operation does not end by the start of the write operation of the next cycle, the refresh operation can be performed before the write operation of the next cycle. it can.
[0115]
Note that the external configuration of the control system of the first embodiment shown in FIG. 1 shown in FIG. 7 can also be applied to the control system of the first embodiment. However, in the second embodiment, the write command delay signal wrpdx is input instead of the internal write command wrpx among the internal command signals input to the bit line control circuit 730 of FIG.
[0116]
Further, in the refresh / command determination circuit 100b of the second embodiment, the case where the write operation is further performed after the write operation has been described, but the semiconductor memory device of the first embodiment has been described. When a read operation is performed after a simple operation, that is, a write operation, the standby refresh operation can be performed after the read operation.
[0117]
Finally, the overall configuration of the semiconductor memory device of the present invention will be described.
FIG. 16 is an overall configuration diagram of the semiconductor memory device.
The semiconductor memory device includes input buffers 906, 907, 908, and 909 connected to an address input terminal 901, command input terminals 902, 903, and 904, a data input / output terminal 905, an address input terminal 901, and command input terminals 902 to 904, respectively. , A refresh control circuit 910, an input / output buffer 911, an address latch / decode circuit 912, a control circuit 913, a data control circuit 914, a memory cell array 915, and a write amplifier / sense buffer circuit 916.
[0118]
Here, the address latch / decode circuit 912 includes an address latch circuit 710 and an address decode circuit 720 shown in FIG. The control circuit 913 includes the control system in the first embodiment shown in FIG. 1 or the control system in the second embodiment shown in FIG. 11, and further includes the control system shown in FIG. The address latch circuit 710 and the address decode circuit 720 are omitted. Memory cell array 915 includes the configuration shown in FIG. Write amplifier / sense buffer circuit 916 includes a write amplifier and a sense amplifier buffer connected to internal data buses DB, / DB shown in FIG.
[0119]
The refresh control circuit 910 includes a timer and the like, generates a refresh request signal srtz, and outputs it to the control circuit 913. The data control circuit 914 controls data input / output under the control of the control circuit 913.
[0120]
The operation of the semiconductor memory device shown in FIG. 15 will be briefly described below.
When the external address ADD is input to the address input terminal 901, it is input to the address latch / decode circuit 912 via the input buffer 906. Thereby, the decoded row address and column address are designated, and the word line and column in the memory cell array 915 are selected.
[0121]
On the other hand, when external control signals (chip enable signal / CE, write enable signal / WE, output enable signal / OE) are input, these are input to the control circuit 913 via the input buffers 907, 908, 909. Entered. Based on these control signals, the above-described write operation and read operation are performed on the memory cell array 915, and data is transferred via the input / output buffer 911 under the control of the data control circuit 914 at the selected address. Input / output. The refresh is performed by inputting a refresh request signal srtz generated by the refresh control circuit 910 to the control circuit 913.
[0122]
【The invention's effect】
As described above, in the present invention, Write cycle is longer than normal operation mode After the write operation, it is possible to prevent a collision between the standby refresh and the read operation as the next command operation, and to shorten the write recovery time.
[Brief description of the drawings]
FIG. 1 is a block diagram of a part of a control system of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining an operation in a control system of the semiconductor memory device according to the first embodiment;
FIG. 3 is a circuit configuration diagram of an example of a refresh / command determination circuit.
FIG. 4 is a timing diagram illustrating an operation of a refresh / command determination circuit.
FIG. 5 is a circuit configuration diagram of a command control circuit.
FIG. 6 is a circuit configuration diagram of a command standby signal generation circuit.
7 is a block diagram showing an external configuration of the control system of FIG. 1. FIG.
FIG. 8 is a circuit diagram showing a configuration example of a part of a core circuit.
FIG. 9 is a timing chart showing an operation of the semiconductor memory device according to the embodiment of the present invention.
FIG. 10 is a timing chart for explaining the operation of the semiconductor memory device according to the first embodiment when writing is performed after a long-cycle write operation;
FIG. 11 is a block diagram of a part of a control system of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 12 is a circuit diagram of a write command delay circuit.
FIG. 13 is a timing chart for explaining the operation in the control system of the semiconductor memory device according to the second embodiment.
FIG. 14 is a circuit configuration diagram of a refresh / command determination circuit in the semiconductor memory device of the second embodiment.
FIG. 15 is a timing chart for explaining the operation of the refresh / command determination circuit in the semiconductor memory device of the second embodiment;
FIG. 16 is an overall configuration diagram of a semiconductor memory device.
FIG. 17 is a block diagram of a part of a control system of a conventional DRAM.
FIG. 18 is a timing chart showing an operation of a conventional semiconductor memory device when refresh is performed first.
FIG. 19 is a timing chart showing an operation of a conventional semiconductor memory device when a read or write operation is performed first.
[Explanation of symbols]
100a Refresh / command determination circuit
200 Command decode circuit
300 RAS system operation control circuit
400 Command control circuit
500 Command standby signal generation circuit

Claims (4)

In a semiconductor memory device that performs an internal refresh operation,
A command control circuit for generating an internal command signal for performing a command operation;
A command wait signal generating circuit for generating a command wait signal for waiting for the internal command signal for performing the next command operation when the write cycle is a write operation that is longer than the normal operation mode ;
Based on the command waiting signal, the relationship between the end of the write operation and the start of the next command operation is determined, and when the write operation does not end until the start of the next command operation, the next command If the operation is a read operation, a determination circuit that outputs a standby refresh command after completion of the read operation;
A semiconductor memory device comprising:   The determination circuit includes a flip-flop circuit that takes a NAND logic of the state transition detection signal and the command standby signal and holds the NAND logic to prohibit the internal refresh operation, and performs a read operation on the flip-flop circuit. 2. The semiconductor memory device according to claim 1, wherein the holding is released by inputting the internal command signal to be performed.   If the next command operation is a write operation, the determination circuit releases the flip-flop circuit that holds refresh inhibition, and outputs the standby refresh command before the start of the write operation. The semiconductor memory device according to claim 2.   4. The semiconductor memory device according to claim 3, further comprising a write command delay circuit that inputs the internal command signal corresponding to the write operation, and delays the output so as to detect and output the end of the internal refresh operation. .

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