JPS6199999A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To simplify a necessary redundancy circuit by storing a defective address signal and a defective bit address in said signal, as defective information, and switching only a data line which has become defective actually, to a redundancy data line. CONSTITUTION:Redundancy memory arrays YR-ARY1, YR-ARY2 are provided on memory arrays M-ARY1, M-ARY2, respectively, and the redundancy memory array is constituted of only one complementary data line, although the memory array is constituted of eight pairs of complementary data lines. A column switch C-SW1 and C-SW2 are provided with a switching circuit which is connected selectively to the redundancy data line. Also, an address storage means for storing a defective address signal and a defective bit address, and an address conveyor are provided. The address conveyor AC detects a designation of a defective address, inhibits a selecting operation of a defective data line in the address, and also connects the redundancy data line provided on the redundancy use memory array, to a common complementary data line corresponding to a defective bit.

Description

[Detailed Description of the Invention] [Technical Field] [This invention relates to a semiconductor memory device, and is used, for example, in a dynamic RAM (random access memory) that writes/reads storage information in units of multiple bits. It is related to effective technology.

[Background technology]

In semiconductor memory devices, the use of a defective bit relief method has been considered in order to improve the product yield. - In order to adopt the defective bit relief method, for example, a semiconductor memory device with a ×1 bit configuration (writing or reading data in units of 1 bit) is equipped with an appropriate storage means for storing defective addresses in the memo array. and its address comparison circuit, and redundancy circuit (spare memory array)
Additional circuitry is provided, such as:

However, in a semiconductor memory device that writes or reads data in units of multiple bits, such as a device with an x8 bit configuration, one address is assigned to each of the eight pairs of data lines, and the corresponding eight pairs of common data are assigned to each of the eight pairs of data lines. It connects to the line.

Therefore, even if one pair of data lines among the eight pairs of data lines is defective, all the data lines are switched to the spare memory array. For this reason, it is necessary to provide eight pairs of redundant data lines in the spare memory array as well, so it is necessary to provide an extra redundant data line for the actual defective data line. (For semiconductor memory devices with redundant bits, see, for example, Japanese Unexamined Patent Publication No. 53-41946.) [Object of the Invention] An object of the present invention is to provide a semiconductor memory device that substantially improves the defect recovery rate with a small number of spare memory arrays. The purpose is to provide a storage device.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor memory device with a multi-bit configuration,
A redundant data line in which a redundant memory array including at least one redundant data line is reserved, and the redundant data line is coupled to one of the above common data lines according to a defective address signal and a defective bit address. A selection circuit and a circuit for inhibiting the generation of any of the selection timing signals in accordance with the defective address and bit address are provided to repair the defective data line.

〔Example〕

FIG. 1 shows a dynamic RA according to an embodiment of the present invention.
A block diagram of M is shown. The dynamic RAM shown in the figure is a dynamic RAM that accesses in 8-bit units, although it is not particularly limited, and is formed on a semiconductor substrate such as single-crystal silicon using known semiconductor integrated circuit manufacturing technology. Ru.

In this embodiment, the memory array is arranged in two parts, M-ARYI and M-ARY2, although this is not particularly limited. Each memory array M-ARYI, M
-ARY2, eight complementary data line pairs are formed as one set, and are formed to extend in the vertical direction in the figure. In other words, instead of configuring the memory array by dividing it into 8 blocks (mats), one address is assigned to each pair of 8 complementary data lines adjacent to each other in the memory array. In the figure, they are arranged in order in the horizontal direction. By doing so, the memory array and its peripheral circuits can be simplified.

Row-related address selection lines (word lines) are connected to each of the memory arrays M-ARY1. They are formed in common with respect to M-ARY2 in the horizontal direction, and are arranged in order in the vertical direction in the figure. - The above complementary data line pair is connected to column switches C-3Wl, C
-8 common complementary data line pairs CDI, C via 5W2
Selectively connected to D2. In the figure, the common complementary data line pair runs in the horizontal direction. This common complementary data line pair CDI, CD2 is connected to main amplifiers MAI, MA2.
are connected to the respective input terminals.

Sense amplifier SA1. SA2 receives the minute read voltage of the complementary data line pair of the memory array, is activated by the timing signal φpa, and increases the complementary data line pair to high level/low level according to the read voltage:
It is something to do.

The row address buffer R-ADB receives m from an external terminal.
It receives the +l bit address signal RAD, forms internal complementary address signals aO-am, 70-τm, and sends them to the row address decoder R-DCH. Note 1. In the following description and drawings, a pair of internal complementary address signals;
For example, let aQ, 0 be expressed as an internal complementary address signal a-0.

Therefore, the internal complementary address signals aQ-3m, a
Q~1m is expressed as internal complementary address signal aQ~1m.

Row address decoder R-DCR selects one word line in accordance with the address signals 10-am in synchronization with word line selection timing signal φX.

Column address pants 1C-ADB receives address signal CAD of fi+l bits from an external terminal, forms internal complementary address signals a Owan, a Owan, and sends them to column address decoder C-0CR. In addition, in accordance with the representation of the internal complementary address signals, in the drawings and the following description, the internal complementary address signals aO to a
n+aO=an is expressed as internal complementary address signal O−Satn.

The column address decoder C-DCR forms a selection signal synchronized with the data line selection timing signal φy for eight complementary data line pairs in accordance with the address signals aQ to An.

The column switches c-swi and c-3w2 receive the selection signal and connect the eight pairs of complementary data lines to the corresponding eight pairs of common complementary data lines. In addition, in the same figure, ff1J
The illustrated complementary data line pair and the common complementary data line pair are represented by one line.

The input/output circuit I10 is composed of a main amplifier and a data output cover sofa for reading, and a data input cover sofa for writing. During reading, the input/output circuit I10 amplifies one of the main amplifiers MAI or MA2, which is activated, and outputs the data to the outside. Send to terminal DA. Also, during a write operation, the (i write output is transferred to the common complementary data line pair CD1.CD).
Supply to 2. In the figure, this write signal path is omitted.

Internal control signal generation +111iJ path TG has two external control signals %C5 (chip select signal), WE (write/f
Although not particularly limited, the address signal change detection signal φ formed by the address signal change detection circuit ATD receiving the address signals aO to ant and aQ-an is received. Forms and sends various timing signals necessary for operation.

do.

In this embodiment, the memory array M-A RYl,
Redundant memory array YR-ARY1 in M-ARAY2
．． YR-ARY2 is provided respectively. These redundant memory arrays YR-ARYI and YR-ARY2
Although the memory arrays M-ARYI and M-AYRY2 are composed of eight pairs of complementary data lines, they are composed of only one complementary data line as will be described later.

And for column switches c-swi and C-3W2,
A switch circuit (multiplexer) is provided to selectively connect the pair of redundant data lines and the eight pairs of common complementary data lines.

Further, an address storage means for storing a defective address signal and a defective bit address is provided, and a defective address stored by comparing the defective address signal and an address signal aO-an (Jl) from an address buffer C-ADB is input. An address conveyor AC is provided, which includes a column address comparison circuit that detects whether a defective address has been specified. In addition to prohibiting the selection operation of the defective data line in the redundant memory array YR-ARY1 (or YR-.
', RY2) is switched to a selection operation in which the redundant data line provided in the bit is connected to the common complementary data line corresponding to the defective bit.

Although it is desirable to provide a similar redundant memory array for the data line, it is omitted in the figure because it is not directly related to this invention.

212th! 1 shows a circuit diagram of an embodiment of the above column switch circuit. In the figure, the MOSFET is an enhancement type N-channel MOSFET.
, T.

Complementary data line DO1DO of memory array M-ARY
~D7. D7 is MO5FE that constitutes the column switch
TQ1. Q2-Q7. They are respectively connected to common complementary data lines CDO, CD0-CD7°CD7 via Q8.

These M OS F E T Q 1.

Q2-Q7. The gate of Q8 is shared, and C data line selection timing signals φyO to φy7 are supplied through transmission gates MO5FETQ9 to Q12, which are commonly controlled by the output signal of the column address decoder D-OCR. These word 1g selection timing signals φ
yO to φy7 are the word line selection timing signal φy
formed based on.

Further, the spare memory array YR-ARY is constituted by a pair of complementary data lines, D. The pair of complementary data lines '5 are each connected to a switch MO5FETQI3.
．． Ql 4-Q19. The common complementary data lines CDO, CDO~ through the multiplexer configured by Q20.
CD? , CD7. These switches MO3FETQ13. Q14-Q19. The gate of Q20 receives a data line selection timing signal φyO° which is formed by the address conveyor AC and is formed according to the defective bit address when the defective address is determined as tit.
~φy7゛ is supplied.

That is, the complementary data lines Do, DO to D7 .
Of the complementary data lines D2.D7, the complementary data lines D2. If D2 is defective, these 8
Pairs of complementary data lines DO, DO to D7. The address assigned to D7 and the complementary data line D2 .
The bit address of D2 is written. Then, the defective data line D2. When accessed to an address containing D2, the address comparison circuit detects this. Based on this detection output, the address conveyor AC refers to the defective bit and, on the other hand, inhibits the output of the data line selection timing signal φy2.

This allows the MO3FET that constitutes the column switch to
Q5. Since only Q6 remains off, defective data lines D2. Selection of D2 is prohibited.

Further, the address conveyor AC refers to the defective bit address and, on the other hand, in synchronization with the data line selection timing signal φy, the spare memory array YR-A
RY data line selection timing signal φy2' is generated. This causes switch MO3FETQ17. Q1
Since B is turned on, the spare complementary data line, D
is the defective complementary data line D2. ．． D2 is replaced by a common complementary data line CD2. Connected to CD2.

〔effect〕

(1) In a semiconductor memory device with a multi-bit configuration, by storing the defective address signal and the defective bit address therein as -defective information, only the actually defective data line is switched to a redundant data line. This has the effect that the required redundancy circuit can be simplified.

(2) According to the above (11), a larger number of redundant data lines can be formed within the same occupied area, so that the defect relief rate can be improved.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. Not even. For example, writing or reading may involve multiple bits (eg, 4 bits, etc.). Further, the specific circuit configuration of each circuit block can be implemented in various ways.

For example, the address signal supplied from the external glass may be supplied from a common external terminal in a time-sharing manner with the row address signal and the column address signal.

[Application field]

Although the invention made by the present inventor is applied to dynamic RAM, which is the background field of application, it is not limited to this, and for example, it can be applied to static RAM or programmable RO.
Even in M (read-only memory), the present invention can be widely applied on the condition that multiple-bit/7-bit signals are written or read as described above.

[Brief explanation of drawings]

FIG. 1 is an internal purchasing block diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram of a column switch showing a specific embodiment thereof. M-ARYI, M-ARY2...Memory array, SA
1 + S A 2...Sense amplifier, R-ADH.
- Row address buffer, C-3W1. C-3W2...
Column switch, C-ADB...Column address buffer, R-DCR...Row address decoding, C-DCR
I, C-DCR2...Column address decoder, MAL
, MA2... Main amplifier, T G... Timing generation circuit, ATD... Address signal change detection circuit, Ilo...
・Input/output circuit, AC... Address conveyor Figure 1 C^0 00~D7

Claims (1)

[Claims] 1. A column switch that connects a plurality of data lines to which one address is assigned and a common data line corresponding thereto by a plurality of selection timing signals;
a redundant memory array including one redundant data line, a redundant data line selection circuit for coupling the redundant data line to one of the common data lines in accordance with the defective address signal and the defective bit address, and the defective address signal and the defective bit address. 1. A semiconductor memory device comprising: a defective address switching circuit comprising a circuit for inhibiting generation of any one of the selection timing signals described above according to a bit address. 2. The semiconductor memory device according to claim 1, wherein the plurality of data lines to which one address is assigned are provided adjacent to each other. 3. The semiconductor memory device according to claim 1 or 2, wherein the semiconductor memory device is a dynamic RAM.