GB2165971A - A semiconductor memory - Google Patents

Abstract

In a multi-bit semiconductor memory having a redundant memory YR-ARY, any faulty data line CD is replaced with a redundant data line. To decrease the number of redundant data lines required when a plurality of data lines are selected at once, the semiconductor memory is furnished therein with first storage means (MMo Fig. 3) for forming signals necessary for an address comparing operation in an address comparing circuit (ACo-ACn) and also second storage means (DM1...DM3...) for forming signals indicative of data line positions to be remedied. When a faulty address has been detected as the result of the address comparing operation, the second storage means is referred to, and the data line indicated by the second storage means is replaced with the redundant data line. This arrangement can decrease the number of the redundant data lines when compared with an arrangement wherein all the data lines to be simultaneously selected are replaced with redundant data lines. <IMAGE>

Description

SPECIFICATION A semiconductor memory This invention relates to a semiconductor memory device, and more particularly to a technique which is effective when applied to, for example, a dynamic RAM (random access memory) wherein storage information is written/read in units of a plurality of bits.

Regarding semiconductor memory devices, it has been considered to utilize a defective-bit saving system for the purpose of raising the available percentage of products. In order to adopt the defective-bit saving system, the semiconductor memory device of, for example, X 1 bit arrangement (which writes or reads data in single-bit unit) is provided with proper storage means to store faulty addresses in a memory array and additional circuits such as an address comparator circuit and a redundant circuit (spare memory array).

In the case of a semiconductor memory device which writes or reads in multiple-bit unit, for example, one of X8 bit arrangement, a single address is allotted to eight pairs of data lines, and the eight pairs of data lines having an identical address signal are connected to eight pairs of common data lines respectively corresponding thereto. In this case, even when only one pair of data lines are faulty among the eight pairs of data lines to be connected, all these eight pairs of data lines are replaced with a spare memory array. Therefore, the spare memory array needs to be furnished with eight pairs of redundant data lines. In other words, redundant data lines in excess of actual faulty data lines must be provided. A semiconductor memory device which is provided with redundant bits, is disclosed in Japanese Patent Application Laid-Open No.

53-41946.

It is an object of the present invention to provide a semicondcutor memory device which enhances a substantial defect saving rate with a small number of spare memory arrays.

The novel aspects of the present invention will now be summarized below. In a semiconductor memory device of plural-bit arrangement, faulty-bit address signals for indicating faulty data lines among one set of data lines to be saved are prepared, and when any faulty address has been indicated, those of the plurality of data lines except one indicated by the faulty-bit address signal are selected, and a redundant data line is selected in lieu of the data line indicated by the faulty-bit address signal.

The present invention will now be described in greater detail by way of example with reference to the accompanying drawings, wherein: Figure 1 is a block diagram showing an embodiment of a dynamic RAM; Figure 2 is a circuit diagram of a column switch for use in the semiconductor memory shown in Fig. 1; Figure 3 is a circuit diagram of an address comparator, a redundant decoder, a faulty-bit address signal generator and a selection timing signal controller; and Figure 4 is a timing chart waveform diagram to assist in the explanation of the circuits shown in Fig. 3.

Referring first to Fig. 1, which is a block diagram of a dynamic RAM, it should be noted that although not especially restricted, the dynamic RAM shown in Fig. 1 is a dynamic RAM which accesses in units of 8 bits and which is formed on a semiconductor substrate such as of single-crystal silicon by known techniques for manufacturing semiconductor integrated circuits.

In this embodiment, though not especially restricted, a memory array is divided in two as M-ARY1 and M-ARY2 which are arranged on the left and right sides respectively. This arrangement of each memory array will be better understood from Fig. 2 to be referred to later. In each of the memory arrays M ARY1 and M-ARY2, eight pairs of complementary data lines are combined into one set, and they are formed so as to extend in the vertical direction in the figure. In other words, in the embodiment, the memory array is not constructed in eight divided blocks (or mats).

Though not especially restricted, a single column address is allotted to one pair of complementary data lines adjoining each other among the eight pairs of complementary data lines within the identical memory array, and the respective complementary data lines are successively arranged in the lateral direction in the figure. Thus, the memory array and the peripheral circuits thereof can be simplified.

Though not especially restricted, row-system address select lines (word lines) are made common to both the memory arrays M-ARY1 and M-ARY2 and are successively arranged in the vertical direction in the figure.

The pairs of complementary data lines are selectively connected to eight pairs of common complementary data lines CDL or CDR through a column switch C-SW1 or C-SW2. In the figure, the pairs of common complementary data lines run in the lateral direction. The pairs of common complementary data lines CDL and CDR are respectively connected to the input terminals of main amplifiers MA1 and MA2.

Sense amplifiers SA1 and SA2 which receive read voltages of slight levels applied from selected ones of memory cells to the complementary data line pairs of the memory arrays, are brought into operating states by a timing signal fpa and amplify the read voltages to a definite high level/low level.

Precharge circuits PC1 and PC2 are operated by a precharge timing signal fpc which is gen erated before starting the selection of the memory cells, and they bring the paired complementary data lines to a precharge level or reference level which is substantially equal to Vac/2 (where Vcc denotes a power source vol tage).

A row address buffer R-ADB receives rowsystem address signals RAD of (m+ 1) bits through external terminals, and forms internal complementary address signals arO-arm and arO-arm to be supplied to a row address decoder R-DCR. In the ensuing description and the drawings, one pair of internal complementary address signals, for example, arO and arO shall be expressed as an internal complementary address signal, for example, arO.

Accordingly the internal complementary address signals arO-arm and arO-arm are expressed as internal complementary address signals arO-arm.

The row address decoder R-DCR selects one word line of each of the two memory arrays M-ARY1 and M-ARY2 in accordance with the address signals arO-arm and in synchronism with a word line select timing signal A column address buffer C-ADB receives column-system address signals CAD of (nfl) bits from external terminals, and it forms internal complementary address signals ac0-acn and acO-acn and sends them to column address decoders C-DCR1 and C-DCR2. In conformity with the way of expressing the internal complementary address signals described above, the internal complementary address signals ac0-acn and ac0-acn shall be expressed as internal complementary address signals acO-acn in the drawings and the ensuing description.

Each column address decoder C-DCR forms select signals for selecting the eight pairs of complementary data lines, namely, one set of complementary data line pairs, in accordance with the address signals ac0-acn and in synchronism with a data line select timing signal v Upon receiving the select signals, the column switch C-SW1 or C-SW2 connects the eight pairs of complementary data lines of the memory array M-ARY1 or M-ARY2 to the eight pairs of common complementary data lines corresponding thereto. In the figure, each of the complementary data line pairs or the common complementary data line pairs exemplarily shown is depicted with a single line.

The main amplifiers MA1 and MA2 have their operations controlled by timing signals Cimal and #,, and amplify the data signals of the common complementary data lines CDL and CDR, respectively.

Though not shown in detail, an input/output circuit I/O is composed of a data output buffer for reading operation, the circuit I/O amplifies the output of one main amplifier MA1 or MA2 which is brought into the operating state and delivers the amplified signal to external terminals DA. On the other hand, in the writing operation, the circuit I/O supplies the write outputs thereof to the pairs of common complementary data lines CDL or CDR. In the figure, signal paths for the writing are omitted.

An internal control signal generator TG receives two external controi signals CS (chip select signal) and WE (write enable signal) and a transition detection signal 0 for the address signals, which is formed by an address signal transition detector ATD receiving the address signals arO-arm and ac0-acn though not especially restricted, and forms and delivers the various timing signals necessary for the memory operation.

In this embodiment, the memory arrays M ARY1 and M-ARY2 are respectively provided with redundant memory arrays YR-ARY1 and YR-ARY2. Notwithstanding that each of the memory arrays M-AR1 and M-ARY2 is composed of the eight pairs of complementary data lines, each of the redundant memory arrays YR-ARY1 and YR-ARY2 is composed of only one pair of complementary data lines as will be described later. In correspondence with the provision of the redundant memory array YR-ARY1 and YR-ARY2, the column switch C-SW1 and C-SW2 are provided with switching circuits(multiplexor) which connects the pair of redundant data lines to a selected one of the eight pairs of common complementary data lines. The practicable arrangements of the memory array, the redundant memory array and the switching circuit will be detailed with reference to Fig. 2 later.

The illustrated RAM is also furnished with an address comparing circuit AC which includes address storing means to store faultyaddress signals and faulty-bit addresses, and a column address comparator to compare the faulty-address signals and the address signals ac0-acn supplied from the address buffer C ADB and to detect that the stored faulty addresses have been input. When any faulty address has been indicated, this address comparing circuit AC refers to the faulty-bit address in the faulty address, thereby to inhibit the operation of selecting faulty data lines in the selected address and to perform the operation of connecting the redundant data lines laid in the redundant memory array YR-ARY1 (or YR-ARY2), to the common complementary data lines corresponding to the faulty bit. The practicable arrangement of the address comparing circuit AC will be detailed with reference to Fig. 3 later. In the address comparing circuit AC, address storage means for the faulty addresses and address storage means for the faulty-bit addresses are programmed with program signals which are applied to terminals PO to Pn+3.

Although the provision of similar redundant memory arrays for the data lines is desirable, it is not directly pertinent to this invention and is therefore omitted from the figure.

The outline of the operation of the illustrated RAM will now be explained.

The access of the RAM is started when the chip select signal CS is changed from a chip non-select level of high level to a chip select level of low level.

Upon the starting of the chip select, the timing signal ssspc of predetermined pulse width for the precharge circuits PC1 and PC2 is first output from the timing generator TG. Thus, the complementary data lines in the respective memory arrays are brought to the precharge level which is substantially equal to Vac,/2.

After the output of the timing signal fpc has been stopped, in other words, after the operations of the precharge circuits PC1 and PC2 have been stopped, the word line select timing signal (p, is generated. Thus, among the plurality of word lines of each of the memory arrays M-ARY1 and M-ARY2, each one specified by the row address signal RAD is selected. That is, the memory cells specified by the row address signal RAD are selected. The selected memory cells afford read signals to the corresponding pairs of complementary data lines of the respective memory arrays.

After the generation of the timing signal fI the timing signal fpd is produced from the timing generator TG. Thus, the sense amplifiers SA1 and SA2 are operated.

After the production of the timing signal 0",, the timing signal Xy is generated. In accordance with the generation of the timing signal the select signal for selecting the data line is delivered from the column decoderC-DCR1 or C-DCR2.

Here, the eight complementary data line pairs constituting one set (hereinbelow, termed 'unit data line group') have one of column addresses set in one-to-one correspondence respectively. In a case where the unit data line group includes any faulty pair of complementary data lines which is unsuited for reading or writing data on account of, for example, a defective memory cell, defective wiring involving disconnection or short-circuit, or the defect of the sense amplifier or the column switch circuit, this unit data line group is regarded as a faulty data line group. The column address corresponding to such faulty data line group is regarded as a faulty address.

According to this embodiment, bit address information items in one-to-one correspondence are set for the respective pairs of complementary data lines which constitute the faulty data line group. As stated before, the bit address information items are held in the address storage means within the address comparing circuit AC.

According to this embodiment, when the faulty address has been indicated by the external address signal, the column switch circuit C-SW1 or C-SW2 is controlled, whereby the selection of the faulty complementary data line pair is inhibited, and the complementary data line pair in the redundant memory array YR ARY1 or YR-ARY2 is selected instead.

The timing signal (p or fmar is generated in synchronism with the timing signal fyt in other words, in synchronism with the operation of the column switch circuit C-SW1 or C-SW2.

The timing signal fmal or 25mar operates the main amplifier MA1 or MA2 which corresponds to the memory array M-ARY1 or M-ARY2 to be selected, so that the data signal applied to the common complementary data lines CDL or CDR is amplified.

The data signal amplified by the main amplifier MA1 or MA2 is delivered to the data terminals DO-D7 through the input/output circuit l/O.

If the write enable signal WE is indicating the write level which is the low level, the data signal at the data terminals DO-D7 is written into the memory cells of the memory array M ARY1 or M-ARY2 through the input/output circuit I/O, the main amplifier MA1 or MA2 and the column switch circuit C-SW1 or C SW2.

The access of the RAM is also started responsively when the state of at least one of the address signals RAD and CAD is changed in the chip select state (CS: low level).

When the transition of the address signal(s) RAD or/and CAD has been detected by the address signal transition detector ATD, the detection pulse 0 is output from the detector ATD, and the timing generator TG is operated.

In response to the detection pulse (p, the generation of the timing signals (5pea fx fyl (py (p and fmar is stopped, whereupon the timing signal "c is generated for a predetermined period. That is, the circuits of the sense amplifiers SAl, SA2, the column switch circuits C SW1, C-SW2, etc. are brought into the nonoperating states and all the word lines are brought to the non-select level, whereupon the precharge circuits PC1 and PC2 are brought into the operating states for the predetermined period so as to bring the respective pairs of complementary data lines to the precharge level.

Next, the word line select timing signal fy is generated thereby to select the word lines of the memory arrays M-ARY1 and M-ARY2, and the timing signal (pupa is generated thereby to operate the sense amplifiers SA1 and SA2.

Thenceforth, the various timing signals similar to the above are generated, whereby circuit operations similar to the above are performed.

In Fig. 2, a circuit diagram of one embodiment of the column switch circuit is shown along with parts of the memory array M-ARY and the redundant memory array YR-ARY. Referring to the figure, MOSFETs are N-channel MOSFETs of the enhancement mode.

The memory array M-ARY includes complementary data line pairs DO, DO to D7, D7, word lines WO and W1, and memory cells MC1 to MC8. Each of the memory cells is composed of an address selecting MOSFET Qm and an information storing capacitor Cm.

One current carrying electrode of the address selecting MOSFET Qm is regarded as the data input/output terminal of the memory cell and is coupled to the corresponding data line, while the gate electrode thereof is regarded as the select terminal of the memory cell and is coupled to the corresponding word line.

The illustrated complementary data line pairs DO, DO to D7, D7 constitute a unit data line group which has one column address.

The redundant memory array YR-ARY is composed of complementary data line pairs DY and DY and a plurality of memory cells RM1 and RM2, and has the same arrangement as that of the memory array M-ARY.

In the arrangement of Fig. 2, the column switch circuit C-SW is composed of MOSFETs 01 to Q8 and Q9 to Q12. The column switch circuit C-SW also includes a multiplexor MPX which is composed of MOSFETs 013 to 020.

The complementary data lines DO, DO-D7, D7 of the memory array M-ARY are respectively connected to common complementary data lines CDO, CDO-CD7, CD7 through the MOSFETs 01, Q2-07, 08 which constitute the column switch. The gates of the MOS FETs 01, 02-Q7, Q8 are respectively made common and supplied with data line select timing signals fvO~fv7 through the transfer gate MOSFETs 09-012, which are controlled in common by the output signal of the column address decoder D-DCR. These data line select timing signals Ao-0y7 are formed on the basis of the data line select timing signal fv.

The spare memory array YR-ARY includes one pair of complementary data lines DY and DY. The pair of complementary data lines DY and DY are selectively connected to the common complementary data lines CDO, CDO-CD7, CD7 through the multiplexor MPX composed of the switching MOSFETs 013, Q14-Q19, Q20, respectively. The gates of these switching MOSFETs 013, Q14-Q19, Q20 are supplied with data line select timing signals 090'-4S7' which have been formed by the address comparing circuit AC in accordance with the faulty bit addresses at the time of the indication of the faulty address.

The data line select timing signals yO and (pyo' are timing signals for coupling the respective data line pairs of the memory array M ARY and the redundant memory array YR ARY to the first pair of common complementary data lines CDO and CDO. The signals fyO and (py0, are complementarily brought to the high level in accordance with the bit address information of the address comparing circuit AC at the data line select timing.

Likewise, the timing signals fy1 fy1 to y7x fact are brought to the high level complementarily to each other at the data line select timing, respectively.

More specifically, in a case where among the illustrated complementary data lines DO, DO-D7, D7, the complementary data lines D2, D2 are defective, the address allotted to the eight pairs of complementary data lines DO, WO-D7, D7 and the bit address information of the complementary data lines D2, D2 of the third bit are written in the storage means of the address comparing circuit AC beforehand. When the column address including the defective data lines D2, D2 is accessed, the address comparator detects this access. In accordance with the resulting detection output, the address comparing circuit AC refers to the faulty-bit address information and inhibits the output of the data line select timing signal fy2 on one hand.Thus, only the MOSFETs 05, 06 constituting the column switch are held in the 'off' states, so that the selection of the defective data lines D2, D2 is inhibited. On the other hand, by referring to the defective-bit address information, the address comparing circuit AC generates the data line select timing signal fact for the space memory array in synchronism with the data line select timing signal fye Thus, the switching MOSFETs 017, Q18 are brought into the 'on' states, so that instead of the defective complementary data lines D2,D2, the spare complementary data lines D, D are connected to the common complementary data lines CD2, CD2.

Fig. 3 is a circuit diagram of the address comparing circuit AC.

The address comparing circuit AC is constructed of address comparators ACo to ACn, an address decoder ACd, storage means DM1 to DM3 for bit address information, decoders DDO to DD7, and timing signal controllers TCO to TC7.

Each of the address comparators ACo to ACn is composed of memory means MMo and address comparing MOSFETs 027, 028 which are switch-controlled by the memory means.

Though not especially restricted, the memory means MMo is composed of a fuze element FUZ which is a program element made of, e. g., polycrystalline silicon, and MOSFETs 024 to Q26 which serve to produce a signal of a good level even when the fuze element FUZ is not favorably severed and to produce a signal of a level complementary thereto. The MOSFET Q25 constitute a kind of inverter together with the MOSFET 026, and it is dynamically driven by a timing signal fc1 in order to lower the power consumption of the circuit.

In the address comparator ACo, in a case where the fuze element FUZ is not severed, the drain of the MOSFET 024 is maintained at the high level which is substantially equal to the power source voltage Vcc, and that of the MOSFET 026 is maintained at the low level which is substantially zero volts. Thus, the MOSFETs 027 and Q28 are respectively held in the 'off' state and the 'on' state. As a result, the output arO of the address comparator ACo becomes equal to the address signal aO.

In a case where the fuze element FUZ is severed, the conduction states of the MOS FETs 027 and 028 are reversed, and the output arO becomes equal to the address signal aO accordingly.

Likewise, the address comparator ACn selects either of the address signals an and a~n, depending upon whether or not the fuze element in this comparator is severed.

Though not especially restricted, the fuze element FUZ is severed by electrical fusion.

More specifically, terminals pO-pn which are formed of, e.g., pad electrodes disposed on a semiconductor chip are coupled to the fuze elements FUZ in the respective circuits ACo-ACn.

When a faulty column address has been detected in a test such as semiconductor wafer test, voltages of levels corresponding to respective address signals at that time are applied to the terminals pO-pn through a conductor member such as tungsten needle. As a result, faulty-address information items are written into the circuits ACo-ACn. By way of example, when the voltage of substantially zero volts is applied to the terminal pO in correspondence with the low level of the address signal aO, the fuze element FUZ is fused. Contrariwise, when the terminal pO is at the level substantially equal to the power source voltage Vcc in correspondence with the high level of the address signal aO, the fuze element FUZ is left unsevered.

Owing to the fact that the faulty-address information items are previously written or programmed in the circuits ACo-ACn in this manner, when the address signals aO-an indicate the faulty-column address, all the outputs arO-arn of the respective circuits ACo-ACn are responsively put into the low level, and when none of the address signals aO-an indicates the faulty address, at least one of the outputs arO-arn is put into the high level.

The decoder ACd is composed of MOSFETs Q29-031 which constitute a dynamic NOR circuit. The output (p,# of the decoder ACd is put into the high level responsively when the faulty-column address is indicated.

According to this embodiment, the bit address information is written in the three storage means DM1-DM3 though no special restriction is intended. As seen from Fig. 3, each of the storage means DM1-DM3 has the same arrangement as that of the memory means MMo. One of eight sorts of bit address information is stored by the three storage means DM1-DM3.

The decoders DDO-DD7, each of which is composed of MOSFETs 032-034, decode the outputs dml-dm3 of the storage means Dm 1-Dm3.

The output Ipidlo of the decoder DDO is maintained at the high level responsively when the bit address information of the storage means DM1-DM3 indicates the first bit address, and it is maintained at the low level when the bit address information indicates any other bit address. Likewise, the output fed17 of the decoder DD7 is maintained at the high level when the bit address information indicates the eighth bit address.

As illustrated in the figure, each of the timing signal controllers TCO-TC7 is composed of MOSFETs 035-043, and these controllers are operated by the output (p,# of the decoder ACd, the outputs (pd1o#(pd17 of the corresponding decoders DDO-DD7, the timing signals f and #,, and the data line select timing signal (py.

The MOSFETs 037 to 041 are provided in order to complementarily switch-control the transfer gate MOSFETs 035 and 036, and the MOSFETs 042 and 043 are provided in order to forcibly bring one of two timing signals to be delivered from each controller, to the low level.

Fig. 4 is a waveform diagram of the address comparing circuit AC in Fig. 3. Now, the operations of the circuits in Fig. 3 will be described in connection with the waveform diagram of Fig. 4.

When the chip select signal CS is brought to the low level as shown at A in Fig. 4, the timing signal fc, which is output from the timing generator TG in Fig. 1 is responsively rendered the high level for a predetermined period as shown at C in Fig. 4. ~~~~ Unfavourable levels of the outputs dm1, arO etc., which are incurred by undesirable leakage currents under the 'off' states of the MOSFETs 022, 025 etc., are restored to favorable levels again owing to the above fact that the timing signal fcl is rendered the high level.

As illustrated at D in Fig. 4, the timing signal Ii5c2 which is produced from the timing generator TG is rendered the high level for the predetermined period with some delay relative to the timing signal fc,.

The address decoder ACd is precharged by the timing signal c2 If the column address signals aO-an are indicating the faulty address, the output l -d of the address decoder ACd is rendered the high level in synchronism with the timing signal 5ac2 as shown by a solid line at F in Fig. 4. In contrast, if the address signals aO-an are not indicating the faulty address, the output 0,d is maintained at the low level as shown by a broken line at F in Fig. 4.

As illustrated at E in Fig. 4, the timing signal #, which is provided from the timing gen erator TG is rendered the high level responsively when the chip select signal CS is brought to the low level, and it is rendered the low level after the timing signal sXc. is brought to the low level. The timing signal (p,# needs, at least, to be rendered the high level before the timing signal fy is brought to the high level, and it may well be rendered the high level after the timing signal fc, is brought to the low level.

The decoders DDO-DD7 are precharged by the timing signal (p,a which has been rendered the high level.

Now, if the outputs of the storage means DM1-DM3 are indicative of the first bit address, all of the MOSFETs 033 to 034 connected in parallel in the decoder DDO are maintained in the 'off' states. In this case, the output zero of the decoder DDO is held at the high level as shown by a solid line at G in Fig.

4. In contrast, if the outputs of the storage means DM1-DM3 are indicative of another bit address, at least one of the MOSFETs 033 to 034 is maintained in the 'on' state, so that the output zero of the decoder DDO is held at the low level as shown by a broken line at G in Fig. 4.

As illustrated at J in Fig. 4, the data line select timing signal fry is brought to the high level at a timing after the operation of the sense amplifiers SA1 and SA2 in Fig. 1.

In accordance with the various signals stated above, the timing signal controller, for example, TCO operates as follows.

First, the MOSFET 037 is brought into the 'on' state by the timing signal fc1 of early timing at the start of the chip select. In consequence of the 'on' state of the MOSFET Q37, a node n1 is precharged to the high level as shown at H in Fig. 4. Since the MOS FET 041 is brought into the 'on' state by the high level of the node nl, a node n2 is rendered the low level as shown at I in Fig. 4.

Next, when the timing signal (p,3 is brought to the high level as shown at E in Fig. 4, the MOSFET 039 is responsively brought into the 'on' state.

If the output Y0fd of the address decoder ACd is at the high level as shown by the solid line at F in Fig. 4 in accordance with the indication of the faulty address, the MOSFET Q40 is brought into the 'on' state. Consequently, a current path is formed between the output of the decoder DDO and the node n2 with the MOSFETs 039 and 040 intervening therebetween. Therefore, the potential of the node n2 is determined by the output of the decoder DDO.

As described before, if the first bit address is set in the storage means DM1-DM3, the output S0d10 is brought to the high level. In this case, the node n2 is rendered the high level in synchronism with the timing signal (p,# as shown by a solid line at I in Fig. 4. When the node n2 has been rendered the high level in this manner, the MOSFET 038 is responsively brought into the 'on' state, so that the node n1 is brought to the low level as shown by a solid line at H in Fig. 4.

A substantial latch circuit composed of the MOSFETs Q37-041 is put in a static operation state or a ratio operation state during the period during which all of the timing signals (p, and (p,s and the signal frd are held at the high level. In order to permit the level changes of the nodes n1 and n2 in the static operation period, the MOSFETs are designed so as to have proper ratios between 037 and 038 and between Q32, 039 and Q40 and 041, respectively. If a high speed operation is not required of the RAM and accordingly the level change timing of the node n2 may well be late, the timing signal (p,s for the MOSFET 039 may well be rendered the high level after the MOSFET 037 has been brought into the 'off' state.

If the output zero of the decoder DDO is maintained at the low level as shown by the broken line at G in Fig. 4, the node n2 is maintained at the low level as shown by a broken line at I in Fig. 4 and the node n1 at the high level as shown by a broken line at H, irrespective of the 'on' and 'off' states of the MOSFETs 039 and 040.

Even in the case where the output zero of the decoder DDO is maintained at the high level, if the output word is maintained at the low level as shown by the broken line at F in Fig.

4, the MOSFET 040 is responsively brought into the 'off' state, so that the node n2 is held at the low level.

That is, the node n2 of the circuit TCO is rendered the high level in synchronism with the timing signal lfic3 only when the faulty column address is indicated and besides the first bit address is indicated.

One of the MOSFETs 035 and Q36 is brought into the 'on' state in accordance with the high and low levels of the nodes n1 and n2. The timing signal fy is transferred to one of the two output terminals of the timing signal controller TCO through that of the MOS FETs Q35 and 036 which is in the 'on' state.

Thus, the data line timing signal (pyo' is brought to the high level in synchronism with the timing signal fy when the faulty address is indicated and besides the first bit address is indicated by the storage means DM1-DM3.

On this occasion, the data line select timing signal yO is left intact at the low level by the 'off' state of the MOSFET Q35 and the latch circuit composed of the MOSFETs 042 and 043.

When, after the first operating cycle T1, the column address signal is changed as shown at B in Fig. 4, the subsequent operation is responsively executed (operating cycle T2).

At the start of the operating cycle T2, the data line select timing signal (py having been rendered the high level beforehand is brought to the low level. The timing signal sXvo or(pyo' set at the high level beforehand is brought to the low level in response to the low level of the timing signal fv because the MOSFET Q35 or Q36 has been brought into the 'on' state since then.

After the change of the timing signal fv to the low level, the timing signal (p,# is brought to the high level as in the foregoing.

Thenceforth, the various timing signals as thus far described are generated, whereupon the various circuits are operated.

According to this invention, the following effects can be attained: (a) In a semiconductor memory device of multiple-bit arrangement, a faulty-address signal and faulty-bit addresses in the particular address are stored as fault information, whereby only data lines which are really faulty are replaced with redundant data lines. This produces the effect that a required redundant circuit can be simplified.

(b) As a result of effect (a) above, a larger number of redundant data lines can be formed subject to an equal occupation area. This produces the effect that the defect remedying rate can be enhanced.

The following modifications or alternative arrangements of the above described dynamic RAM are possible: (a) The writing or reading may be performed in units of any plural bits (for example, 4 bits).

(b) The practicable circuit arrangement of each circuit block can have various aspects of performance. For example, address signals to be supplied from external terminals may well be row address signals and column address signals which are supplied from common external terminals by a time division system.

Whilst, the above described embodiment specifically relates to a dynamic RAM, it is also applicable to other semiconductor memory devices. For example, it is applicable to a static RAM or a programable ROM (read only memory), the principle being extensively applicable under the condition that signals of a plurality of bits are written or read as stated above.

Claims (10)

1. A semiconductor memory including: (a) a first data line which has a plurality of memory cells coupled thereto; (b) a plurality of second data lines each of which has a plurality of memory cells coupled thereto; (c) a plurality of common data lines; (d) a first switch circuit which is located between said first data line and said plurality of common data lines and which permits data of said first data line to be transferred to any one of said plurality of common data lines; (e) a second switch circuit which is located between said plurality of second data lines and said plurality of common data lines; and (f) a control circuit which switch-controls said first and second switch circuits so that, when the data of said first data line is to be afforded to one said common data lines, coupling between the common data line to have the data of said first data line afforded thereto and said second data lines may be inhibited.

2. A semiconductor memory according to claim 1, wherein said first switch circuit comprises a plurality of first insulated-gate field effect transistors which are located between said first data line and the respective common data lines and which are respectively switch-controlled by first timing signals provided from said control circuit; and said second switch circuit comprises a plurality of second insulated-gate field effect transistors which are respectively located between said second data lines and the corresponding common data lines and which are respectively switch-controlled by second timing signals provided from said control circuit.

3. A semiconductor memory according to claim 1 or 2, wherein one memory cell coupled to said first data line and one memory cell coupled to each of said second data lines have respectively select terminals thereof coupled to one word line so as to be simultaneously selected by said word line.

4. A semiconductor memory according to any one of the preceding claims, wherein said second switch circuit is switch-controlled so as to simultaneously couple the plurality of second data lines to the plurality of common data lines.

5. A semiconductor memory according to claim 2, wherein said second timign signals consist of a plurality of timing signals which are in one-to-one correspondence with said plurality of common data lines, said second timing signals being respectively supplied to said second insulatedgate field effect transistors through third insulated-gate field effect transistors which are respectively switch-controlled by a common select signal, and said first timing signals consist of a plurality of timing signals which are in one-to-one correspondence with said plurality of common data lines.

6. A semiconductor memory according to claim 2, further including: (g) an address comparing circuit which compares an input address signal and an address signal provided from storage means.

7. A semiconductor memory according to claim 6, wherein said control circuit receives an output of said address comparing circuit and a data line position indicating signal so as to inhibit delivery of one of said second timing signals indicated by said data line position indicating signal and simultaneously generate one of said first timing signals when the comparison signal has been provided from said address comparing circuit.

8. A semiconductor memory according to claim 7, wherein said each memory cell is a dynamic memory cell.

9. A semiconductor memory including: (a) memory arrays in each of which data of a plurality of bits can be simultaneously accessed; (b) address decoders which are arranged in correspondence with said memory arrays; (c) first storage means to form first signals for comparing addresses; and (d) second storage means capable of forming data line position indicating signals which indicate data lines of said memory arrays to be replaced.

10. A semiconductor memory constructed and arranged to operate substantially as herein described with reference to and as illustrated in the accompanying drawings.