DE3537015A1 - SEMICONDUCTOR STORAGE - Google Patents

Abstract

In a multi-bit semiconductor memory having a redundant memory YR-ARY, any faulty data line CD is replaced with a redundant data line. To decrease the number of redundant data lines required when a plurality of data lines are selected at once, the semiconductor memory is furnished therein with first storage means (MMo Fig. 3) for forming signals necessary for an address comparing operation in an address comparing circuit (ACo-ACn) and also second storage means (DM1...DM3...) for forming signals indicative of data line positions to be remedied. When a faulty address has been detected as the result of the address comparing operation, the second storage means is referred to, and the data line indicated by the second storage means is replaced with the redundant data line. This arrangement can decrease the number of the redundant data lines when compared with an arrangement wherein all the data lines to be simultaneously selected are replaced with redundant data lines. <IMAGE>

Description

Description ^

The invention relates to a semiconductor memory device and, more particularly, to one effective to a dynamic RAM (random access memory / memory with random access) technology to be used in the memory information in units is written / read by multiple bits.

For semiconductor memory devices, the application became of a fault bit protection system in order to increase the yield of the products. To take over the fault bit protection system is the semiconductor memory device having, for example, a χ 1 bit arrangement (which stores the data writes and reads in units of individual bits), with a suitable memory device for storing error addresses in a memory array and provided with additional circuitry such as an address comparator circuit and a redundancy circuit (spare memory arrangement).

In a semiconductor memory device that writes and reads in units of plural bits such as in a χ 8 bit arrangement as considered here a single address is assigned to eight pairs of data lines having an identical address signal and having eight pairs are connected by respective corresponding common data lines. Even if in this case among the eight Pairs of data lines to be connected only one data line pair is defective, all eight data line pairs are replaced by a replacement memory arrangement. For this The replacement memory arrangement must therefore be equipped with eight pairs of redundancy data lines. It must be in others Words redundancy data lines are arranged, the number of which exceeds that of the actually faulty data lines

goes out. (For a semiconductor memory device having redundancy bits, see Japanese Patent Application Laid-Open No. 53-41946 referenced.)

The object of the invention is to be seen in a semiconductor memory device indicate with which the disadvantages inherent in the state of the art are at least partially overcome and in particular an increase in the actual error saving rate through a small number of replacement memory arrangements enables.

These and other objects as well as novel features of the invention will become apparent from the following description as well as the accompanying one Drawings clearly.

The operation of the invention is briefly outlined below by way of example: In a semiconductor memory device with a multi-bit structure, error bit address signals are generated, which indicate the faulty data lines of a set of data lines to be protected. According to a Error addresses are selected from the large number of data lines that are not designated by the error bit address signal while a redundancy data line was selected instead of the data line identified by the error bit address signal will.

A preferred embodiment of the invention is described below with reference to the accompanying drawings described. Show in the drawings

Fig. 1 is a block diagram showing the internal structure of an embodiment the invention;

Fig. 2 is a circuit diagram of a possible embodiment of a Column switch;

3 shows a circuit diagram of an address comparator, a redundancy decoder, an error bit address signal generator and a control device for a selection clock signal; and
FIG. 4 is a timing diagram of the circuits in FIG. 3.

1 shows a block diagram of a dynamic RAM according to an embodiment of the invention. Without Restriction to this, access in the dynamic RAM shown is in 8-bit units. The RAM is after the well-known Technologies for the production of integrated semiconductor circuits on a semiconductor substrate, for example from monocrystalline Silicon.

According to this exemplary embodiment, the memory arrangement is shown in FIG split two arrangements M-ARY1 and M-ARY2, which are provided on the left and right side. The structure of the individual memory arrangements can be better understood from FIG. 2, to which reference is made later. In each of the Memory arrangements M-ARY1 and M-ARY2 are eight pairs of complementary data lines combined into a set and formed so as to be in the horizontal direction in the drawing. The memory arrangement in this embodiment in other words, is not built up in eight separate blocks (or matrices). Without any particular restriction then a single column address is assigned to a pair of complementary data lines that are among the eight Pairs of complementary data lines in the same memory array are adjacent to each other. The respective complementary In the figure, data lines are arranged one behind the other in the lateral direction. This allows the storage arrangement and their peripheral circuits can be simplified.

According to this embodiment, the line system address

- Q -

Selection lines (word lines) for both memory arrangements M-ARY1 and M-ARY2 are formed jointly and in the figure arranged one behind the other in the vertical direction.

The complementary data line pairs are activated by a column switch C-SW1 or C-SW2, optionally with eight pairs connected by common complementary data lines CDL or CDR. In the figure, the pairs of the common run complementary data lines in the lateral direction. The common complementary data line pairs CDL and CDR are connected to the input terminals of main amplifiers MA1 and MA2, respectively.

By means of a clock signal 0pa, sense amplifiers SA1 and SA2 are brought into their operating states, those of selected memory cells Read voltages supplied to the complementary data line pairs of the memory arrangements are low Received level and these read voltages to a certain Boost high level / low level.

A precharge clock signal 0pc, which is generated before the selection of the memory cells begins, precharge circuits PC1 and PC2 put into operation, which are the paired complementary ones Bring data lines to a precharge level or reference level substantially equal to Vcc / 2 (where Vcc denotes a power source voltage).

A row address buffer R-ADB receives over external connections Line system address signals RAD with (m + 1) bits and forms internal complementary address signals arO - arm and arO arm, which are to be fed to a line address decoder R-DCR. In the following description and drawings, a pair of internal complementary address signals, for example arO and arO, as an internal complementary address

- I U ""

Signal designated and shown as arO . Accordingly, the internal complementary address signals arO - arm / arO - arm are represented as internal complementary address signals arO - arm .

The row address decoder R-DCR selects a word line from each of the two memory arrangements M-ARY1 and M-ARY2 in accordance with the address signals arQ - arm and in synchronism with a word line selection clock signal 0x.

A column address buffer C-ADB receives column system address signals CAD with (n + 1) bits via external connections, forms internal complementary address signals acO - acn and acO acn and outputs these to column address decoders C-DCR1 and C-DCR2. Corresponding to the description above, the internal complementary address signals acO - acn and acO - acn are also referred to in the drawings and the following description as internal complementary address signals acO - acn .

Each column address decoder C-DCR forms selection signals in order to select the eight pairs of complementary data lines, ie a set of complementary data line pairs, in accordance with the address signals ac0- acn and in synchronism with a data line selection clock signal 0y.

After receiving the selection signals, the column switch C-SW1 or C-SW2 connects the eight pairs of complementary data lines of the memory arrangement M-ARY1 or M-ARY2 with the eight pairs of common complementary ones corresponding to these Data lines. In the drawing, each of the complementary data line pairs or the common complementary data line pairs is shown as an example by a single line.

The operation of the main amplifiers MA-1 and MA2 is controlled by the Clock signals 0 times and 0 mar controlled. They amplify the data signals the common complementary data lines CDL or CDR.

The input / output circuit not shown in detail I / O is made up of a data output buffer for read operation. The I / O circuit amplifies the output one of the main amplifiers MA1 or MA2, which is in the operating state and supplies the amplified signal to external connections DA.

On the other hand, the circuit performs I / O in the write operation their write-output pairs of the common complementary Data lines CDL or CDR too. The signal paths for writing are not shown in the figure.

An internal control signal generator TG receives two external control signals CS (chip selection signal) and WE (write enable signal) and a transition detection signal 0 for the address signals, which is formed by an address signal transition detector ATD, which, for example, the address Receives signals arO - arm and acO - acn and forms and delivers the various clock signals required for memory operation.

In this embodiment, the memory arrays are M-ARY1 and M-ARY2 each with redundancy memory arrangements YR-ARY1 and YR-ARY2 provided. Although each of the storage arrangements M-ARY1 and. M-ARY2 is constructed from the eight pairs of complementary data lines, each of the redundancy memory arrangements YR-ARY1 and YR-ARY2, as described later, have only one pair of complementary data lines. Corresponding the arrangement of the redundancy memory arrangements YR-ARY1 and YR-ARY2 are the column switches C-SW1 and C-SW2 provided with circuits (multiplexers) that share the pair of redundant data lines with a selected pair of the eight connect complementary data line pairs. The practical structure of the memory arrangement, the redundancy memory arrangement and the switching blocks is

with reference to Fig. 2 will be described in detail later.

The RAM shown is also provided with an address comparator circuit AC, which has an address memory device for storing error address signals and error bit addresses as well as a column address comparator to compare the error address signals and the address buffer C- ADB supplied address signals acQ - acn to compare and to detect whether the stored error addresses have been entered. If an error address is specified, this address comparator circuit AC refers to the error bit address in the error address in order to prevent the selection of faulty data lines in the selected address and the connection of the YR-ARY1 (or YR-ARY2 ) lying redundant data lines with the common complementary data lines according to the error bit. The practical construction of the address comparator circuit AC will be described in detail with reference to FIG. In the address comparator circuit AC, the address storage device for the error addresses and the address memory device for the error bit addresses are programmed with signals which are applied to connections PO to Pn + 3.

Although the provision of similar redundancy memory arrangements for the data lines is advantageous, it is not included in any direct connection with the present invention, which is why such redundancy memory arrangements in the figure are not shown.

The operation of the illustrated RAM will now be outlined.

Access to the RAM begins when the chip select signal CS changes from a high non-select level to a low one Selection level is changed.

After starting the chip selection, the clock generator is the first TG the clock signal 0pc outputted with a predetermined pulse width for the precharge circuits PC1 and PC2. This will make the brought complementary data lines in the respective memory arrangements to the precharge level, which is essentially is equal to Vcc / 2.

After finishing the output of the clock signal 0pc, in others Words upon completion of the operation of the precharge circuits PC1 and PC2, the word line selection clock signal 0x is generated. With this, from the multitude of word lines of each memory arrangement M-ARY1 and M-ARY2, those are selected, which are specified by the row address signal RAD. That is, the more detailed by the row address signal RAD designated memory cells are selected. The selected memory cells supply read signals to the corresponding complementary ones Data line pairs of the respective memory arrangements.

After generating the clock signal 0x, the clock generator TG generates the clock signal 0pa. The sense amplifiers SA1 and SA2 operated.

After the formation of the clock signal 0pa, the clock signal becomes 0y generated. The selection signal for the selection of the data line from the column decoder is corresponding to the generation of the clock signal 0y C-DCR1 or C-DCR2 supplied.

In this case, the eight complementary data line pairs, which build up a set (hereinafter referred to as "standard data line group" one of the column addresses each set in one-to-one correspondence. if the Unit data line group comprises a defective pair of complementary data lines, for example due to a defective memory cell, a defective conductor track that leads to an interruption or a short circuit, or

the defect in the sense amplifier or the column switch is unsuitable for reading or writing data, this unit data line group is regarded as a defective data line group. The one of such flawed A column address corresponding to a data line group is referred to as an error address.

According to this embodiment, bit address information words become set in one-to-one correspondence for the respective pairs of complementary data lines that represent the faulty Establish data line group. As stated above, the bit address information words are stored in the address storage device held in the address comparator circuit AC.

According to this embodiment, the column switch C-SW1 or C-SW2 is controlled when by the external address signal the error address was specified, whereby the selection of the faulty complementary data line pair is prevented and instead the selection of the complementary data line pair in the redundancy memory arrangement YR-ARY1 or YR-ARY2 takes place.

The clock signal 0mal or 0mar becomes synchronous with the clock signal 0y or in other words synchronous with the operation of the column switch C-SW1 or C-SW2 generated. The clock signal 0mal or 0mar operates the main amplifier MA1 or MA2, which is the corresponding memory arrangement M-ARY1 or M-ARY2, so that it is connected to the common complementary data lines CDL or CDR applied data signal is amplified.

The data signal amplified by the main amplifier MA1 or MA2 is connected through the input / output circuit I / O to the data ports DO - D7 delivered.

When the write enable signal WE indicates the write level, i.e. the low level, the data signal is applied to the data

connections DO - D7 through the input / output circuit I / O, the main amplifier MA1 or MA2 and the column switch C-SW1 or C-SW2 in the memory cells of the memory array M-ARY1 or M-ARY2.

Access to the RAM also begins in response to that in the chip selection state (CS: low level) the state of at least one of the address signals RAD and CAD is changed will.

If the transition of the address signals RAD and / or CAD from Address-signal transition detector ATD has been detected, the detection pulse 0 is output from the detector ATD and the clock generator TG operated.

In response to the detection pulse 0, the generation of the Clock signals 0pa, 0x, 0y, 0mal and 0mar are set, whereupon the clock signal 0pc is generated for a certain time. That is, the circuits of the sense amplifiers SA1, SA2, the Column switches C-SW1, C-SW2, etc. are in their non-operational states and set all word lines to the non-selection level, whereupon the precharge circuits PC1 and PC2 can be brought into the operating state for the predetermined period of time in order to access the corresponding pairs of complementary Data lines to generate the precharge level.

Then, the word line selection clock signal 0y and the clock signal 0pa are generated to thereby select the word lines of the memory arrangements M-ARY1 and M-ARY2 or to operate the sense amplifiers SA1 and SA2.

Thereafter, similar to the description above, the different clock signals are generated, whereby the corresponding circuit operations be effected.

2 is a circuit diagram of one embodiment of the column switch along with parts of the memory array M-ARY and the redundancy memory arrangement YR-ARY shown. The MOSFETs shown in this figure are n-channel enhancement MOSFETs.

The memory arrangement M-ARY comprises complementary data line pairs DO, Ö ~ Ö to D7, D7, word lines WO and W1 and Memory cells MC1 to MC8. Each of the memory cells is made up of an address selection MOSFET Qm and an information storage capacitor Cm built. A current-carrying electrode of the address selection MOSFET Qm is used as the data input / output terminal of the memory cell and is connected to the corresponding data line, while the gate electrode of the MOSFET serves as the selection terminal of the memory cell and is connected to the corresponding word line is.

The illustrated complementary data line pairs DO, DO to D7, D7 ~ build a unit data line group, the has a column address.

The redundancy memory arrangement YR-ARY has complementary Data line pairs DY and DY and a plurality of memory cells RM1 and RM2 and has the same structure as the Memory arrangement M-ARY.

In the arrangement of FIG. 2, the column switch C-SW is made up of MOSFETs Q1 to Q8 and Q9 to Q12. The column switch C-SW also includes a multiplexer MPX with MOSFETs Q13 to Q20.

The complementary data lines DO, DO-D7, dT of the memory arrangement M-ARY are each connected via the MOSFETs QI, Q2 - Q7, Q8 that make up the column switch with common grain

Plementary data lines CDO, CDO - CD7, CD7 connected. the Gates of the MOSFETs Q1, Q2-Q7, Q8 are each formed in common. They are transferred via the transfer gate MOSFETs Q9 - Q1-2, which are shared by the output signal of the column address decoder C-DCR can be controlled with the data line selection clock signals 0yO - 0y7 supplied. These data line selection clock signals 0yÖ - 0y7 are generated based on the data line selection clock signal 0y formed.

The replacement memory array YR-ARY comprises a pair of complementary ones Data lines DY and DY. This pair of complementary data lines DY and DY is made up of the switching MOSFETs Q13, Q14 - Q19, Q20 built multiplexer MPX optionally connected to the common complementary data lines CDO, CDO - CD7, CD7. The gate connections of this Switching MOSFETs Q13, Q14 - Q19, Q20 are activated with the data line selection clock signals 0yO '- 0y7' applied to the formed by the address comparator circuit AC in accordance with the error bit addresses at the time the error address is displayed became.

The data line selection clock signals 0yO and 0yO 'are clock signals for coupling the respective data line pairs of the memory arrangement M-ARY and the redundancy memory arrangement YR-ARY to the first pair of common complementary data lines CDO and CDO. The signals 0yO and 0yO 'become corresponding to the bit address information of the address comparator circuit AC brought complementary to the high level at the time of data line selection.

Similarly, the clock signals 0y1, 0y1 'to 0y7, 0y7' become complementary brought to each other at the time of the selection of the data line to the high level.

In particular, in a case where the complementary Data lines DO, DO - D7, D7 the complementary data lines D2, D2 are defective, the eight pairs of complementary data lines DO, DO-D7, D7 assigned Address and the bit address information of the complementary data lines D2, D2 of the third bit are written in advance in the memory device of the address comparator circuit AC. If the column address containing the faulty data lines D.2, D2 is accessed, the address comparator detects this access. In accordance with the resultant output, the address comparator circuit AC takes the error bit address information Obtains and prohibits the output of the data line selection clock signal 0y2. So only the MOSFETs Q5, Q6 of the column switch are held in their OFF states so that the selection of the faulty data lines D2, D2 is prevented. On the other hand, the address comparing circuit generates AC with reference to the error bit address information the data line selection clock signal 0y2 'for the replacement memory arrangement in synchronism with the data line clock signal 0y. The switching MOSFETs Q17, Q18 brought into the ON state, so that instead of the faulty complementary data lines D2, D ~ 2, the complementary replacement data lines D, D with the common complementary

Data lines CD2, CD2 are connected. Fig. 3 shows a circuit diagram of the address comparator circuit AC.

The address comparator circuit AC has the following components: address comparators ACO to ACn, an address decoder ACd, storage devices DM1 to DM3 for bit address information, decoders DDO to DD7 and clock signal control units TCO to TC7.

Each of the address comparators ACO to ACn has a memory device MMO and address comparator MOSFETs Q27, Q28, whose switching state is controlled by the memory device will.

Without being particularly limited to this, the memory device MMO comprises a fusible element FUZ which, for example, is a programming element made of polycrystalline silicon, and MOSFETs Q24 to Q26, which are used to create a Signal at a suitable level even if the fuse element FUZ is not advantageously disconnected, and for generation of a signal at a complementary level. The MOSFET Q25 forms one together with the MOSFET Q26 Type of inverter and is dynamically controlled by a clock signal 0c1, to reduce the power consumption of the circuit.

In a case in which the fusible element FUZ is not disconnected, the drain terminal of the is in the address comparator ACO MOSFET Q24 held at the high level, which is substantially equal to the power source voltage Vcc, during the des MOSFET Q26 is held low, which is essentially Is 0 volts. With this, the MOSFETs Q27 and Q28 are kept in the OFF and ON states, respectively. As a result of this will the output arO of the address comparator ACO equals the address signal ä "Ö ~.

In a case where the fuse element FUZ is disconnected, the conduction states of the MOSFETs Q27 and Q28 are reversed, and the output ar0 accordingly becomes equal to the address signal a0.

Similarly, the address comparator ACn selects one of the address signals and on depending on whether the fusible element is disconnected in this comparator or not.

The fusible element FUZ is separated, for example, by an electrical melting process.

In detail, connections pO - pn, for example

are connection points arranged on a semiconductor chip, with the fuse elements FUZ in the respective circuits ACO- ACn connected.

If during a test, for example a semiconductor wafer test, a faulty column address is detected, voltages with levels that correspond to the respective address signals correspond to this lateral point, applied to the connections pO - pn by a conductive element such as a tungsten needle. As a result, error address information words in the circuits ACO - ACn are inscribed. For example, according to the low level of the address signal aO a When a voltage of essentially 0 volts is applied to the terminal pO, the element FUZ is melted. On the other hand is located in correspondence with the high level of the address signal aO, the terminal pO on a substantially the power source voltage At a level corresponding to Vcc, the fusible element FUZ is not disconnected.

Due to the fact that such writing or programming of the error address information words in the circuits ACO - ACn takes place, all outputs arO am of the corresponding circuits ACO - ACn set to the low level when the address signals aO - to the error column address indicate, and at least one of the outputs arO arn is set to the high level when none of the address signals aO - to indicate the error address.

The decoder ACd has MOSFETs Q29 to Q31 which have a dynamic Form a NOR circuit. The output 0rd of the decoder ACd is set high in response to that the error column address is specified.

According to this embodiment, the bit address information written into the three storage devices DM1-DM3.

As can be seen from FIG. 3, each of the storage devices DM1-DM3 has the same structure as the storage device MMO. One of eight kinds of bit address information is stored in the three storage devices DM1 to DM3.

The DDO DD7 decoders, each made up of MOSFETs Q32 to Q34 decode the outputs dm1 - dm3 of the storage devices DM1 - DM3,

The output 0d10 of the decoder DDO is held at the high level when the bit address information of the memory devices DM1-DM3 indicates the first bit address, and it is held at the low level when the bit address information is any other bit address indicates. Similarly, the output 06.11 of the decoder DD7 is held high when the bit address information indicates the eighth bit address.

As shown in the figure, each of the clock signal control units TCO-TC7 is composed of MOSFETs Q35-Q43. These control units are represented by the output of the decoder 0RD ACD expenditure 0DLO - 6.11 operated the corresponding decoder DDO DD7, the clock signals 0c1 and 0C3, as well as the data line selecting timing signal 0y.

The MOSFETs Q37 to Q41 are provided for the switching state of transfer gate MOSFETs Q35 and Q36 complementary to control, the MOSFETs Q42 and Q43 are provided to control one of the two clock signals to be supplied by each control unit forcibly to the low level.

4 shows a diagram of the operational sequence over time of the address comparator circuit AC in Fig. 3. The operations of the circuits in FIG. 3 will now be described with reference to the flow chart of FIG.

When the chip selection signal CS, which is shown in Fig. 4 under Ά is brought to the low level, the clock signal output from the clock generator TG in FIG. 1 is 0c1, which is shown in Fig. 4 under C is set to the high level for a certain period of time.

Unfavorable output levels dm1, arO etc. caused by undesired Leakage currents occur under the OFF states of the MOSFETs Q22, Q25, etc., due to the fact that the clock signal 0d is brought to the high level, reset to favorable levels.

As shown under D in FIG. 4, the clock signal 0c2 generated by the clock generator TG becomes with a certain Delay relative to the clock signal 0d set to the high level for the predetermined period of time.

The address decoder ACd is precharged by the clock signal 0c2. If the column address signals aO - to the error address specify, the output 0rd of the address decoder ACd becomes synchronous to the clock signal 0c2 is set to the high level, as shown by the solid line under F in FIG. Give the Address signals aO - an on the other hand not the error address, the output 0rd is held at the low level, as shown in Fig. 4 under F with the dashed line.

As shown in Fig. 4 under E, this takes from the clock generator TG delivered clock signal 0c3 then to the high level when the chip selection signal CS "brought to the low level becomes, and it takes the low level after the clock signal 0c1 is brought to the low level. The clock signal 0c3 must at least be brought high before clock signal 0y is brought high, and it can also be set to the high level after the clock signal 0c1 becomes the low level.

The decoders DDO - DD7 are preloaded by the clock signal 0c3, that has taken the high level.

If the outputs of the memory devices DM1 - DM3 now indicate the first bit address, then all are connected in parallel in the decoder DDO MOSFETs Q33 to Q34 are held in the OFF states. In this case the output is 0dÄO of the decoder DDO held high as shown by the solid line under G in FIG. On the other hand, give the expenses of the memory devices DM1-DM3 have a different bit address, at least one of the MOSFETs Q33 to Q34 becomes in the ON state kept so that the output 0d £ O of the decoder DDO on is held the low level, as shown in Fig. 4 under G in phantom.

As shown at J in Fig. 4, the data line select clock signal 0y is brought to the high level at a point in time after the operation of the sense amplifiers SA1 and SA2 in FIG .

According to the different signals mentioned above, the clock signal control unit, e.g. TCO, works as follows:

First, the MOSFET Q37 becomes one by the clock signal 0c1 brought into the ON state at an early point in time at the start of the chip selection. As a result of the ON state of MOSFET Q37 a node n1 is precharged to the high level as shown at H in FIG. Since the high level of the Node n1 of the MOSFET Q41 is brought into the ON state, a node n2 takes the low Pe-. gel, as shown in FIG. 4 under I.

If, in accordance with E in FIG. 4, the clock signal 0c3 is high Brought to level, the MOSFET Q39 turns ON in response thereto.

If the output 0rd of the address decoder ACd is at the high level according to the display of the error address, as under F. Solidly shown in Fig. 4, the MOSFET Q40 is brought into the ON state. As a result, the MOS-FETs Q39 and Q40 a current path between the output of the decoder DDO and the node n2 formed. The potential of node n2 is therefore determined by the output of the decoder DDO determined.

According to the description above, the output is 0d £ O on brought high when the first bit address is set in memory devices DM1-DM3. In this case the node n2 assumes the high level in synchronism with the clock signal 0c3, as indicated by a solid line under I. shown in FIG. In this way, when node n2 has gone high, MOSFET Q38 becomes in response then turned ON so that node n1 is set to the low level as with a solid line Line shown under H in FIG.

During the period when all clock signals 0c1 and 0c3 and the signal 0rd are high, it becomes a latch circuit composed of MOSFETs Q37-Q41 set in a static operating state or a ratio operating state. About the level changes of the switching points To allow n1 and n2 in the static operating state, the MOSFETs are designed so that between Q37 and Q38 and between Q32, Q39 and Q40 and Q41 respectively suitable ratios are present. If high speed operation is not required for the RAM and the timing of the level change of the node n2 can accordingly be later, the clock signal 0c3 of the MOSFET Q39 can be at the high level after the MOSFET Q37 is turned OFF.

The output 0d10 of the decoder DDO becomes the low level held as shown by the broken line under G in Fig. 4 are independent of the ON and OFF states of the MOSFETs Q39 and Q40, the node n2 at the low level, as in Fig. 4 under I dashed shown, and the node n1 held at the high level, as shown in Fig. 4 under H with a dashed line.

Even in the case where the output 0d & O of the decoder DDO is held high, the MOSFET Q40 is turned OFF when the output is 0rd is held low level (see. Fig. 4, dashed line under F), so that the node n2 at the low Level remains.

That is, the node n2 of the circuit TCO is only set to the high level in synchronism with the clock signal 0c3, when the error column address and next to it the first bit address are displayed.

According to the high and low levels of the nodes n1 and n2, one of the MOSFETs Q35 and Q36 in the Brought ON state. The clock signal 0y is generated by whichever of the MOSFETs Q35 and Q36 is in the ON state, to one of the two output connections of the clock signal control unit TCO transferred.

The data line clock signal 0yO 'is thus synchronous with the Clock signal 0y brought to the high level when the error address and next to it by the memory devices DM1 DM3 the first bit address will be displayed. On this occasion the data line selection clock signal 0yO remains due to the OFF state of the MOSFET Q35 and the latch circuit from the MOSFETs Q42 and Q43 unchanged at the low level.

If after the first working cycle T1 the column address signal is changed as shown at B in Fig. 4, in response to this, the following operation is carried out (duty cycle T2).

At the start of duty cycle T2, the data line selection clock signal becomes 0y previously brought to the high level is set to the low level. That before on the clock signal 0yO or 0yO 'set high level is in response brought to the low level of the clock signal 0y to the low level since the MOSFETs Q35 or Q36 since then switched to the ON state.

After the clock signal 0y is changed to the low level, the clock signal 0c1 becomes as in the previous one to the set high level.

From then on the different ones are already described Generated clock signals and then operated the various circuits.

According to the present invention, the following effects can be achieved:

(1) In a semiconductor memory device having a multi-bit structure become an error address signal and error bit addresses stored in the individual address as error information, so only the data lines that actually are defective, are replaced by redundant data lines. This has the effect that a redundancy circuit is required can be simplified.

(2) Due to the above point (1) can be based on a constant Occupancy area a larger number of redundancy data lines can be formed. That has the effect that the

Number of defects healed can be increased.

In the foregoing, the invention was specifically described using an exemplary embodiment. However, it is not on This exemplary embodiment is limited, but can be modified in many ways without departing from the basic inventive concept to deviate. For example, writing or reading can be in units of any number of bits (for example 4 bits). In addition, the practical structure of each individual circuit block can be adapted to different levels requirements can be adapted. The address signals to be supplied from external connections can, for example, be row address signals and column address signals indicated by a so-called time division system can be fed from common external connections.

In addition, the invention is not restricted to the case described, in which it is applied to a dynamic RAM found. It is, for example, also on a static RAM or a programmable ROM (read only memory) under the Condition advantageously applicable that according to the above description Signals from several bits are written or read.

YES / bi

Claims (8)

FATCNTANWALTK "" STREHL SCHOBEL-HOPF SCHULZ 35 37015 WIDENMAYERSTRASSE 17, D-8000 MUNICH 22 HITACHI, - LTD. DEA-27275 October 17, 1985 Semiconductor memory 1. semiconductor memory,
marked by a first data line (DY, DY) connected to a plurality of memory cells (RM1, RM2); a large number of second data lines (DO, DO - D7, D7), each with a large number of memory cells (MC1 MC8) are connected; a large number of common data lines (CDO, CDO CD7, CD7); a first switching circuit (MPX) between the first data line (DY, DY ") and the multitude of common Data lines (CDO, CDO - CD7, CD7) is inserted and the transfer of data of the first data line is any the common data line allowed; .- * A ψ 4 a second switching circuit (C-SW) / between the Large number of second data lines (DO, D ~ Ö - D7, D7) and the Large number of common data lines (CDO, CDO - CD7, CD7) is inserted; and a control circuit (TC) that controls the first and second switching Circuit (MPX, C-SW) controls so that when the data of the first data line (DY, DY) on one of the common Data lines (CDO, CDO - CD7, CD7) are to be transmitted, the connection between this common data line and the second data lines (DO, DO - D7, D7) is prevented. 2. Semiconductor memory according to claim 1, characterized in that that the first switching circuit (MPX) has a plurality of first field effect transistors with an insulated gate electrode (Q13 - Q20), which between the first data line (DY, DY) and the respective common data lines (CDO, CDO - CD7, CD7) are inserted and their respective ones Switching state is controlled by first clock signals (0yO * - 0y7 ') supplied by the control circuit (Tc), and that the second switching circuit (C-SW) a plurality of second field effect transistors with an insulated gate electrode (Q1 - Q8), each between the second data lines (DO, DÖ - D7, DT) and the corresponding common Data lines (CDO, CDO - CD7, CD7) are inserted and their respective switching status by the control circuit (TC) supplied second clock signals (0yO - 0y7) is controlled. 3. Semiconductor memory according to claim 1 or 2, characterized in that that one with the first data line (DY, DY) connected memory cell (RM1 / RM2) and one with each of the second data lines (DO, DO - D7, D7) connected memory cells (MC1 - MC4 / MC5 - MC8) via their respective selection connections are connected to a word line (W0 / W1) so that they are simultaneously selected by this word line. 4. Semiconductor memory according to one of claims 1 to 3, characterized in that the switching state of the second switching circuit (C-SW) is controlled so that the plurality of second data lines (DO, oil) - D7, Dl) simultaneously with the plurality of the common data lines (CDO, CDO - CD7, CD7). 5. Semiconductor memory according to claim 4, characterized, that the second clock signals (0yO - 0y7) from a plurality of clock signals in one-to-one correspondence to the large number of common data lines (CDO, CDO - CD7, CD7) exist and the respective second field effect transistors (Q1 - Q8) by third field effect transistors with isolated Gate electrode (Q9 - Q12) are supplied, their respective switching status by a single selection signal is controlled, and that the first clock signals (0yO '- 0y7') from a plurality of clock signals in one-to-one correspondence to the large number of common data lines (CDO, CDO - CD7, CD7) exist. 6. Semiconductor memory according to claim 5, characterized by an address comparator circuit (AC) which receives an input address signal (PO - Pn) and an address signal (aO - an) supplied by a memory device compares, wherein the control circuit (TC) is constructed so that it has an output (0rd) of the address comparator circuit (AC) and an indication signal (0y) for the position of a data line receives / supplies one of the second clock signals (0yO - 0y7), which is indicated by this display signal, suppresses and at the same time one of the first clock signals (0yO * - 0y7 *) generated if by the address comparator circuit (AC) the comparison signal (0rd) was supplied. 7. Semiconductor memory according to one of claims 1 to 6, characterized in that the memory cells (RM1, RM2; MC1 - MC8) are dynamic Memory cells are. 8. semiconductor memory, marked by Memory arrangements (M-ARY1, M-ARY2), in each of which data from several bits can be accessed at the same time, To address decoder (R-DCR; C-DCR1, C-DCR2), in correspondence are arranged to the memory arrangements, a first memory device (C-ADB) which forms first signals for comparing addresses, and a second storage device (AC), the display signals (0y) can form the position of a data line, which indicate the data lines to be replaced in the memory arrangements.