JPS6251093A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain both functions of a static column mode and a page mode by providing a function for directly transmitting an address signal supplied to an address buffer and a latch function for holding the address signal synchronously with the edge of a control signal. CONSTITUTION:A column address buffer C-ADB realizes three types of continuous access modes. Therefore, it is operated by a timing signal ce formed based on a chip selecting signal CE and provided with a function for directly transmitting as it is the address signals AY0-AYn of a column system consisting of n+1 bits supplied from an external terminal, a latch function for holding the address signals AY0-AYn synchronously with the edge of an internal control signal cs and a multiplexer function for receiving an address signal formed by an address counter circuit ADC.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is effective when used in a dynamic RAM (Random Access Memory) whose peripheral circuit is composed of a static type circuit.

[Background technology]

As a continuous access operation in dynamic RAM, one word line is selected by the row selection circuit, and the column address signal is changed in synchronization with the column address strobe signal CAS to switch data lines one after another. In this way, the page mode that performs continuous read/write operations of the memory cells connected to the word line and the column system selection circuit are configured with static type circuits, and the column selection circuit is configured with a static type circuit while the word line is in the selected state. A so-called static column mode is known in which a continuous read/write operation of memory cells coupled to the word line is performed by changing the address signal and switching the data lines one after another.

The former page mode uses the column address strobe signal as a clock to capture the address signal supplied from the external terminal, so it allows continuous access at relatively high speed, but on the other hand, it is necessary to supply the clock signal from the external terminal. . The latter column static mode allows continuous access by simply changing the column address signal, but its operation speed is relatively slow due to the skew (difference in address signal change timing) of the address signal supplied from the external pin. In other words, the column selection operation is performed after waiting for the address signal that changes the slowest among the multi-bit address signals.In this way, both have their advantages and disadvantages, and the conventional dynamic The type RAM is configured to have any of the above functions.

In addition, the dynamic type R equipped with the above continuous access function
Regarding AM, for example, Nikkei McGraw-Hill published the magazine "Nikkei Electronics J No. 169" dated July 18, 1983.
Pages to 193 pages, ■Published by Hitachi, September 1983.
(See Hitachi IC Memory Data Book).

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic RAM that has multiple functions and operates at high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the address buffer has the function of directly transmitting the address signal supplied from the external terminal, and the latch function of holding the address signal supplied from the external terminal in synchronization with the edge of a predetermined control signal supplied from the external terminal. It uses this to realize both page mode and static column mode functions. Also, address buffer 1
A multiplexer function is provided to selectively accept address signals from external terminals and address signals generated internally, and these can be controlled by external control terminals to enable continuous access using the above internal address signals. It is intended to do so.

〔Example〕

FIG. 1 shows a dynamic RA according to an embodiment of the present invention.
A block diagram of M is shown. The dynamic RAM shown in the figure is a dynamic RAM that is accessed in units of 8 pins, although it is not particularly limited, and is formed on a semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In this embodiment, the memory array is arranged in two parts, M-ARYI and M-ARY2, although this is not particularly limited. Each memory array M-ARYI, M-
In ARY2, eight complementary data line pairs are formed as one set, and are formed to extend in the vertical direction in the figure.

In other words, instead of configuring the memory array by dividing it into 8 blocks (mats), one address is assigned to each 8-bit data line and 8 complementary data line pairs adjacent to each other in the same memory array. In the figure, they are arranged in order in the horizontal direction. By doing so, the memory array and its peripheral circuits can be simplified. The memory array M-ARY1. The memory cells arranged in matrix in M-ARY2 are 1MO consisting of a capacitor for memory axis storage and a MOSFET for address selection.
A type 3 dynamic memory cell is used. The gate of the MOSFET for address selection of this memory cell is
It is coupled to the word line and its drain (source) is coupled to the data line.

Row-related address selection lines (word lines) are connected to each of the memory arrays M-/RY1. They are formed in the horizontal direction to the left and right with respect to M-ARY 2, and are arranged in order in the vertical direction in the figure.

The above complementary data line pair includes column switches C-8Wl, C
-8 common complementary data line pairs CDI, C via 3W2
Selectively connected to D2. In the figure, the common complementary data line pair runs in the horizontal direction. These common complementary data line pair CDI.

CD2 is connected to the input terminals of main amplifiers MAI and MA2, respectively.

The sense amplifiers SAI and SA2 receive a minute read voltage on the complementary data line pair of the memory array, are activated by the timing signal φpa, and amplify the complementary data line pair to a high level/low level according to the read voltage. .

Row address buffer R-ADB receives chip selection signal C
It is put into an operating state by a timing signal Cθ formed based on E, receives row-related address signals AXO-AXm consisting of m+1 bits supplied from an external terminal, and outputs internal complementary address signals aO-am, D-O-Dm. to form the
Send to row address decoder R-DCR. In the following description and drawings, a pair of internal complementary address signals, for example aQ and TO, will be expressed as internal complementary address signal 0. Therefore, the internal complementary address signals aO-am and ao-wam are expressed as internal complementary address signals 10-1m. Row address decoder R-DCR selects one word line in synchronization with word line selection timing signal φX according to address signals 10 to am.

Column address buffer C-ADB is activated by a timing signal C6 generated based on a chip selection signal CE, and fi+l supplied from an external terminal, in order to realize three types of continuous access modes as described later.
Column-based address signals AYO to AYn consisting of bits
The function of directly transmitting the address signal A Y O-A Y in synchronization with the edge of the internal control signal
A latch function for holding n and a multiplexer function for receiving and receiving address signals formed by the address counter circuit ADC of 4iLffl are provided. In addition,
In accordance with the above method of representing internal complementary address signals, internal complementary address signals a0 to an, a
Qxan is an internal complementary address signal and is expressed as 0 to n.

Internal complementary address signals aO-an and aQ-an formed by column address buffer C-ADB are transmitted to column decoder C-DCH.

The operation of the column decoder C-DCR is controlled by the data line selection timing signal φy, and the column decoder C-DCR decodes the address signal transmitted to it and selects eight data lines in synchronization with the data line selection timing signal φy. conduct.

Column switches C-3WI and C-5W2 receive the data line selection signal and connect the eight pairs of complementary data lines to the corresponding eight pairs of common complementary data lines. In addition, in the figure, the complementary data line pair and the common complementary data line pair illustrated as an example are realized by one line.

The input/output circuit I10 includes a data output cover 7 for reading.
It consists of a buffer and a data input buffer for writing. The data output buffer is activated during reading, and one of the main amplifiers M that is activated is activated.
Amplify the output signal of AL or MA2 and connect it to external terminal Do-D.
? Send to.

Further, the data input buffer is activated during a write operation, and supplies write signals supplied from external terminals DO to D7 to the common complementary data line pair CDi or CD2. Note that this write-related signal path is omitted in the figure. The data output buffer and data input buffer described above have a tri-state output function, and when it is placed in an inactive state, its output is set to high impedance (
or floating).

The internal control signal generation circuit TG generates four external control signals CE.
(chip enable signal), WE (write enable signal), OE (output enable signal), C5 (clocked serial signal), and address signals that receive the above address signals aQ-am and aO~art, although not particularly limited. In response to the change detection signal φ of the address signal formed by the change detection circuit ATD, various timing signals necessary for memory operation according to the operation mode are formed and sent out. The RAM is operated in an internally synchronous manner by forming a series of timings for internal operations based on the detection signal φ generated by the address signal change detection circuit ATD as described above. As a result, even though a dynamic memory cell as described above is used, it can be accessed from the outside in the same way as a static RAM (configuring a so-called pseudo-static RAM). For this purpose, each peripheral circuit such as the address buffers R-ADB, C-ADB and address decoders R-DCR, C-DCRI, C-DCR2, etc. is configured by a CMOS (complementary MO3) static type circuit. Ru.

Although not particularly limited, the automatic refresh circuit REFC includes a fresh address counter, a timer, etc., and is activated by setting the refresh signal REF supplied from an external terminal to a low level. That is, in a non-selected (held) state where the internal chip enable signal is set to a high level, when the refresh signal REF is set to a low level, the automatic refresh circuit REFC controls the row address buffer R-AD by a control signal (not shown).
By switching the multiplexer installed at the input section of B,
A refresh operation (auto refresh) is performed by transmitting a fresh address signal generated by the built-in glue fresh address counter to the row decoder R-DCR, selecting one word line, and amplifying the sense amplifier SA.
I do.

When the refresh signal REF is kept at a low level, a timer is activated, and the refresh address counter is incremented at regular intervals, during which time a continuous refresh operation (self-refresh) is performed.

FIG. 2 shows a circuit diagram of an embodiment of the column address buffer C-ADH and address counter circuit ADC. In the same figure, the P channel part S F
ET is distinguished from N-channel MOSFET by the addition of a straight line to its channel portion.

The figure shows a unit circuit of an address buffer for one bit as a representative. The address signal supplied from the external terminal AYn is passed through a NAND gate circuit Gl controlled by the internal chip enable signal ce to the P-channel MO3FET Q2, which is one input terminal of the multiplexer circuit, and the N-channel section.
Supplied to the gate of S F ETQ3. Between the source of the P-channel MO3FET Q2 and the power supply voltage Vcc, there is a P-channel MO3F that receives an inverted control signal B.
ETQI is provided, and an N-channel MO3FETQ4 receiving a control signal cs is provided between the source of the N-channel MO3FETQ3 and the ground potential point of the circuit. Note that the address signal AY supplied from the external terminal
By adding switch MOSFETs QI and Q4 that receive the control signals cs and cs to the CMOS Nant gate circuit that receives n and the internal chip enable signal, both circuits may be configured as one circuit.

P-channel MOSFETQ6 and N-channel MO3FETQ are the other input terminals of the multiplexer circuit above.
7 is supplied with the corresponding output signal 71° of the address counter circuit ADC. These MO5FE
TQ6. Q7 also has a P-channel MO3FET similar to the above.
Q5 and N-channel M'03FETQB are respectively provided.

These MO3FE'l'Q5. The gate of Q8 is cross-connected with the gates of the MO3FETs QI and Q4, so that the control signals cs and cs are supplied in a crossed manner.

The output terminals of the above two circuits are commonly connected, and a CMOS inverter circuit I is used as an input circuit that constitutes a latch circuit.
Connected to the input terminal of VI. This f inverter circuit I
VI is a clocked inverter circuit, and is activated by a clock signal φcs. The output signal of the inverter circuit IVI is transmitted to the input terminal of the CMOS inverter circuit IV2. The output signal of this inverter circuit IV2 is fed back to its input via the clocked inverter circuit [V3. This clocked inverter circuit I
V3 is activated by an inverted signal of the clock signal φcs. The above clocked inverter circuit IVI
-The latch circuit based on IV3 performs the operation of taking in the signal through the multiplexer circuit at the timing when the clocked serial signal C8 changes from low level to high level according to its operation mode, and the clocked inverter circuit ■Vl is in the operating state. By setting the clocked inverter circuit IV3 to a non-operating state, it operates as a static circuit that directly transmits the signal from the multiplexer circuit.

CMOS inverter circuit IV forming the above latch circuit
The output signal No. 3 is supplied to the input terminal of the CMOS inverter circuit IV4, and the inverted internal address signal ai is sent from the output terminal of this inverter circuit IV4. The output signal of this inverter circuit IV4 is supplied to the input terminal of a CMOS inverter circuit IV5, and a non-inverted internal address signal ai is sent from the output terminal of this inverter circuit IV5.

The address counter circuit ADC includes flip-flop circuits FF0 to FFn arranged in series, and an address buffer C-AD connected to the cent input of each flip-flop circuit FF0=FFn via Nant gate circuits GO to Gn.
B internal address signal aOwan is supplied respectively. These gate circuits GO to Gn, as described later,
The gate is opened by the l-shot pulse φcs' generated when the high-speed continuous operation mode is set by the internal address signal, and the address signal corresponding to the address signal supplied from the external terminal is used as an initial value for each flip-flop circuit FFO to F. Incorporated into F n. In addition, an internal signal c formed based on the clocked serial signal C-8 is input to the counting input of the first stage flip-flop circuit FFO.
The carry signal of the flip-flop circuit FFO, which performs its counting operation at the edge of s, for example, when it falls from a high level to a low level, is supplied to the counting input of the next stage FFI. This results in a binary counter operation.

Next, referring to the timing diagrams shown in FIGS. 3 to 5, three
Explain the types of continuous access modes.

FIG. 3 shows a timing diagram for explaining the read operation in the static column mode.

If the clocked serial signal C8 is at a high level at the timing when the chip enable signal CE changes from high level to low level, a continuous access mode is set by address signals AYO to AYn supplied from external terminals. In the static column mode, the clocked serial signal C5 is maintained at a high level.

By doing this, the control signal CS of the multiplexer circuit shown in FIG. 2 is fixed at high level and τ1 is fixed at low level. As a result, P channel MO3F
'ETQI and N channel MOS I' ETQ4 are maintained in the on state, so that the circuit on the external terminal side of the multiplexer circuit is activated.

Due to the low level of the chip enable signal CE, the internal signal ca is set to high level, and the address signals AYO-AYn supplied from the external terminals form a latch circuit through the corresponding Nant gate circuit G1 etc. and the multiplexer circuit. Clocked inverter circuit IV
It is transmitted to the input of I. At this time, clock signal φCa
is maintained at a high level, for example, so that the clocked inverter circuit IVI is activated and the feedback clocked inverter circuit IV3 is deactivated. As a result, the latch circuit operates as a buffer circuit that transmits the input signal as it is.

Therefore, a memory cell selection operation is performed by a row-related address signal AX and a column-related address signal AV supplied from an external terminal.For example, although not shown, during a read operation when the write enable signal WE is at a high level. , when the output enable signal OE is set to low level,
Storage information Dout of the selected memory cell is sent to an external terminal. In the above state, when the column system address signals p, Y (AYO-AYn) are changed, the address buffer C-ADB changes the internal address signal in response. As a result, column decoger C
-DCR1 or CDCR2 decodes it, and the column switch circuit is switched, and the signal on the complementary data line of the memory array A that has been switched each time is sent to the external terminal. The above is the read operation in static column mode. This static column mode allows continuous access by switching addresses at arbitrary timing. In addition, in the case of write operation,
Continuous write operations are performed by supplying the write signal Din to the external terminal in synchronization with the change in the address signal AY.

FIG. 4 shows a timing diagram for explaining a read operation in page mode.

''-As stated in the report, if the clocked serial signal cs is at a high level at the timing when the chip enable signal GE changes from high level to low level, the continuous access mode is set by address signals AYO to AYn supplied from external terminals.

The clocked serial signal C8 is maintained at a high level during the first cycle. This allows the first 8
A read operation for bits is performed. In page mode, in order to achieve high-speed access, column-related address switching is performed in synchronization with a clock signal. In this embodiment, the clocked serial signal C8 is used as the clock signal for the address switching.

That is, when the clocked serial signal cs is set to a low level, the input inverter circuit IVI of the launch circuit is rendered inactive, and the feedback inverter circuit v3 is rendered operational. As a result, the address signal AY supplied from the external terminal is invalidated, and the previously fetched address signal is temporarily held. Next, when the clocked serial signal C8 is changed from a low level to a high level, at this timing, the input inverter circuit IVI is temporarily put into an operating state and the feedback inverter circuit IV3 is put into a non-operating state. As a result, at the rising edge of the clocked serial signal C8 to a high level, the address signal AY (AYO to AYn) supplied from the external terminal is captured and held, and the output signal of this latch circuit causes the internal address signal to be is formed. By using such a method of taking in external address signals using timing signals, column switching can be performed immediately without considering the skew of address signals, so that high-speed continuous access (page mode) can be realized. Note that in the case of a write operation, the clocked serial signal cs
Continuous write operations are performed by supplying a write signal Din to an external terminal in synchronization with .

Figure 5 shows high-speed serial mode (extended nibble mode).
A timing diagram is shown to explain a read operation according to the invention.

If the clocked serial signal C3 is at a low level at the timing when the chip enable signal CE changes from a high level to a low level, a continuous access mode (high-speed serial mode) is set using an address signal generated by an internal circuit. In high-speed serial mode, in order to capture the address signal AY supplied from the external terminal,
1 of the multiplexer circuit shown in FIG. 2 temporarily at the timing when the chip enable signal OE is set to low level.
ilJa Shinqcs is set to high level and Otsu is set to low level. As a result, the address signals AY supplied from the external terminals are taken in, and these address signals AY are taken in as initial values into the address counter circuit ADC by the timing signal φcs' generated at that time.

Due to the low level of the clocked serial signal cs,
The control signal cs of the multiplexer circuit goes to low level, C
As a result of S being brought to a high level, the P-channel MOSFE
TQ5 and N-channel MO3FETQtl are turned on, and the multiplexer circuit is connected to the address counter circuit AD.
The circuit on the C side is activated. As a result, the internal address signal an'', etc. corresponding to the fetched address signal AY is transmitted to the launch circuit.Although not particularly limited, at the timing when the clocked serial signal C8 is set to high level, the column system When the clocked serial signal C3 rises to a high level, similarly to the page mode, the manual inverter circuit IVI of the latch circuit temporarily enters the operating state, and the feedback inverter circuit IV3 is rendered inactive.As a result, the address signal 5', etc. corresponding to the initial value address signal is taken in and held, and an internal address signal is formed by the output signal of this launch circuit. The column decoder circuit C-DCR1 or C-DCR2 decodes this address signal to form a data line selection signal, so that the column decoder circuit C-DCR1 or C-DCR2 decodes this address signal to form a data line selection signal, so that the column decoder circuit C-DCR1 or C-DCR2 decodes this address signal to form a data line selection signal, so that the column decoder circuit C-DCR1 or C-DCR2 decodes this address signal to form a data line selection signal. Of the memory cells, the address signal an°
The stored information from the memory cell coupled to the data line selected by the above is sent to an external terminal.

When the clocked serial signal C8 is changed to low level, the address counter circuit ADC performs a counting operation, and the incremented address signal is changed to low level by the low level of the clocked serial signal C8. Since 1 is set to high level, it is transmitted to the input of the latch circuit in the same manner as above. When the clocked serial signal C8 is changed from low level to high level,
At this timing, the latch circuit takes in and holds the incremented address signal, so the internal address signal of the column system is changed. In response to this, a column switching operation is performed and a continuous read operation is performed. In this high-speed serial mode, unlike the static column mode in which address signals are supplied from external terminals as described above, there is no need to consider the skew of the address signal.
Correspondingly, high-speed access operations can be performed. Note that during a write operation, the write signal Din may be supplied to the external terminal in synchronization with the clocked serial signal.

〔effect〕

(11 Address buffer has a function to transmit the address signal supplied from the external terminal as it is, and a latch function to hold the address signal supplied from the external terminal in synchronization with the edge of a predetermined control signal supplied from the external terminal. By providing this, it is possible to obtain a semiconductor memory device having both functions of a continuous access mode by asynchronous address switching such as a static column mode and a continuous access mode such as a page mode.

(2) By adding a multiplexer function to the address buffer, it is possible to selectively accept address signals from external terminals and address signals generated internally, and by controlling these with external control terminals, The effect is that it is possible to provide a function that allows continuous access to memory cells at high speed without considering the skew of address signals.

(3) According to (1) and/or (2) above, 2 to 3
The advantage is that the most appropriate continuous access mode can be selected from among the various types of continuous access modes depending on the system or its operating form at the time.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the clocked serial signal C8 is a control signal instructing the operation mode,
It may also consist of a clock signal. Further, the specific circuits of the multiplexer circuit, the Sochi circuit, and the address counter circuit provided in the address buffer can take various embodiments.

Further, the external address signal may be supplied in time series from a common external terminal by a row address rope signal RAS and a column address strobe signal CAS. In this case, column address strobe signal CA
The clock signal supplied to the launch circuit provided in the address buffer may be formed based on S, and a control signal for distinguishing between the high-speed serial operation mode and the page mode may be added.

[Application field]

In addition to a dynamic RAM in which at least a column selection circuit is constructed of a static type circuit,
It can be similarly used for static type RAM and the like.

[Brief explanation of drawings]

FIG. 1 is an internal configuration block diagram showing an embodiment of a dynamic RAM according to the present invention, FIG. 2 is a circuit diagram showing an address buffer thereof and an embodiment of the address buffer, and FIG. 3 is an operation thereof. Fig. 4 is a timing diagram for explaining static column mode, which is one of the operations, and Fig. 5 is a timing diagram for explaining page mode, which is another one of its operations. FIG. 2 is a timing diagram for explaining a high-speed serial mode, which is one of the modes. M-ARYI, M-ARY2...Memory array, SAI
, SA2...Sense amplifier, R-ADH...Row address buffer, C-3WI, C-5W2...Column switch, C-ADB...Column address buffer, R-DC
R...Row address decoder, C-DCRl, C-DC
R2・-;h RAM address decoder, MAl, MA2・
・Main amplifier, TG・・Internal control signal generation circuit, AT
D: address signal change detection circuit, Ilo: input/output circuit, ADC: address counter circuit, REFC: automatic refresh circuit

Claims (1)

[Claims] 1. A latch that has the function of directly transmitting an address signal supplied from an external terminal and holds the address signal supplied from the external terminal in synchronization with the edge of a predetermined control signal supplied from the external terminal. A semiconductor memory device characterized by including a functional address buffer. 2. The semiconductor memory device according to claim 1, wherein the address buffer is a column-based address signal. 3. The operation mode of the address buffer is instructed by a combination of predetermined control signals supplied from external terminals, the address signal supplied from the external terminals is taken as an initial value, and the address buffer performs step operation according to the predetermined control signals. Claim 1 or 2, characterized in that the device has a multiplexer function of selectively transmitting an address signal formed by an address counter circuit performing the above-mentioned address signal and an address signal supplied from the external terminal. semiconductor storage device.