JPS6357819B2 - - Google Patents
Info
- Publication number
- JPS6357819B2 JPS6357819B2 JP55183472A JP18347280A JPS6357819B2 JP S6357819 B2 JPS6357819 B2 JP S6357819B2 JP 55183472 A JP55183472 A JP 55183472A JP 18347280 A JP18347280 A JP 18347280A JP S6357819 B2 JPS6357819 B2 JP S6357819B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- data
- bit
- address
- memory area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 claims description 21
- 238000010586 diagram Methods 0.000 description 3
- 238000003745 diagnosis Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Hardware Redundancy (AREA)
Description
【発明の詳細な説明】
本発明は電子計算等に使用される記憶装置、特
に主として読出し専用として使用され、かつ高信
頼度が要求される制御記憶装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device used for electronic calculations and the like, and particularly to a control storage device that is mainly used for read-only purposes and requires high reliability.
従来よりメモリの２重化は行なわれているが、
例えば第１図に示す如く、２組のメモリに同一の
データを格納しておき、一方を使用中にエラーを
生じると他方に切替えて使用するのが一般的であ
つた。即ち第１図は１語がデータ３ビツトＲ０〜
Ｒ２とパリテイビツトＰとの４ビツト構成で、各
ビツトが１つのメモリ単位（LSIチツプ又は複数
チツプからなるプリント板）Ｍ０〜Ｍ３として構
成され、アドレスADRSが各メモリ単位Ｍ０〜Ｍ
３に共通に与えられているものとする。そして各
メモリ単位中の記憶領域は２分され、アドレスの
特定の１ビツトによつてその一方が選択されるも
のとする。図では簡単のため２分された各領域に
は１ビツトのデータのみ示してある。 Although memory duplication has traditionally been carried out,
For example, as shown in FIG. 1, it has been common practice to store the same data in two sets of memories, and if an error occurs while using one, the memory is switched to the other. That is, in FIG. 1, one word consists of three data bits R0~
It has a 4-bit configuration of R2 and parity bit P, and each bit is configured as one memory unit (LSI chip or printed board consisting of multiple chips) M0 to M3, and the address ADRS is assigned to each memory unit M0 to M3.
It is assumed that this is commonly given to 3. It is assumed that the storage area in each memory unit is divided into two parts, and one of them is selected by one specific bit of the address. In the figure, only 1 bit of data is shown in each area divided into two for simplicity.
通常は上記特定アドレスビツトを例えば“０”
にしてプライマリ側の領域を使用し、パリテイエ
ラー等を発見すると上記特定アドレスビツトを
“１”に変更してオルタネート領域を使用する。 Normally, the above specific address bits are set to “0”, for example.
If a parity error or the like is found, the specific address bit is changed to "1" and the alternate area is used.
しかしながらこのような従来例では、各メモリ
単位のデータの入出力系に故障を生じた場合、論
理値が“１”又は“０”に固定して出力される現
象を生じ、オルタネート側に切替えてもエラーは
救済されない。 However, in such conventional examples, if a failure occurs in the data input/output system of each memory unit, a phenomenon occurs in which the logical value is fixed to "1" or "0" and output, and the output is switched to the alternate side. However, the error cannot be corrected.
本発明はこのような問題を解決することを目的
としており以下第２図によつて説明する。 The present invention aims to solve such problems and will be explained below with reference to FIG. 2.
第２図は本発明一実施例を示すブロツク図であ
り、第１図と比べると、各メモリ単位Ｍ０〜Ｍ３
の出力にEORゲートＥ０〜Ｅ３が接続され、そ
れらの一方の入力が共通に結ばれてアドレス
ADRSの特定の１ビツトにつながつている。この
特定ビツトとは上記の如くのプライマリ／オルタ
ネートの切替え用のアドレスビツトである。そし
て書込まれるデータは、オルタネート側ではプラ
イマリ側と反対の極性とされている。即ちプライ
マリ側のあるアドレスの内容が“0100”であれ
ば、それに対応するオルタネート側のアドレスの
内容は“1011”とされている。このようにするこ
とによつて、例えば上記特定アドレスビツトを
“０”としてプライマリ側を使用中において、メ
モリ単位Ｍ２のデータ出力系が論理“１”に固定
する障害を生じたとする。すると読出しデータは
“0110”となり寄数パリテイエラーが検出され、
上記特定ビツトを“０”から“１”にしてオルタ
ネート側に切替える。各メモリ単位からの読出し
データは“1011”となる。Ｍ２の出力系は“１”
に固定となつているが、もともとの記憶データが
“１”であるので問題はなくなる。そして上記特
定アドレスビツトを“１”したことによりEOR
ゲートは反転器として働き、最終出データは
“0100”となり、正しく読出すことが可能となる。 FIG. 2 is a block diagram showing one embodiment of the present invention, and when compared with FIG. 1, each memory unit M0 to M3 is
EOR gates E0 to E3 are connected to the output of
It is connected to a specific bit of ADRS. This specific bit is an address bit for primary/alternate switching as described above. The data to be written has a polarity opposite to that on the primary side on the alternate side. That is, if the content of a certain address on the primary side is "0100", the content of the corresponding address on the alternate side is "1011". By doing so, suppose that, for example, when the specific address bit is set to "0" and the primary side is in use, a failure occurs in which the data output system of the memory unit M2 is fixed to logic "1". Then, the read data becomes “0110” and a parity parity error is detected.
The specific bit is changed from "0" to "1" to switch to the alternate side. The read data from each memory unit becomes "1011". The output system of M2 is “1”
However, since the original stored data is "1", there is no problem. Then, by setting the above specific address bit to “1”, EOR is activated.
The gate functions as an inverter, and the final output data becomes "0100", allowing correct reading.
尚、EORゲートにおいて論理値固定障害を生
じると、エラーの救済はできないが、高集積度の
メモリ素子側での障害発生率に比べてEORゲー
トの障害発生率は非常に小さく、全体としての信
頼性は充分高くすることができる。また上記特定
アドレスビツトを切替えてもエラーが救済されな
いことによつて、EORゲートの障害か又はアド
レス系の障害であることが予測されるので、保
守・診断時の障害部分の切り分けも容易となる。 Note that if a logic value fixed failure occurs in the EOR gate, the error cannot be repaired, but the failure rate of the EOR gate is very small compared to the failure rate of highly integrated memory elements, and the overall reliability is high. can be made sufficiently high. In addition, if the error is not relieved even if the specific address bits are switched, it is predicted that there is a failure in the EOR gate or in the address system, making it easier to isolate the failure part during maintenance and diagnosis. .
第１図は２重化メモリの一従来例、第２図は本
発明の一実施例を示すブロツク図である。
図中Ｍ０〜Ｍ３はメモリ単位、ADRSはアドレ
スバス、Ｅ０〜Ｅ３はEOR（排他的論理和）ゲー
トである。
FIG. 1 is a block diagram showing a conventional example of a duplex memory, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, M0 to M3 are memory units, ADRS is an address bus, and E0 to E3 are EOR (exclusive OR) gates.
Claims (1)
用する２重化メモリにおいて、第１のメモリ領域
にはそのままのデータを格納し、第２のメモリ領
域には前記と同一データの各ビツトを反転したデ
ータを格納する手段と、一方のメモリ領域を使用
中に読出しデータのパリテイエラーを検出したと
きアドレスを他方のメモリ領域に切替える手段
と、読出しデータと上記２つのメモリ領域を識別
するアドレスのビツトデータを入力とするEOR
ゲートを設けたことを特徴とする２重化メモリ。1 In a duplex memory in which a set of memory is divided into two according to addresses, the first memory area stores the data as is, and the second memory area stores each bit of the same data. means for storing inverted data; means for switching the address to the other memory area when a parity error in read data is detected while using one memory area; and identifying the read data and the two memory areas. EOR using address bit data as input
A duplex memory characterized by having a gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55183472A JPS57105900A (en) | 1980-12-24 | 1980-12-24 | Duplicated memory control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55183472A JPS57105900A (en) | 1980-12-24 | 1980-12-24 | Duplicated memory control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57105900A JPS57105900A (en) | 1982-07-01 |
| JPS6357819B2 true JPS6357819B2 (en) | 1988-11-14 |
Family
ID=16136386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55183472A Granted JPS57105900A (en) | 1980-12-24 | 1980-12-24 | Duplicated memory control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57105900A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0375316U (en) * | 1989-11-27 | 1991-07-29 | ||
| JPH03505363A (en) * | 1988-05-25 | 1991-11-21 | スベンソン、ローゲル | Device in expandable attachment means |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05216771A (en) * | 1991-09-18 | 1993-08-27 | Internatl Business Mach Corp <Ibm> | Method and apparatus for ensuring recovery possibility of important data in data processing apparatus |
| JP5910356B2 (en) | 2012-06-29 | 2016-04-27 | 富士通株式会社 | Electronic device, electronic device control method, and electronic device control program |
-
1980
- 1980-12-24 JP JP55183472A patent/JPS57105900A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03505363A (en) * | 1988-05-25 | 1991-11-21 | スベンソン、ローゲル | Device in expandable attachment means |
| JPH0375316U (en) * | 1989-11-27 | 1991-07-29 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57105900A (en) | 1982-07-01 |
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