JPS62226500A - Memory access system - Google Patents

Abstract

PURPOSE:To use an address to a fault area and to access a normal nonused address area by inputting the address through an address signal changing means to a memory. CONSTITUTION:Addresses A0-A2 are changed through exclusive OR gates 1-3, etc., of an address signal converting means in accordance with control signals C0-C2, etc., the address to the fault area of a memory cell 5 is used, the nonused normal area of the cell 5 can be accessed and the reading/writing action of the normal data can be continued.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an access method for an address area (data write area) of a memory cell.

(Prior Art) Conventionally, the relationship between a plurality of address areas constituting a memory cell and a memory address that accesses each of these areas is fixed. Therefore, even if part of the address area of a memory cell fails and there is a normal unused address area, the address for the failed address area is used to create a normal unused address area. could not be accessed.

(Problems to be Solved by the Invention) When a failure occurs in part of the address area of a memory cell as described above, even if this memory cell has an unused normal address area, this memory cell cannot be used. Since normal data reading operations are no longer possible, a device using this memory cell cannot continue to operate, which is a disadvantage.

SUMMARY OF THE INVENTION The present invention aims to eliminate the above-mentioned drawbacks by providing a memory access method that can replace a failed address area with a normal unused address area and easily disrupt normal data read/write operations. purpose.

[Structure of the Invention] (Means for Solving the Problems) The memory access method of the present invention provides a method for accessing the memory cell through address signal changing means that can change an address signal for accessing a memory cell to any other address signal. A configuration is adopted in which the address signal is input to the cell.

(Function) In the memory access method of the present invention, when a specific address area of a memory cell fails, the address signal for accessing this address area is changed to an unused normal address area of the memory cell by the address signal changing means. Since the address signal can be changed to correspond to the address signal, the failed address area can be replaced with an unused normal address area, and data read/write operations to the memory cell can be continued.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing one embodiment of the present invention. 1,
2. '3 is an exclusive OR (EXOR) gate which receives address signals AO, AI, A2 and control signals Co, respectively.
The exclusive OR of CI and C2 is taken and the result is output to the address decoder 4.

4 is an address decoder that decodes the input address signal and outputs it to the memory cell 5; 5 is a memory cell having an 8-word 7' address area in which addresses 0 to 7 are assigned V]; It is assumed that memory addresses OOO to 111 correspond to words at addresses 0 to 7 of memory cell 5, respectively.

Next, the operation of this embodiment will be explained. First, it is assumed that a 5-word address area at addresses 0 to 4 of memory cell 5 is used, and the remaining 3-word address area at addresses 5 to 7 is unused. When all of the above five words of the memory cell 5 are normal, the control signals Co to C2 input to the exclusive OR gate 1 are controlled so that they all become ◯. Therefore, the memory address signals AO, AI, A2 pass through the exclusive OR gates 1, 2.3 as they are and are input to the address decoder 4. Therefore, memory address signals AO, A
I, A2 and each address area of memory cell 5 have a corresponding relationship as shown in Table 1.

That is, the memory address signal OOO specifies the address area at address 0, the memory address signal 001 specifies the address area at address 1, and so on.

Table 1 Here, it is assumed that the address area at address 2 corresponding to memory address O'IO of memory cell 5 has failed.

If this continues, a faulty address area will exist in the memory cell 5, making it impossible to continue reading and writing data using this memory cell.

Therefore, the control signals @CO, CI, which were all O until now,
, C2 are each set to 1.01. As a result, the outputs of the exclusive OR gates 1 and 2.3 are as shown in Table 2 in response to the inputs of the memory address signals AO, AI, and A2.

Table 2 below shows that the memory address signal OOO passes through the exclusive OR gates 1 and 2.3 to obtain the memory address fj@
It is changed to 101. Therefore, even if 0.0,0 is input as the memory address signal, the memory address signal 101 is input to the address decoder 4, and the corresponding address area of the memory cell 5 becomes address 5. In the same manner, the memory address signal 001 is changed to the memory address signal 100 by the exclusive OR gate 1.2.3, and the address area of the memory cell 5 corresponding to this is changed to the memory address signal 100.
becomes. In the end, the address areas of the memory cell 5 that can be accessed by memory addresses ○○O to 100 are 1, 4, .
5, 6, and 7, and it is possible to read and store data into the memory cell 5 without using the address area of the failed address 2. Therefore, there will be no problem even if the data read/write operation with respect to the memory cell 5 is continued as it is.

According to this embodiment, by changing the control signals GO, C1, and C2 of the exclusive OR gates 1, 2, and 3, memory address signals AO, , A, i, and A2 can be changed without changing By replacing the faulty address area of cell 5 with an unused normal address area, access to memory cell 5 can be continued normally. Therefore, the operation of the device using the memory cell 5 will not be stopped due to a failure in a part of the address area of the memory cell 5, improving the reliability and operation of the device. I can do it.

FIG. 2 is a block diagram showing another embodiment of the present invention. In this example, the present invention is applied to access to a control storage (CS) 6. Generally, a control storage device that stores a microprogram rarely uses the entire address area. Therefore, when starting up the system, the control record/hawk device 6 is diagnosed, and if a faulty area is included in the address area being used, a control signal is sent to replace the faulty area with an unused address area. GO, ClC
By setting 2 in register 7, this control store 6 can be used to continue normal operation of the system.

By the way, one way to increase the yield of memory is to configure memory cells redundantly in advance, and if a certain area has a failure, cut the circuit in that area with a laser beam, etc., and restore the failed area to a normal redundant configuration. A method of replacing by area has been realized. However, the above method requires cutting the circuit using a laser beam, etc.
The operation of replacing a faulty area with a normal area is frequent.

Here, instead of adopting a redundant configuration as described above as a method of increasing memory yield, if there is an area that is not used by the user within the entire address area, the above-mentioned present invention can be applied to transfer the memory address signal to the failure area. By fixing the control signal so as to access a normal address area 1 while avoiding the problem, and shipping the memory as a normal memory, this will essentially be the same as improving the yield of the memory. It can also be applied to improve memory yield.

[Effects of the Invention] As described above, according to the memory access method of the present invention, by inputting the memory address to the memory via the address signal changing means, the address area of the memory cell can be changed into a normal unused address area. This has the effect of allowing normal data read/write operations to be continued with respect to this memory cell.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the invention, and FIG. 2 is a block diagram showing another embodiment of the invention. 1.2.3...Exclusive OR gate 4...Address decoder 5...Memory cell agent Patent attorney Book 1) Takashi Figure 2

Claims (1)

[Claims] In a memory access method that reads and writes data to a plurality of address areas constituting a memory, the memory address signal that specifies the address area is changed to an address signal that specifies another address area. A memory access method characterized by input to memory.