JPH0728700A - Storage device - Google Patents

Abstract

PURPOSE:To obtain the storage device which maintain interchangeability with a conventional device while speeding up access by providing the storage device, which can connect an EEPROM to an HDD in an interchangeable manner with an interface which is newly connected to a direct bus. CONSTITUTION:A storage device 8 consisting of the EEPROM, a CPU 1, a RAM 2, and a ROM 3 are connected to a bus 4. This CPU 1 at the time of accessing the storage device 8 accesses it through the interface 9 for CPU which is directly connected to the bus 4. Access can be performed from an HDD(hard disk drive) interface 5 connected to the bus 4 being a conventional method through an HDD interface 6. Further, a control circuit 7 serves to control the access by arbitrating and switching signals such as an address and data for the EEPROM which are generated by both the HDD interface 5 and the interface 9 for CPU. Further, when data are written, a target block of the EEPROM is erased in advance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to shortening access time of a storage device.

[0002]

2. Description of the Related Art There is an EEPROM as a storage device used for small information devices and the like. When using an EEPROM as a storage device, (1) it is much more shock resistant than an HDD (hard disk drive) because it has no moving parts, (2)
Since it is a memory, read access is fast, (3) it is basically a ROM, so it can be made cheaper than SRAM, and (4) when writing, the entire memory or certain blocks must be erased once in advance. There are drawbacks such as (5) and (4), which requires a considerable amount of time for writing, and (6) the number of times of rewriting has a life.

Among the advantages, there is replacement of a conventional hard disk (HDD) as an application in terms of excellent impact resistance. When connecting to the system, by providing an interface compatible with the conventional HDD, this storage device can be handled without newly developing special control software. In addition, among the drawbacks, erasing in block units often causes no problem because the access unit can be matched with the block unit when used for HDD compatibility.
As for the number of times of rewriting, an alternative memory block is prepared in advance, and when a defective block occurs, the blocks are sequentially replaced, so that the life can be practically no problem even in a normal use environment.

A storage device composed of an EEPROM is
The configuration when connected to the system in DD compatibility is shown in FIG. In FIG. 1, 1 is a CPU, 2 is a RAM, and 3 is an RO.
M, 4 are buses, and 5 is an HDD interface. CP
U1, RAM2, ROM3 and HDD interface 5 are connected via a bus 4. Reference numeral 10 denotes a storage unit, in which an HDD interface 6 for connecting to the HDD interface 5, H
It includes 7 control circuits that enter between the DD interface and the 8 storage devices composed of the EEPROM and perform control. In this case, the CPU 1 uses the input / output instruction (I / O instruction) to access the storage device 8 via the bus 4 and the HDD interface 5. However, since the I / O instruction is not suitable for pipeline processing due to its nature, the performance is not improved even in a CPU which is generally said to have high performance. FIG. 2 shows an example of a read processing algorithm executed by the CPU 1 in the case of the configuration of FIG. Let us consider this algorithm by taking the case of a frequently used sector length of 512 bytes as an example. In FIG. 2, the SEEK command for moving the head to the target track and the track number are issued to the HDD interface 5 twice in the process 102, and at least 1 in the process 103 for determining whether the process 102 has been normally executed. Whether the data can be actually read twice in the process 104 for designating the READ command and the target sector number that triggers reading, and once in the process 105 for determining whether the process 104 has been normally executed. Since each time is repeated by the sector length in the determination of the processing 106 for confirming whether or not and the processing 107 for reading the data of 1 byte, the number of I / O accesses becomes the minimum (3 + 1027 * the number of sectors) times. Process 106
Even if the determination of (1) is not necessary, it occurs (3 + 515 * sector length) times. In this way, when used as HDD compatible, it is necessary to execute a large number of input / output instructions in a single data block transfer in proportion to the data transfer amount.
Therefore, the performance of the CPU cannot be fully utilized.

[0005]

In order to improve performance, it is important not to use I / O instructions having a slow execution speed as much as possible. In order to realize this, it is desirable that a storage device composed of an EEPROM be directly connected to the bus so that the CPU can directly access it. On top of that, it is necessary to maintain compatibility with the software developed with the conventional interface. However, when connecting to the system as a memory, since the memory space of the system is used for RAM, ROM, etc., it is a problem to arrange the storage device configured by the EEPROM in a space that does not overlap these.

An object of the present invention is to provide a new interface for directly connecting a bus to a storage device capable of connecting an EEPROM compatible with an HDD, thereby maintaining high speed access while maintaining compatibility with conventional devices. It is to provide a storage device.

[0007]

In order to achieve the above object, as shown in FIG. 3, there is provided a system in which a storage device 8 composed of an EEPROM, a CPU 1, a RAM 2 and a ROM 3 are connected to a bus 4. . CPU 1 is storage device 8
Access to the bus 4 via the CPU interface 9 directly connected to the bus 4. The HDD interface 5 connected to the bus 4, which is a conventional method, can also be accessed via the HDD interface 6. The control circuit 7 includes the HDD interface 5 and C.
EEPR generated by both of the PU interfaces 9
It has a role of controlling access by arbitrating and switching signals such as addresses and data to the OM. Further, at the time of writing, the target block of the EEPROM is also erased in advance.

FIG. 4 shows a memory arrangement in this system. The storage device is arranged in an empty area of the memory space so as not to overlap the RAM1, ROM2, etc. of the system. C
When the storage capacity of the storage device is smaller than the memory space that can be managed by the PU1, a linear mapping method in which the storage device is continuously arranged in the memory space is adopted, and sufficient memory space cannot be secured due to system convenience. Adopts a bank memory system in which the memory is divided into a plurality of memory blocks of a certain size and shares the same address.

In the configuration of FIG. 3, the read processing of a plurality of sectors will be compared with the case of the HDD compatible connection described above. FIG. 5 shows an example of the algorithm at this time. The application interface unit 200 converts the logical record number and the number of records into the offset and the number of transfer bytes in the storage device. After that, in the process 203, the CPU 1
Reads all at once by transferring memory blocks.
As a result, when all the storage devices 8 are linearly arranged in the memory space, the same result as in the case of the configuration of FIG. 1 can be obtained without using an I / O instruction having a slow execution speed even once. it can. Even if the bank method is adopted, the bank number is obtained from the logical record in the process 202,
Since only the process of switching the memory bank is required, at most one I / O instruction will suffice. As described above, many I / O commands can be omitted as compared with the HDD compatible connection.

The application interface unit 100 of FIG. 2 and the application interface unit 2 of FIG.
By making the interface of 00 to the application completely compatible, it is possible to operate the existing application software as it is.

[0011]

In the above system, in addition to the conventional method for accessing the storage device composed of the EEPROM through the HDD interface connected to the conventional HDD interface, the CPU interface connected to the bus is provided so that the CPU can directly access the HDD interface. You can do it both ways. Since it is almost unnecessary to use the I / O instruction in the access via the CPU interface, the processing time can be shortened as compared with the conventional one, and at the same time, the performance improvement of the CPU can contribute to the shortening of the processing time. The problem of compatibility due to the change in the system connection method is to maintain the compatibility of the specifications of the application interface section of the control software executed by the CPU without changing the application for conventional control software. It can be executed as it is.

[0012]

EXAMPLE FIG. 6 shows a first example of the present invention.
When this system starts up, the CPU 1 accesses it via the HDD interface 5, which is a conventional interface. At this time, the CPU interface 9 is still in an invalid state, and the CPU 1 cannot be used. Then CPU
In order to validate the communication interface 9, a specific parameter setting, for example, a track number that does not physically exist, a sector number, or a combination thereof is performed in a series of procedures. As a result, the control circuit 7 generates the CPU interface control signal 74, and the CPU interface 9 thereafter outputs C
PU1 can be used.

When the CPU 1 accesses the storage device 8, if the CPU interface 9 is used, the CPU
When the HDD interface 6 is used as the access signal 91, the I / O access signal 61 is generated and input to the control circuit 7. The control circuit 7 arbitrates these two access signals, generates an access switching signal 72, and inputs the access switching signal 72 to the access switching circuit 71 to switch the address signal and the data signal necessary for accessing the memory device 8.

The control circuit 7 controls the CPU access signal 91 and I
After arbitrating the / O access signal 61, the memory device 8 is controlled to read and write, and if writing, the target memory block is erased in advance to prepare for the subsequent writing process.

FIG. 7 shows a second embodiment using the present invention. In this example, in the first embodiment, the CPU interface control signal generation circuit 75 for enabling / disabling the CPU interface 9 is separated from the control circuit 7,
It is provided outside the storage unit 10. In this case, I /
This control signal can be generated by providing a register separately from the HDD interface 5 in an appropriate place in the O space and turning on / off a specific bit of this register by the CPU 1.

[0016]

According to the present invention, the storage device using the EEPROM, which has conventionally required many I / O instructions, can be accessed at most once. Since the method of accessing the storage device is very simple, the instruction execution steps of the CPU can be reduced. Therefore, the execution time can be significantly shortened as compared with the HDD compatible access. In addition, speeding up of access can be expected in proportion to improvement in CPU performance. The interface specifications of the application interface unit 200 of FIG.
Since the compatibility with 0 can be maintained, the applications developed in the past can be operated without any modification.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a system at the time of HDD compatible connection.

FIG. 2 is a diagram showing an algorithm for reading a plurality of records in the configuration of FIG.

FIG. 3 is a configuration diagram of a system that realizes the present invention.

FIG. 4 is a diagram showing a relationship between a memory arrangement and a storage unit viewed from the CPU side in the configuration of FIG.

5 is a diagram showing an algorithm for performing the same processing as in FIG. 1 in the configuration of FIG.

FIG. 6 is a diagram showing a first embodiment of the present invention.

FIG. 7 is a diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 1 ... CPU, 2 ... RAM, 3 ... ROM, 4 ... Bus, 5 ... Interface, 6 ... Interface, 7 ... Control circuit, 8 ... Storage device, 9 ... Interface, 10 ... Storage unit, 61 ... HDD access request signal, 71 ... Access switching circuit, 72 ... CPU access request signal, 73 ... Block erasing request signal, 74 ... Interface control signal, 75 ... Interface control circuit, 91 ... Access request signal, 100 ... Application interface section, 101 ... Effectiveness Determination process, 102 ... Head movement process, 103 ... Judgment process, 104 ... Sector designation process, 105 ... Judgment process, 106 ... Judgment process, 107 ... Data read process, 108 ... determination process, 109 ... determination process, 110 ... d Over processing, 200 ... application interface unit, 201 ... process of determining, 202 ... switching process, 203 ... treatment for memory block transfer, 204 ... error processing.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Kitahara 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi Microelectronics Device Development Laboratory

Claims (4)

[Claims] 1. A CPU, a primary storage device, and when writing data, it is necessary to temporarily erase the corresponding area.
A storage device that retains its contents even when the power is turned off is adopted as the secondary storage device,
A storage device, characterized in that the CPU of the information processing system is provided with means for directly accessing a memory system connected by a method compatible with the conventional one. 2. An information processing system according to claim 1, wherein the means for accessing the secondary storage device can use both the conventional method and the method directly performed by the CPU at the same time. 3. The information processing system according to claim 1, wherein the secondary storage device is assigned to a memory space of the CPU so that the CPU can directly access the storage device. 4. A storage device control system according to claim 1, wherein the secondary storage device is accessed by the same CPU command as the primary storage device.