JPH10289160A - Write data guarantee method for semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To check the data errors in a write mode without lowering the data access speed by applying a read operation to a memory storage element that is not actually performing a write operation by interleaving and comparing this written value with that written before the said value to confirm the propriety of data. SOLUTION: A memory write/read control part 1 writes in sequence the data into the semiconductor memory parts 3 to 6. Under such conditions, the semiconductor memory part where a write operation is not actually performed is set to read the data. For instance, if the data write operations are over to the memory parts 3 and 4 while a data write operation is performed to the memory part 5, a write data check part 7 reads the data written into the parts 3 and 4 through the data read buses 11 and 12. These read data are compared with the write data which are previously fetched from a write data check data bus 8, and the coincidence is confirmed between both data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an external storage device for a computer, and more particularly to a high-speed, large-capacity storage device using a semiconductor memory.

[0002]

2. Description of the Related Art In a conventional storage device using a semiconductor memory, an error such as a data error due to a soft error or a data write to a different address due to noise or the like temporarily occurring at an address occurs. was there. To confirm that the data was written correctly,
Read the same address as the one written again, that is,
The verify operation was performed, and the comparison was confirmed.

[0003]

When the above-described verify operation of the prior art is performed, there is a problem that the memory is accessed twice and it takes time to complete the write operation.

In the future, memory storage devices will definitely move in the direction of faster access, and it is important to solve the data error problem at the time of writing, such as a soft error, without causing a decrease in speed performance. Become. An object of the present invention is to provide a function of checking a data error at the time of writing without lowering the speed of data access.

[0005]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object of the storage device, the present invention provides multiple interleave accesses to a memory. Further, when a memory write operation is being performed, a read operation is performed on a memory storage element that is not actually performing a write operation by interleaving, and the validity of data is confirmed by comparing with a value written immediately before.

[0006]

FIG. 1 shows an embodiment of the present invention. A memory write / read control unit that constitutes a storage device;
It comprises a quadruple interleave control unit, four semiconductor memory units, a write data check unit, and a data bus connecting them.

The connection with the host device is made by a memory write / read control unit.

The memory write / read control unit 1 is connected to a quadruple interleave control unit 2 via a memory data bus 10.
Connected to. The quadruple interleave control unit 2 is connected to the four semiconductor memory units 3 to 6 via the interleaved memory data bus 11. The interleave control unit 2 writes the data sent from the memory write / read control unit 1 to the semiconductor memory units 3 to 6 in a time-division manner via the interleaved memory data bus 11.

A write data check section 7 takes in data at the time of writing from a write data check data bus 8 connected to the memory data bus 10 and also reads a data read data bus connected to the interleaved memory data bus 11. From 12, the data written in the semiconductor memory units 3 to 6 can be read. The state of each data bus, write or read, is sent to the write data check unit 7 through the write data check unit control signal 9. Information such as an error detected by the write data check unit 7 is also transmitted by the write data check unit control signal 9.
It is sent to the memory write / read control unit 1.

When the memory write / read control unit 1 writes data to the semiconductor memory units 3 to 6, the first data is written to the semiconductor memory unit 3. The next data is written to the semiconductor memory unit 4, the next data is written to the semiconductor memory unit 5, and the next data is written to the semiconductor memory unit 6. The next data is written to the semiconductor memory unit 3 again.
At this time, a setting is made so that data can be read from a semiconductor memory unit to which data is not actually written.

When data writing to the semiconductor memory units 3 and 4 has been completed and data writing to the semiconductor memory unit 5 is being performed, the write data check unit 7 reads the data written to the semiconductor memory unit 3. Is read from the data read data bus 12 and is compared with the write data previously taken in from the write data check data bus 8 to confirm that the data match.

Similarly, when data is being written to the semiconductor memory section 6, the write data check section 7
Reads the data written to the semiconductor memory unit 4 from the data read data bus 12 and compares it with the write data previously taken in from the write data check data bus 8 to confirm that the data match. .

As described above, the write data check unit 7
Is to read data one after another from the semiconductor memory unit where writing has been completed, compare it with the write data received from the write data check data bus 8, confirm that the data match, and if not, Are transmitted to the memory write / read control unit 1 through the write data check unit control signal 9 as an error.

[0014]

As described above, the memory write / read controller itself can perform only the write operation without being conscious of the check of the write data. Therefore, the memory write / read controller performs memory access without lowering the data transfer performance due to the verify operation. be able to.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention.

FIG. 2 shows a memory write / read timing in the embodiment of the present invention shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory write-read control part 2 Quadruple interleave control part 3 Semiconductor memory part 4 Semiconductor memory part 5 Semiconductor memory part 6 Semiconductor memory part 7 Write data check part 8 Write data check data bus 9 Control signal for write data check part 10 Memory data bus 11 Interleaved memory data bus 12 Data read data bus

Claims (2)

[Claims] 1. A method of reading data at a timing when a write access is not performed by utilizing an interleave access of a semiconductor memory. 2. The method according to claim 1, wherein data written to the semiconductor memory storage device is read, write data is compared, and write data is confirmed.