JPH10242949A - Data frequency conversion method and device for executing the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to accurately convert the frequency of data without being influenced by the dispersion of propagation delay time in hardware. SOLUTION: In the case of converting data DX synchronized with a certain reference clock into data DY synchronized with a different clock, the frequency of the data are accurately converted by using a gray code counter or the like capable of changing always only one bit out of bits constituting the counter in accordance with the count values of memory counters G, M without being influenced by the dispersion of propagation delay time in hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of converting data synchronized with a certain basic clock into data synchronized with a different clock, so that a bit constituting a counter is always stored in a memory counter in accordance with a change in a count value. By using a gray code counter or the like that changes by one bit, a variation in propagation delay time of hardware is eliminated, and a frequency conversion method for converting data to a clock synchronized with a different clock frequency without malfunction is implemented. Device.

[0002]

In order to convert data transmitted in synchronization with a certain basic clock to data synchronized with a different clock, a memory of several bytes for temporarily holding data is usually provided. A memory counter for controlling writing and reading of data to and from the memory is used, and data is written to the memory in order. Then, in the written order, the data is output in synchronization with the clock on the reading side, thereby performing the frequency conversion of the data.

[0003] A binary counter is used as the memory counter. However, in a binary counter, an erroneous comparison result may be output when comparing the values of the counters due to variations in the delay time of the gate. This erroneous comparison result may cause a malfunction at worst depending on the ratio of the write and read clocks. Conventionally, in order to avoid such a phenomenon such as a malfunction, various devices for adjusting the gate delay time have been implemented on hardware. However, when incorporating into IC etc.,
In particular, the larger the IC, the more difficult it is to manipulate the delay time.

[0004]

According to the present invention, when data synchronized with a certain basic clock is converted into data synchronized with a different clock, a bit constituting a counter in accordance with a change in the count value is stored in a memory counter. By using a gray code counter or the like that always changes by one bit, a method of accurately converting the frequency of data without being affected by variations in hardware propagation delay time, and a device that implements this method have been realized. Things.

The data frequency conversion method of the present invention and a device implementing the data conversion method comprise a memory counter for controlling writing and reading of data to and from a frequency conversion memory, and a counter for the memory counter in accordance with a change in the count value. By using a gray code counter or the like in which the bit always changes by one bit, an erroneous operation is essentially prevented from occurring even if the propagation delay time of the hardware varies.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view showing the configuration of a magnetic recording apparatus for writing and reading data to and from a tape for explaining the present invention. In FIG. 1, SCSI is a data input / output terminal of a magnetic recording device, DFC1, DFC2F.
C is a data frequency conversion circuit. MEMO is a memory, and TREC is a recording / reproducing system of a magnetic recording device.

In a magnetic recording apparatus as shown in FIG. 1, data sent from a device having an interface such as SCSI at a standard frequency such as SCSI is temporarily stored in a memory MEMO such as DRAM in the device. Stored in
This is recorded on a recording / reproducing system TREC such as a tape by a system clock peculiar to a magnetic recording apparatus.
Further, a portion for exchanging data with the outside, such as a SCSI controller, needs to operate at a standard frequency of the controller which is different from the system clock. For this reason, when the system clock frequency is different from the standard frequency of the controller due to the configuration of the device, it is necessary to convert the data frequency.

Also, when data is recorded from a memory to a tape or the like, frequency conversion in accordance with magnetic recording characteristics is required. Further, conversely, the same applies to the flow of data when data from the magnetic recording device is sent to another device via an interface such as SCSI. FIG. 2 is a diagram showing a specific configuration of a frequency conversion circuit to which the present invention is applied. In FIG. 2, DX is an input terminal for data X, CLX is an input terminal for a basic clock X of data, and DY is an output terminal for data subjected to frequency conversion.

CLY is an input terminal of a basic clock Y for conversion, and VLD is a flag (v) indicating whether data is valid or invalid.
output signal). G0 and G1 to G7 are gate circuits, and M0 and M1 to M7 are 1-bit memories, each of which uses D-Flip / Flop. DEC is a decoder circuit, a memory counter on the WRC writing side, and RDC is a memory counter on the reading side. SEL is a changeover switch, and CNP is a comparator. DF1 and DF2 are D-Flip /
Flop.

The input terminal DX for the data X is connected to the gate circuit G
0, G1 to G7. The input terminal CLX of the basic clock X is connected to the memories M0, M1 to M7,
Further, it is connected to a memory counter WRC on the writing side. The output terminals of the write-side memory counter WRC are connected to the gate circuits G0, G1 to G7 via the decoder circuit DEC.
, And to the comparator CNP via D-Flip / FlopDF1. Gate circuit G
0, G1 to G7 are output terminals of the memories M0, M1, respectively.
To M7. Output terminals of the memories M0 and M1 to M7 are connected to output terminals DY of data subjected to frequency conversion via the changeover switches SEL.

An input terminal of a conversion basic clock Y is connected to a memory counter RDC on the read side, and DF
Comparator CNP via lip / FlopDF1
And a flag (valid signal) output terminal VLD via a D-Flip / FlopDF2. The output terminal of the comparator CNP is connected to a memory counter RDC on the read side, and D-Flip / Fl
It is connected to a flag (valid signal) output terminal VLD via opDF2. The output terminal of the memory counter RDC on the read side is connected to the changeover switch SEL and the comparator CNP.

In a frequency conversion apparatus as shown in FIG. 2, data sent to a data X input terminal DX in synchronization with a basic clock XHz such as SCSI is converted to a basic clock YHz of a magnetic recording apparatus. The operation of converting the data into synchronized data and outputting the data to the data output terminal DY will be described with reference to the waveform diagram of FIG. For simplicity, the basic clock frequency YH of the read magnetic recording device
It is assumed that z is higher than the basic clock frequency XHz of writing, and data continuously comes from the writing side.

In FIG. 3, (a) shows a clock pulse (frequency, XHz) on the writing side, and (b) shows data on the writing side. (C) shows a clock pulse (frequency, YHz) on the reading side. (D) shows a flag (valid signal) indicating whether data is valid or invalid, and (e) shows data on the reading side. Flag indicating valid data, val
id is valid when valid = 1, the data is valid, and v
When "alide = 0", the data is invalid.

The data as shown in FIG. 3 (b) synchronized with the basic clock frequency X Hz as shown in FIG. 3 (a) is converted to a different clock frequency as shown in FIG. 3 (c). , YHz, is converted to data as shown in FIG. In this case, the hardware is
As shown in the figure, the 8-byte memories M0, M1 to M7 have
The gate circuits G0, G1 are sequentially turned on by the write-side clock pulse X applied to the input terminal CLX of the basic clock X.
Open G7 and write data in order. At this time, the write-side memory counter WRC advances by the number of written data.

The data written in the memories M0 and M1 to M7 are synchronized with the read-side clock frequency YHz as shown in FIG. 3C, which is applied to the input terminal CLY of the conversion basic clock Y. Switch SEL
Thus, the frequency conversion is performed by reading the data to the data output terminal DY in the written order. In this case, since the write clock frequency XHz is different from the read clock frequency YHz, the total amount of data that can be accessed in a unit time is different. Therefore, the flag (D) shown in FIG. vali
d signal) to the output terminal VL of the flag (valid signal).
By outputting to D, the validity of the output data is displayed.

The outline of the operation is as follows. When the writing of data progresses to a position just before an area from which data has not been read, the writing is stopped (the valid signal is lowered). In addition, the reading of data proceeds when data is written, and when the data is advanced to an area where no data is written, the reading is stopped there (valid signal is lowered). The frequency conversion of the data is performed by repeating these operations on both sides, and the writing and reading are advanced or stopped by the memory counter W on the writing side.
This is performed by comparing the value of RC with the value of the memory counter RDC on the reading side by the comparator CNP.

In the example of FIG. 3, although the data synchronized with the clock frequency X Hz is continuous as shown in FIG. 3B, the frequency of the clock frequency Y Hz is higher. As shown in (e), data (y) is intermittent. FIG. 4 is a diagram for explaining the operation of the memory used in the device of FIG. The memory capacity of FIG.
It is assumed that the number of bytes is 0 to 7 and that the data stored in the memory is sent in units of 1 byte.

Wr-pt is a position where data is written,
rd_pt indicates the value of the memory counter at the position from which data is read. The writing side sequentially writes data to the memory in synchronization with the basic clock X. In the above case, when data is sent up to 7 bytes, wr-pt indicating the current position on the writing side advances to 6. At this time, the reading side can read up to 6 data.

Therefore, the reading side reads data from the memory in synchronization with the basic clock Y,
When _pt reaches 6, the read operation must be stopped because the next data has not yet arrived. By repeating such operations, frequency conversion is performed. Here, the operation of stopping or proceeding with the reading operation is performed by comparing wr_pt which is the value of the memory counter WRC on the writing side with rd_pt which is the value of the memory counter RDC on the reading side by the comparator CNP. .

FIG. 5 is a waveform diagram for explaining the frequency conversion operation. 5A shows the write-side clock frequency XHz, FIG. 5B shows the write-side data, and FIG. 5C shows the value of the write counter. (D) The clock frequency on the reading side, YHz, is shown. (E) shows the value of the write counter latched at the rising edge of the clock frequency Y on the read side. (F) shows the value of the read counter. (G) indicates a flag (valid signal) indicating whether the data is valid or invalid, and (h) indicates data on the reading side.

At the rising edge of the clock frequency X on the write side as shown in FIG. 4A, data is taken into the memory as shown in FIG. 4B. At this time, the value wr_pt of the write counter is counted up as shown in FIG.

Write and read counter values, wr
The comparison between _pt and rd_pt is performed as follows. First, as shown in (d), (e), and (f) of FIG. 5, at the rising edge of the read-side clock pulse Y, the value wr_pt of the write counter that is compared with the value rd_pt of the read counter is latched. It is captured. Wr_ latched on the rising edge of lock Y
Let pt be wr_pt (y).

For example, wr_p in (e) and (f) of FIG.
t is the value of the write counter wr_pt (y) and the value of the read counter r, as in the case where wr_pt is 3 and 6.
When d_pt matches, the next data is invalid, so that the valid signal is lowered to stop reading as shown in (g) and (h) of FIG. This is because reading has caught up to the writing point and there is no new data to be read. However, the value wr of the write counter
If the change point of _pt coincides with the rising edge of the clock Y, the value of the write counter cannot be determined, which causes a problem that normal operation is not performed.

FIG. 6 shows the value wr_pt of the write counter.
FIG. 9 is a waveform chart for explaining an example of a case where the rising point of the clock Y coincides with the change point of the clock Y. FIGS. 6A and 6B show two values wr_pt of the write counter.
FIG. 3 shows an example in which each of the changing points 3, 5, 5, 6, 0, and 1 coincides with the rising edge of the clock Y. For this reason, as shown in FIG. 6C, the value wr_pt of the write counter at this time cannot be determined, and a normal conversion operation cannot be performed.

In order for the converter to operate normally, the part of the counter value that cannot be determined is, as shown in FIG. 6D, a change in the value wr_pt of the write counter, such as 2or3, 5or6, 0or1. Must be either before or after In this case, in FIG.
For example, the value of the counter is 2 or 3
This is because the rise of the clock Y is just at the change point of the value wr_pt of the write counter, so that it is not possible to know which one. .

When the value of the write counter wr_pt is
If the value is specified to be either before or after the change, the conversion operation is performed normally. FIG. 7 is a diagram for explaining the operation in the case where the value of wr_pt is specified to either the value before or after the change when the rising of the clock Y is exactly at the change point of the value wr_pt of the write counter. It is a waveform diagram. 7A to 7D show examples in which the value of the write counter value wr_pt is before the change.

In this case, as shown in FIG. 7A, the value of wr_pt (y) is 2, 5, 0. As a result, a normal conversion operation is performed as shown in (b) to (d) of FIG. In this case, the reading of the converted data is interrupted after the data c and f as shown in FIG. (E) to (h) of FIG. 7 show examples in which the value of the write counter value wr_pt has changed.

In this case, the value of wr_pt (y) is 3, 6, 1 as shown in FIG. As a result, a normal conversion operation is performed as shown in (f) to (h) of FIG. In this case, the reading of the converted data is interrupted after the data d and g as shown in FIG. As described above, even when the rising edge of the clock Y is at the changing point of the value wr_pt of the write counter, when the value of the value wr_pt of the write counter is specified as either the value before or after the change. , The conversion operation is performed normally, on the premise that the write counter and the read counter operate normally and their count values change continuously.

However, the value of the write counter wr_p
When t is a binary counter, the change of the value of the write counter from 5 to 6 changes by 2 bits,
The following problems occur. FIG. 8 is a waveform diagram illustrating the operation of the binary counter. A binary counter with a maximum count value of 8 is 3 bits (b0, b1, b2)
The count value and each bit (b0, b1,
The state of b2) is as shown in FIG. 8A, and the change of the value of the write counter from 5 to 6 changes simultaneously by 2 bits.

In this case, each bit (b0, b1, b
The waveforms in the state 2) are shown in FIGS. 8B and 8C. FIG. 8B shows an ideal case in which changes of each bit occur simultaneously. In this case, the count value is 5-6.
Therefore, there is no problem because it changes continuously.
However, in an actual circuit, the variation of each bit usually has a variation in the delay time. For this reason, the change of the value of the write counter by 5-6 causes
b0 and bl do not change strictly at the same time,
It is common for some differences to occur.

Assuming that the change of bl is slightly delayed from b0, the change point in this case is enlarged as shown in FIG. 8C. In this case, between the change of b0 and bl,
b0 = 0, bl = 0, b2 = 1, and the counted value is 4
Is displayed, and an erroneous operation of displaying a value different from the actual count value before and after that is performed. The conversion operation when the rising of the clock Y comes during the above-mentioned change of the binary counter, that is, during the period of the malfunction is described with reference to FIG.

As shown in FIGS. 9A and 9B, when the rising edge of the clock Y coincides with the change point 5-6 of the value wr_pt of the write counter, the value wr_pt of the write counter When the malfunction as shown in FIG. 8 occurs, the value of the write counter wr_pt (y)
Is as shown in FIG. 9C, and the count value changes to 4 different from the values before and after the count value. Therefore, the movement of the value wr_pt (y) of the write counter to be compared becomes discontinuous.

As described above, the value wr_p of the write counter
The conversion operation when the movement of t (y) is discontinuous will be described with reference to FIG. Write counter value wr_pt
If the movement of (y) becomes discontinuous, an erroneous operation in which data output is stopped at an unnecessary place occurs. That is,
The original movements must be as shown in FIGS. 10A to 10D, but when a malfunction occurs, they become as shown in FIGS. 10E to 10H. After the value wr_pt (y) of the write counter changes discontinuously from 5 to 4 as shown in FIG. 10E, the valid changes as shown in FIG. As shown in), a phenomenon occurs in which data output stops at unnecessary places.

There is also a disadvantage that the result of comparison between the values wr_pt and rd_pt of the write counter cannot be accurately monitored. In particular, the cause of a fatal malfunction is shown in FIG.
As shown in FIG. 1, the read clock pulse X is a jittered clock or the like, and the rising of the clock Y coincides with the clock pulse X. In this case,
As shown in FIGS. 11A to 11C, as shown in FIGS. 11A and 11B, the rising edge of the clock Y happens to coincide with the change point of the value wr_pt of the write counter. If this happens, the value wr_p of almost all the write counters as shown in FIG.
Since t (y) has an uncertain value, correct control cannot be performed.

According to the present invention, in order to prevent a malfunction of frequency conversion due to a variation in the propagation delay time of the hardware of the memory counter as described above, a gray code counter or the like is used for the counter indicating the position on the writing side and the reading side. The bits forming the counter are always 1 according to the change in the count value of
By using a counter that changes by bits,
A data frequency conversion method for eliminating a malfunction and a device implementing the method are realized.

FIG. 12 is a diagram for explaining a counter used in the present invention. FIG. 12A shows an example of a gray code counter. As shown in FIG. 12A, a gray code counter having a maximum count value of 8
As with the binary code counter, 3 bits (b0, b
1, b2), and the count value and each bit (b
The state of (0, b1, b2) is as shown in the figure.
The state of the change of the count value and each bit (b0, b1, b2) is 1 bit for any count value.
A feature of the Gray code counter is that only t changes.

For example, the value wr_pt of the write counter
FIG. 12B shows the waveform of the state of each bit (b0, b1, b2) when the count value changes from 5 to 1 in the case where the value of “1” is 1 to 1. The waveform of each bit is shown in FIG.
The count value can be either 11 or 101, but in any case, the values before and after the change point are latched, and the other values are not latched. Therefore, the above-mentioned problem does not occur fundamentally.

As described above, the major difference from the binary counter is that, at any count-up point, only 1 bit changes the state, and the bit changing state changes slightly earlier or later. When the value of the memory counter captured by the clock Y is the value before the change and when the value after the change is captured, the count value differs, but the value of the memory counter changes continuously. Therefore, as described with reference to FIG. 7, a normal conversion operation is performed in any case. The counter used does not need to be a gray code counter. The point is that it is good if only 1 bit changes at any count-up point.

For example, a counter called a Johnson counter can be used. The count value of the Johnson counter and the state of each bit (b0, b1, b2) are shown in FIG.
As shown in FIG. 2 (c), each bit changes only 1 bit at any count value, similarly to the gray code counter. For this reason, the Johnson counter can be used in the same manner as the Gray code counter.

In the embodiments described so far, an example has been described in which the data of the write measurement is continuous data and the data of the read measurement has a frequency faster than that of the write. The relationship between data frequencies is not limited to such a condition. Naturally, even when the data on the writing side is intermittent, or when the reading measurement speed is slower than the writing measurement, the same method as described above can be used to stop or advance the writing measurement. , Can be realized. In addition, the present invention can be applied to the case where both the writing measurement and the reading side need to be controlled intermittently.

[0041]

According to the present invention, when data synchronized with a certain basic clock is converted into data synchronized with a different clock, a memory counter for controlling writing and reading of data to a memory for frequency conversion is used. By using a gray code counter or the like in which a bit constituting the counter always changes by one bit according to a change in the count value, a malfunction does not essentially occur even due to a variation in hardware propagation delay time. Thus, the frequency of the data can be accurately converted.

For this reason, the present invention provides a data frequency conversion method and a data frequency conversion method in which a malfunction does not occur essentially due to a variation in hardware propagation delay time of a memory counter that controls writing and reading of data to and from a frequency conversion memory. Since it is possible to realize a device that implements this, unlike the conventional device, it is not necessary to increase the capacity of the memory for data transfer or to make the receiving side circuit have a margin to avoid failures. The circuit configuration can be simplified.

Conventionally, the probability of a malfunction of the comparison circuit of the counter has been suppressed in order to equalize the gate delay time of the memory counter. However, the present invention essentially eliminates unstable elements. This eliminates the necessity, so that the hardware configuration can be simplified even when the frequency conversion circuit is incorporated in an IC, and the signal of the comparison result of the counter can be accurately output.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a magnetic recording apparatus that writes and reads data on a tape for explaining the present invention.

FIG. 2 is a diagram showing a specific configuration of a frequency conversion circuit to which the present invention is applied.

FIG. 3 is a waveform diagram illustrating an operation when converting data transmitted in synchronization with a basic clock X Hz such as SCSI into data synchronized with a basic clock Y Hz of a magnetic recording apparatus.

FIG. 4 is a diagram for explaining an operation of a memory used in the device of FIG. 2;

FIG. 5 is a waveform chart for explaining an operation of frequency conversion.

FIG. 6 shows a change point of a value wr_pt of a write counter,
FIG. 9 is a waveform chart for explaining an example in a case where the rising edges of the clock Y coincide with each other.

FIG. 7 is a waveform chart for explaining an operation in a case where the rising edge of the clock Y is exactly at the changing point of the value wr_pt of the write counter.

FIG. 8 is a waveform chart illustrating the operation of a binary counter.

FIG. 9 is a diagram for explaining an operation when a clock Y rises during a change of a binary counter.

FIG. 10 is a diagram illustrating an operation when the value of a write counter becomes discontinuous.

FIG. 11 is a diagram illustrating a case where the rising of the clock Y coincides with the clock pulse when the read clock pulse has jitter.

FIG. 12 is a diagram illustrating a counter used in the present invention.

[Explanation of symbols]

SCSI: Data input / output terminal of magnetic recording device, D
FC1: Data frequency conversion circuit, DFC2: Data frequency conversion circuit, MEMO: Memory, TREC
... Recording / reproducing system of magnetic recording device, DX ... Data X
, CLX... Input terminal of data basic clock X, DY... Output terminal of frequency-converted data, CLY... Input terminal of conversion basic clock Y, VLD. · Flag (valid signal) output terminal, WRC ··· Write-side memory counter, DEC
... Decoder circuit, CNP ... Comparator, RD
C: memory counter on reading side, SEL: switch, DF1, DF2 ... D-Flip /
Flop, G0 to G7: Gate circuit, M0 to M7
..1 bit memory

Claims (6)

[Claims] When converting data synchronized with a certain basic clock into data synchronized with a different clock,
By using a counter in which the bit that constitutes the counter always changes by one bit in response to a change in the count value for the memory counter, the data frequency can be prevented from malfunctioning without being affected by variations in hardware propagation delay time. Conversion method. 2. When converting data synchronized with a certain basic clock to data synchronized with a different clock,
A data frequency conversion method in which a gray code counter is used as a memory counter to prevent malfunctions without being affected by variations in hardware propagation delay time. 3. When converting data synchronized with a certain basic clock into data synchronized with a different clock,
A data frequency conversion method in which a malfunction is prevented by using a Johnson counter as a memory counter without being affected by variations in hardware propagation delay time. 4. A memory from which data is read in synchronization with a certain basic clock, and means for converting data into a clock different from the basic clock by reading out data from the memory in synchronization with a clock different from the basic clock Control means for controlling writing and reading of data to and from a memory using a memory counter using a counter in which a bit constituting the counter always changes by one bit in response to a change in the count value; Without being affected by the variation in propagation delay time
Data frequency converter that prevents malfunction. 5. A memory from which data is read in synchronization with a certain basic clock, means for converting data into a clock different from the basic clock by reading data read out from the memory in synchronization with a clock different from the basic clock Control means for controlling the writing and reading of data to and from the memory using a gray code counter and a memory counter to prevent malfunctions without being affected by variations in hardware propagation delay time. Data frequency converter. 6. A memory from which data is read in synchronization with a certain basic clock, and means for converting data into a clock different from the basic clock by reading data read out from the memory in synchronization with a clock different from the basic clock Control means for controlling writing and reading of data to and from a memory using a memory counter using a Johnson counter, and preventing data from malfunctioning without being affected by variations in hardware propagation delay time. Frequency converter.