JPH09179693A - Disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent unauthorized data from being recorded in a disk storage part and to prevent the fault generation of a system by detecting the abnormality of write data based on time information from a timer means and/or judgement information from a data format judgement part. SOLUTION: An abnormality detection part 7B is provided with a function as the timer means and the function as the data format judgement part. Also, the abnormality detection part 7B is provided with the function for detecting the abnormality of the write data from an HDC 1 based on the time information from the timer means and the judgement information from the data format judgement part and the function for informing the HDC 1 of that effect in the case of detecting the abnormality of the write data. Further, the abnormality detection part 7B is provided with the function for sending out the write data for which an error is to be detected in the write abnormality detection part 3B of a data read/write IC 3 to the write abnormality detection part 3B in the case of detecting the abnormality of the write data.

Description

Detailed Description of the Invention

(Technical Field of the Invention) Technical Field of the Invention Conventional Technology (FIGS. 6 to 8) Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (FIGS. 1 to 5)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk device suitable for use as an external storage device in, for example, a computer or a communication terminal.

[0003]

2. Description of the Related Art Conventionally, for example, in a computer or a communication terminal, a disk device as an external storage device is mounted in order to secure a larger storage capacity. This disk device is configured by incorporating, for example, two or three 3.5-inch or 2.5-inch disk media, and is intended to downsize the device.

FIG. 6 is a block diagram showing a general disk device. The disk device 100 shown in FIG. 6 is connected to a small computer such as a personal computer, and programs and the like used in processing in these small computers are shown. It stores data. Further, the disk device 100 shown in FIG.
C (Hard Disk Controller) 101, RDC (ReaD Chan)
102), read / write IC (Read Write Integ)
It has a rated circuit 103, a head 105, a disk medium 104 and a spindle motor 104A.

The HDC 101 controls the entire disk device 100 in response to a command from a host device (not shown), and the RDC 102 interfaces read / write data between the HDC 101 and the read / write IC 103. is there. Specifically, the RDC 102 receives the write data from the HDC 1 as an 8-bit parallel signal via the data bus 106, converts the parallel signal into a serial signal, and outputs the serial signal to a read / write IC 103 described later. On the other hand, read data from the read / write IC 103 is converted from a serial signal into a parallel signal and output to the HDC 101 via the data bus 106.

Further, the read / write IC 103
Writes the write data from the RDC 102 on the disk 104 via the head 105, and
The data recorded on the disk 104 is read out via the head 105, and the HD is read out via the RDC 102.
It is designed to output to C101. The head 1
Reference numeral 05 designates a disk 10 by an actuator (not shown).
4 can be freely moved in the radial direction or the circumferential direction on the recording surface.

The disk medium 104 is the head 10
5, a magnetic disk or a magneto-optical disk for recording data in a format having magnetic or magneto-optical characteristics through 5, and is rotated by a spindle motor 104A. By the way, the above-mentioned HDC1
The write data input from 01 through the data bus 106 is, for example, as shown in FIG.
esponse most likelihood; based on the input sequence of the partial response / maximum likelihood decoding method, the preamble data (“00” pattern) 121 and the training data (“88”, “68” as the data for automatic equalization of the PR circuit equivalent filter). The header section 120 is composed of a "pattern" 122 and synchronous data ("AA" pattern) 123, user data 124, an ECC 125, and postamble data 126.

The above-mentioned synchronization data 123 can be arbitrarily set according to the device, and even in the PRML system,
If automatic equalization is not necessary, the sync byte can be sent after the preamble data. In addition, the above RD
The C 102 and the read / write IC 103 are functionally shown in FIG.
It has a configuration as shown in FIG. The RDC 102 shown in FIG. 7 uses PR as a read / write method.
It uses the ML8 / 9 conversion method.

Here, in FIG. 7, 111 is an RD
The RDC interface unit 111 is a C interface unit that performs a parity check on the write data input from the HDC 101 via the data bus 106 together with the write gate signal, while the header unit 1
A change in data in 20 is detected, and a timing for rewriting header information is generated based on the detected change in data in the header section 120.

Specifically, the RDC interface unit 111, when data shown in (b) of the time chart of FIG. 8 is input as write data, the training data 122 following the preamble data 121. It is supposed to check.
The parity signal from the RDC interface unit 111 is output via the parity detection line (P ERROR) 102A.

Reference numeral 112 is an 8/9 conversion unit, and this 8/9 conversion unit 112 outputs 8 bytes per byte for the user data 124 input via the data bus 106.
The parallel signal of bits is converted into a parallel signal of 9 bits per byte. Further, reference numeral 113 is a pattern generating unit (pattern generate), and the pattern generating unit 113 is based on the timing information generated by the RDC interface unit 111 and converts the header unit (code in (c) of FIG. 3). 120A) (see 120A).

Further, 114 is a multiplexer (Multiplexer), and this multiplexer 114 has the user data 124A converted by the 8/9 converter 112 and the pattern generator 1
The header section 120A generated in 13 is multiplexed. Further, 115 is a parallel / serial conversion circuit, and this parallel / serial conversion circuit 115 is
The parallel signal in which the header section 120A from the multiplexing section 114 and the user data 124A are multiplexed is converted into a serial signal.

Further, 116 is a pre-coder, and 11
7 is for reading data from the disk medium 104
A write precompression circuit that performs phase compensation before writing the data from the precoder 116 by the write nonlineality, 118 outputs the write data from the write precompression circuit 117 to the read / write IC 103 at a predetermined timing. It is a flip-flop (FF) for.

Further, the read / write IC 103
Focusing on the processing of write data, the write driver 103A includes a write driver 103A and a write abnormality detection unit 103B. Here, the write driver 103A writes the write data (serial signal) from the RDC 102 by driving the head 105 and the disk medium 104.

Further, the abnormality detecting section 103B is provided with the RDC1
02, when the head 105 is short-circuited with respect to GND or when a write error is detected, the WUS signal (Writ signal) is detected.
e UnSafe) 103C is notified.
With such a configuration, in the above-described disk device shown in FIGS. 6 and 7, in the state where the write gate WG of the RDC 102 is turned on (see time points (s1) to (s2) in (a) of FIG. 8). , From the HDC 101 to the RDC interface unit 111 of the RDC 102 via the data bus 106 [see (b) of FIG. 8] according to a series of sequences, the preamble data 121, the training data 122, and the synchronization data 12 that form the header unit 120.
3 is sequentially output, and then the user data 124 is transmitted.

The RDC interface section 111 detects a change in data in the header section 120 and generates a timing for rewriting header information based on the detected change in data in the header section 120. The pattern generation unit 113 generates a writing pattern (see reference numeral 120A in FIG. 8C) according to the data of each unit on the basis of the timing information generated by the RDC interface unit 111, and causes the MUX circuit 114 to generate the writing pattern. Output.

Specifically, as shown in FIG. 8C, for example, in the pattern generation unit 113, the preamble data (“00” pattern) 121 input by a series of sequences is converted into the preamble data (“11”). "pattern)
121A, training data (“88”,
The “68” pattern) 122 is used as training data (“T”
R1 ”,“ TR2 ”pattern) 122A, and the synchronization data (“ AA ”pattern) 123 is converted into synchronization data (“ S ”).
B "pattern) 123A.

The 8/9 converter 112 receives the user data 124 from the RDC interface 111, converts the user data 124 into 9-bit data 124A per byte, and outputs the data 124A to the MUX circuit 114. The MUX circuit 114 selects and outputs the signal sequence generated by the pattern generation unit 113 until the input timing of the synchronous data 123A, and thereafter selects the converted user data 124A from the 8/9 conversion unit 112. And outputs it to the parallel / serial conversion circuit 115.

As a result, the write data converted into the serial signal by the parallel / serial conversion circuit 115 is stored in the precoder 116 and the write precompression circuit 11.
7 and read / write via the flip-flop circuit 118
The writing IC 103 is transmitted. As a result, the read / write IC 103 causes the write driver 103
In A, the head 105 and the disk medium 104 are driven to write the write data (serial signal) from the RDC 102, while in the abnormality detection unit 103B, when the head 105 is short-circuited with respect to GND or for a long time. A write error or the like when there is no data change (change between "0" and "1") is detected, and this is notified as a WUS signal (Write unsafe).

[0020]

However, in the above-mentioned disk device shown in FIGS. 6 and 7, the HDC is particularly important.
When a failure occurs in 101, the RDC 102
After the gate WG is turned on, data (“8
8 "," 68 "," AA "pattern) may not be input.

In this case, the RDC 102 cannot generate a write pattern according to the data of each part, and reads / writes the abnormal write data (serial data), such as only the preamble, to the read / write IC 1
It will be output to 03. Such data is stored in the write abnormality detection unit 103 of the read / write IC 103.
In B, it cannot be detected as an abnormality.

Therefore, the conventional disk device has a problem that abnormal data is written to the disk medium 104 even if the data is abnormal.
Further, the RDC 102 only checks the parity of the data from the HDC 101, and even if the data according to the series of sequences as described above is not input, no abnormality is reported and the write operation is performed. There were times when it ended.

The present invention was devised in view of the above problems, and when an abnormality is detected by the RDC, the read / write IC of the related art notifies the HDC of the abnormality via a route of the RDC. It is an object of the present invention to provide a disk device that can notify an abnormality.

[0024]

Therefore, in the disk device of the present invention, a disk storage unit for storing data, and data for reading the data stored in the disk storage unit and writing the data in the disk storage unit. In a disk device including a read / write unit and an interface unit that performs conversion processing on read / write data between the data read / write unit and a host device, the data read / write unit includes
When an error in write data is detected based on the data from the interface unit, an error detection / notification unit is provided to notify the upper device of the error. Further, the disk device of the present invention includes an abnormality detection unit for detecting an abnormality in the write data from the host device, and an error detection / notification unit of the data read / write unit when the abnormality detection unit detects an abnormality in the write data. And an error data sending section for sending write data for detecting an error to the data reading / writing section.

In the disk device of the present invention, the clocking means for timing the time after the write data from the host device can be input and / or the write data from the host device has a predetermined data format. And a data format determining unit for determining whether or not the write data from the higher-level device is detected based on the timing information from the timing means and / or the determination information from the data format determining unit. It is characterized by being provided with an abnormality detecting section (claims 1 to 3).

Further, in the above-mentioned disk device of the present invention, when the abnormality detecting unit detects an abnormality in the write data, it is possible to provide an abnormality notifying means for notifying the upper device of the abnormality.

[0027]

1 is a block diagram showing a disk device according to an embodiment of the present invention. The disk device 16 shown in FIG. 1 has a larger storage capacity for a computer or a communication terminal, for example. It is mounted as an external storage device in order to secure it, and the HDC (Hard Disk Controll)
er) 1, RDC (ReaD Channel) 2, read / write IC (Read Write Integrated Circuit) 3, head 4,
It has a disk medium 5 and a spindle motor 5A.

Here, the HDC 1 controls the entire disk device 1 in response to a command from a higher-level device (not shown), similar to the one shown in FIG. 6 (see reference numeral 101). In addition, the RDC 2 reads / writes data.
It has a function as an interface unit that performs conversion processing on read / write data between the write IC 3 and the HDC 1 (or higher-level device).

Specifically, the RDC 2 receives the write data from the HDC 1 as an 8-bit parallel signal via the data bus 6, converts the parallel signal into a serial signal, and a read / write I described later.
While outputting to C3, read data from the read / write IC3 is converted from a serial signal into a parallel signal and output to the HDC1 via the data bus 6.

Further, the read / write IC 3 has a function as a data read / write unit for reading the data stored in the disk medium 5 and writing the data in the disk medium 5. Specifically, the read / write IC 3 records the write data from the RDC 2 on the disk medium 5 via the head 4 and reads the data recorded on the disk medium 5 via the head 4, R
It is adapted to output to HDC1 via DC2.
The head 4 can freely move in the radial direction or the circumferential direction on the recording surface of the disk medium 5 by an actuator (not shown).

Further, the disk medium (disk storage unit) 5
Is a magnetic disk or a magneto-optical disk for recording data in a format having magnetic or magneto-optical characteristics via the head 4, and the spindle motor 5
It is designed to be rotated by A. By the way, as the write data input from the HDC 1 via the data bus 6, as in the case of FIG. 8B described above, PRML (partial r
esponse most likelihood; based on an input sequence of partial response / maximum likelihood decoding), for example, preamble data (“00” pattern) 121 and training data (“88”, “88” as data for automatic equalization of an equivalent filter of a PR circuit) 68 "pattern) 122 and synchronous data (" AA "pattern) 123, header section 120, user data 124, ECC 125, and postamble data 126.

The above-mentioned synchronization data 123 and training data 122 may be arbitrary or fixed, and if automatic equalization is not required, the training data may be removed and a synchronization byte may be sent following the preamble data. . Further, in the case of using the PRML8 / 9 conversion method as the read / write method, the RDC 2 described above focuses on the processing for write data, and the RDC interface section 7, 8/9 conversion section 8, pattern generation section (pat
tern generate) 9, a multiplexer (MUX) 10, a serial / parallel converter 11, a precoder 12, a write precompression circuit 13, a multiplexer (MUX) 14 and a flip-flop (FF) 15.

Here, the RDC interface unit 7 is functionally composed of a pattern check / timing generate unit 7A, an abnormality detecting unit 7B and a parity check unit 7C in this example. Has been done. That is, the pattern detection / timing generation unit 7A detects the change and order of data in the header section 120 in the write data, and determines the timing for rewriting the header information based on the detected change and order of data in the header section 120. To generate.

Further, the abnormality detecting section 7B has a series of sequences as the data of the header section 120 in the write data within a fixed time after the write gate signal is turned on (a state in which the write data from the HDC 1 can be input). It is determined whether or not the data (“88”, “68”, “AA” pattern) according to the above is input, and the determination result is directly reported to the HDC 1 via the parity line 7D described later, and the multiplexing unit described later is also used. The read / write IC 3 outputs data capable of detecting an abnormality via 14.

In other words, in the abnormality detecting section 7B, when the data according to the series of sequences is not input within the above-mentioned fixed time, it is possible to detect that the HDC 1 is abnormal and output that fact. You can do it. Therefore,
The above-mentioned abnormality detection unit 7B has a function as a time measuring means for timing the time after the write data from the HDC1 can be input, and whether the write data from the HDC1 has a predetermined data format or not. A function as a data format determination unit, a function as an abnormality detection unit that detects an abnormality in the write data from the HDC 1 based on the timing information from the time counting means and the determination information from the data format determination unit and the abnormality detection unit. When an abnormality in the write data is detected, HDC is notified to that effect.
1 has a function as an abnormality notifying unit for notifying the user 1 and a function of creating abnormal data and inputting it to the multiplexing unit 14.

The above-mentioned abnormality detecting section 7B has a certain period of time for judging the input of data according to a series of sequences, and the data according to the series of sequences is normally input after the write gate signal is turned on. The time of 1.
The time can be set from 5 times to 2 times or more. Further, the parity check unit 7C performs a parity check on the write data input from the HDC1 via the data bus 106 together with the write gate signal, and the check result is output to the HDC1 via the parity detection line 7D. It has become.

The 8/9 conversion unit 8, the pattern generation unit 9, the multiplexing unit 10, the serial / parallel conversion unit 11, the precoder 12, the write precompression circuit 13 and the flip-flop 15 are shown in FIG. Since it has the same function as that shown in, the description thereof will be omitted. The multiplexing unit 14 multiplexes the write data from the write precompression circuit 117 from the write precompression circuit 117 and the determination result from the abnormality detection unit 7B and outputs the multiplexed data to the flip-flop 15. As a result, the flip-flop 15 operates in the multiplexing unit 1
The multiplexed signal from 4 is output to the read / write IC 103 at a predetermined timing.

By the way, the read / write IC 3 is
Focusing on the processing for write data, the write driver 3A and the write abnormality detection unit 3B are provided. Here, the write driver 3A writes the write data (serial signal) from the RDC 2 by driving the head 4 and the disk medium 5.

Further, the write abnormality detecting section 3B is
When an error in the write data is detected based on the data from C2, it has a function as an error detection / notification unit that notifies the HDC 1 to that effect. In particular,
The abnormality detection unit 3B is configured such that, when the write data sent from the RDC 2 is written, when the head 4 is short-circuited with respect to GND, or a long-term data change (“0”).
And a change in "1") are detected, and this is notified as a WUS signal (Write UnSafe).

Further, when the data in accordance with a series of sequences is not input from the HDC 1 within a fixed time after the write gate signal is turned on, in the above-described abnormality detecting section 7B, the write abnormality detecting section 3B is used. WU
A signal capable of outputting the S signal [for example, data that does not change for a long period of time (DC erase signal)] is output.

That is, the abnormality detecting section 7B described above writes the write data such that an error is detected in the write abnormality detecting section 3B of the data reading / writing IC 3 when the abnormality of the write data is detected. It also has a function as an error data sending unit for sending to 3B. By the way, when the abnormality detection unit 7B of the RDC interface unit 7 described above is focused on the function of determining whether or not data according to a series of sequences is input from the HDC 1 within a certain time, the hardware as shown in FIG. Have a configuration.

That is, in FIG. 2, 21 is a pattern generator (PATT GENE), 22, 23, 27 and 34 are comparators (COM), 24, 25 and 29 are inverters (N), 2
6, 33 are counters, 28, 36 are OR circuits, 30, 3
2 is a D flip-flop (FF), 31 is an EOR circuit, and 35
Is the delay line (DL). Here, the pattern generation unit 21
For example, data patterns (“88”, “68”, “A
A ") is configured by a shift register or a memory, and the output data is sequentially switched in synchronization with the input clock signal (when configured by the memory, the output data Addresses are now switching sequentially).

Further, the comparator 22 compares the data pattern input from the HDC 1 via the data bus 6 with the data pattern "00" in synchronization with the clock signal CLK, and the input data pattern is "00". If it is "," the counter 26
Is output to Further, the comparator 23
The data pattern input from the HDC 1 via the data bus 6 is compared with the data pattern as the comparison reference pattern generated by the pattern generation unit 21. In other words, this comparator 23 allows the HDC
It is possible to judge whether the write data from 1 has a predetermined data format.

The write data from the HDC1 is
When it has a predetermined data format, the pattern generator 21 can output the data of the data pattern (comparison reference pattern) to be input at the timing of the next clock signal CLK. In addition, the inverter 24 outputs a write gate signal WG (Write G
ate), and the inverter 25 inverts and outputs the clock signal CLK.

Further, the counter 26 receives the write gate signal as a reset signal, the signal (b) from the comparator 22, and the data input from the input of the write gate signal in synchronization with the clock signal. With respect to, the continuous state of the data pattern “00” is counted. In other words, the counter 26 turns on after the write gate signal from the HDC 1 is turned on (a state in which write data can be input),
The time is measured when no data other than "00" is input.

Further, the comparator 27 includes a counter 26
Output (c) is input, and the number of times the data pattern “00” is continuously input as the count value in the counter 26 is a predetermined number (for example, 10 times).
The result of the comparison is the clock signal CLK.
The inverted signal of is output to the OR circuit 36 as the clock CL.

In this case, the comparator 27
Is a signal to that effect (“H” level signal) when the data pattern “00” is input more than 10 times consecutively.
Can be output. Further, the OR circuit 28 receives the inverted signal of the write gate signal WG from the inverter 24 and the comparison result signal (i) from the comparator 34, which will be described later, and performs an OR operation on these signals.

Further, the inverter 29 is the comparator 2
The determination signal (b) as to whether the data pattern from 2 is “00” is inverted and output to the flip-flop 30. Further, the D flip-flop 30 holds the signal output from the inverter 29 as data, and outputs the signal (e) using the inverted signal of the clock signal CLK from the inverter 25 as the clock CL, while O
When the'H 'level signal is input as a signal from the R circuit 28, the information held as data is reset.

Further, the EOR circuit 31 includes the comparator 2
An exclusive OR operation is performed on the output from the D flip-flop 30 and the output from the D flip-flop 30. further,
The D flip-flop 32 holds the signal output from the EOR circuit 31 as data, outputs the data (g) using the clock signal CLK as the clock CL, and outputs the inverted signal of the write gate signal WG from the inverter 24 as a reset signal. Is input as a write gate signal WG
When is turned off, the information held as data is reset.

Further, the counter 33 outputs the inverted signal of the clock signal CLK delayed by the delay line 35 to the clock CL.
Then, the data pattern of the data (0) input from the flip-flop 30 in synchronization with the clock signal CLK via the data bus 6 is “0”.
The number of times the data different from 0 "is input is counted.

Further, the comparator 34 includes a counter 3
The output from 3 is compared with a predetermined number of times (four times, for example), and the comparison result is output to the OR circuit 28 as an inverted signal of the clock signal CLK as a clock CL. In this case, the comparator 34 outputs a signal ('H' level signal) to that effect when data having a data pattern different from “00” is continuously input four times. .

As a result, when the write gate signal is turned off or data having a data pattern different from "00" is input four times in a row, the output of the OR circuit 28 becomes an "H" level signal, and the flip-flop is turned on. The data held in the group 30 is reset, and the EOR circuit 31 is set to “L”.
A level signal is output. That is, data whose data pattern is not "00" (for example, "88",
"68", "AA") is not input at a predetermined timing, or the data pattern is not "00", a data pattern other than "88", "68", "AA" is input. If so, the OR circuit 31 outputs the'H 'level signal as an error bit to the flip-flop 32.

Further, the OR circuit 36 outputs as an error detection signal when the'H 'level signal is output from at least one of the output signal from the D flip-flop 32 and the output from the comparator 27. is there. The operation of the disk device according to the embodiment of the present invention having the above-described configuration will be described below with reference to the flowchart shown in FIG. 3 and the time charts shown in FIGS.

Outputs (see (a) to (j)) of the respective functional units in FIG. 2 correspond to the signals (a) to (j) in FIGS. 4 and 5. First, the abnormality detection unit 7B of the RDC interface unit 7 determines whether or not the write gate signal WG from the HDC 1 is turned on in synchronization with the input clock signal CLK [step A1.
From the NO route of step A2], when the write gate signal WG is turned on, the information on the time when no data is input, which is being counted by the counter 26, is reset [step A3, time point in FIG. 4 and FIG. t
1), (u1)].

Here, at the timing of this clock signal CLK, when the data of the "00" pattern is input, the count value of the counter 26 is increased by "1" and output as the counter output (c). [From the YES route of step A4 to step A5, time point (t
2) to (t4), see (u2) to (u4) of FIG. 5]. Further, based on the output (d) of the comparator 27, “0
When the data of the 0 "pattern is input 11 times in succession, it is output as an error detection signal through the OR circuit 36. [From the YES route of step A6 to step A
14], otherwise, wait until the next clock timing [from NO route of step A6 to step A
7].

At this timing, when the write gate signal WG is turned off, a standby state is set until the write gate signal WG is turned on next [YES route from step A8 to step A1]. Further, when the write gate signal WG is continuously in the ON state, at the timing of the clock signal CLK,
It is again judged whether or not the data of the "00" pattern is inputted [from the NO route of step A8 to step A
4].

Thereafter, similarly, until the data other than the "00" pattern is input at the timing of the clock signal CLK or the count value of the counter 26 becomes "11", the processing from step A4 to step A8 described above is performed. Be done. Further, when data other than the “00” pattern is input at the timing of the clock signal CLK, the data is “88” in the comparator 23.
It is determined whether or not it is a pattern [NO in step A4
From the root, step A9].

Here, when the data following the "00" pattern is not the data of the "88" pattern, the data does not follow a series of sequences, and the comparator 23 outputs an "H" level signal as an error bit. . This'H 'level signal is output as an error detection signal via the EOR 31, the D flip-flop 32 and the OR circuit 36 [from NO route of step A9 to step A9].
14].

Further, when the data following the "00" pattern is the data of the "88" pattern, it follows a series of sequences, and in the comparator 23, the data input by the timing of the next clock signal CLK is "6".
It is determined whether or not the data has an 8 "pattern [step A10, step A11, time point (t5) in FIG. 4, FIG.
Point (u5)].

That is, when the data following the "88" pattern is not the data of the "68" pattern [see the time point (u6) in FIG. 5], it is not the data according to the series of sequences but the case of the above step A9. Similarly, the OR circuit 3
6 outputs an error detection signal [from NO route of step A11 to step A14, time point (u7) in FIG.
(See (u8)].

Further, when the data following the "88" pattern is the data of the "68" pattern, it follows a series of sequences, and in the comparator 23, the data input by the timing of the next clock signal CLK is "A".
It is determined whether or not the data is the A "pattern data [see step A10, step A11, time point (t6) in FIG. 4].

Here, even when the data following the "68" pattern is not the data of the "AA" pattern, as in the case of the steps A9 and A11 described above, the OR is performed.
An error detection signal is output from the circuit 36 [Step A
Step A14 from No. 13 route]. Also, "6
When the data following the 8 "pattern is the data of the" AA "pattern, it is determined that the data format of the header part is a normal sequence, and therefore the OR circuit 36 does not output the error detection signal [step A13]. YES route, refer to time point (t7) in Fig. 4. When the error detection signal is output as described above, the abnormality detection unit 7B outputs the HDC1 signal via the parity detection line 7D.
To the write error detection section 3B of the data read / write IC 3, which is stored in a shift register or the like (not shown), for detecting an error.
The ERASE signal) is output via the multiplexer 14 and the flip-flop 15.

As a result, the write abnormality detection unit 3B detects an error based on the write data from the RDC interface unit 2 described above, and the WU is sent to the HDC 1.
By outputting the S signal, error detection can be reported. When the error detection signal is not output, the abnormality detection unit 7B notifies the HDC 1 of the abnormality via the parity detection line 7D as described above, and the write data such that the read / write IC 3 detects an error. Is not output.

As described above, according to the disk device of the embodiment of the present invention, when the abnormality detection unit 7B detects an abnormality in the write data, the write abnormality detection unit 3B of the read / write IC 3 detects an error. Write data as described above is written to the write abnormality detection unit 3
Since it can be sent to B, it is possible to prevent recording of illegal data on the disk medium 5 and to prevent the occurrence of a failure in the system including the disk device in advance.

Furthermore, conventional read / write I
Since the error information detected by the RDC2 can be notified to the HDC1 via the path from the C3 to the HDC1 for notifying the abnormality, it is not necessary to newly provide a path for detecting the abnormality, and the device can be configured. There is an advantage that the cost for doing so can be reduced. In addition, the abnormality detection unit 7B
When an anomaly in the write data is detected in (1), the fact can be notified to the HDC 1 via the parity detection line 7D, so that there is also an advantage that the reliability of anomaly detection can be improved.

In the above-mentioned abnormality detecting section 7B,
Within a certain time after the write gate signal is turned on,
As data of the header section 120 in the write data, data having a predetermined data format (“8
8 "," 68 "," AA "pattern) is input. However, the present invention is not limited to this, and it is not limited to" 00 "within a certain time after the write gate signal is turned on. The abnormality can be detected by determining whether the data is input, or the abnormality can be detected by simply determining whether the pattern of the input data has a predetermined data format.

[0067]

As described above in detail, according to the disk device of the present invention, when an abnormality of the write data is detected by the abnormality detection unit, an error is detected by the error detection / notification unit of the data read / write unit. Such write data can be sent to the error detection / notification unit, preventing unauthorized recording of data in the disk storage unit and preventing system failures that include disk devices from occurring in advance. can do.

Further, since the error information detected by the interface unit can be notified to the host device via the conventional route, it is not necessary to newly provide a route for detecting an abnormality, and the device can be configured. There is an advantage that the cost for doing so can be reduced. Further, when the abnormality detection unit detects an abnormality in the write data, it is possible to notify the higher-level device of that fact, so that there is an advantage that the reliability of the abnormality detection can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a disk device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of a disk device according to an embodiment of the present invention.

FIG. 3 is a flowchart for explaining an operation of the disk device according to the embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of the disk device according to the embodiment of the present invention.

FIG. 5 is a time chart for explaining the operation of the disk device according to the embodiment of the present invention.

FIG. 6 is a block diagram showing a general disk device.

FIG. 7 is a block diagram showing a main part of a general disk device.

FIG. 8 is a time chart for explaining the operation of a general disk device.

[Explanation of symbols]

1 HDC (upper device) 2 RDC (interface unit) 3 read / write IC (data read / write unit) 3A write driver 3B write error detection unit (error detection / notification unit) 4 head 5 disk medium (disk storage unit) 5A Spindle motor 6 Data bus 7 RDC interface 7A Pattern check / timing generator 7B Abnormality detector 7C Parity check 7D Parity detection line 8 8/9 Detector 9 Pattern generator 10 Multiplexer 11 Serial / parallel converter 12 Pre Coder 13 write precompression circuit 14 multiplexing unit 15 D flip-flop 16 disk device 21 pattern generation unit 22, 23, 27, 34 comparator 24, 25, 29 inverter 26, 33 counter 28, 36 OR Circuit 30, 32 D Flip-flop 31 EOR circuit 35 Delay line 101 HDC 102 RDC 102A Parity detection line 103 Read / write IC 103A Write driver 103B Write error detection unit 103C WUS signal 104 Disk medium 104A Spindle motor 105 Head 106 Data bus 111 RDC Interface part 112 8/9 conversion part 113 Pattern generation part 114 Multiplexing part 115 Parallel / serial conversion part 116 Precoder 117 Write precompression circuit 118 Flip-flop 120 Header part 121 Preamble data 122 Training data 123 Synchronization data 124 User data 125 ECC 126 Postamble data

Claims (3)

[Claims] 1. A disk storage unit for storing data, a data read / write unit for reading data stored in the disk storage unit and writing data in the disk storage unit, and the data read / write unit. In a disk device including an interface unit that performs conversion processing on read / write data between a host and a higher-level device, the data read / write unit causes an error in the write data based on the data from the interface unit. When the detection is made, an error detection / notification unit for notifying the upper device is provided, and a time measuring means for measuring the time after the write data from the upper device can be input, and the upper device. Does the write data from the device have the specified data format? A data format determining section for determining whether or not there is an abnormality, and an abnormality detecting section for detecting an abnormality in the write data from the host device based on the timing information from the timing means and the determination information from the data format determining section, Error data for sending write data to the data read / write unit such that an error is detected in the error detection / notification unit of the data read / write unit when an error in the write data is detected in the error detection unit A disk device characterized by having a sending unit. 2. A disk storage unit for storing data, a data read / write unit for reading data stored in the disk storage unit and writing data in the disk storage unit, and the data read / write unit. In a disk device including an interface unit that performs conversion processing on read / write data between a host and a higher-level device, the data read / write unit causes an error in the write data based on the data from the interface unit. When it is detected, it is provided with an error detection / notification unit for notifying the upper device of that fact, and a time measuring means for measuring the time after the write data from the upper device can be inputted, and the time measuring means. Abnormality of write data from the host device based on the time information from the means And an anomaly detection section that detects an error in the anomaly detection section and an anomaly detection section that detects an error in the anomaly detection section of the data reading / writing section. A disk device comprising an error data sending unit for sending to a read / write unit. 3. A disk storage unit for storing data, a data read / write unit for reading data stored in the disk storage unit and writing data in the disk storage unit, and the data read / write unit. In a disk device including an interface unit that performs conversion processing on read / write data between a host and a higher-level device, the data read / write unit causes an error in the write data based on the data from the interface unit. A data format determination unit that includes an error detection / notification unit that notifies the upper level device when it is detected, and determines whether the write data from the upper level device has a predetermined data format. Based on the judgment information from the data format judgment unit. Then, when an abnormality in the write data from the host device is detected, and when the abnormality in the write data is detected in the abnormality detection unit, an error is detected in the error detection / notification unit of the data read / write unit. A disk device, comprising: an error data sending unit for sending write data for detecting the error to the data reading / writing unit.