JPH04129068A - Data fetching system for recording and reproducing device - Google Patents

Abstract

PURPOSE:To prevent a failure in normal fetching of following recording/ reproducing units at the time of runaway of a VFO (phase synchronizing) clock by switching the clock to a recording/reproducing reference clock at the time of detecting step-out. CONSTITUTION:If a clock VFOCLK 4 is deviated to the low frequency side at a point A to detect VFOERR, a switch 32 is operated by VFOERR to switch the address control count-up clock from the VFOCLK 4 to a clock WRCLK 9, and input data of a read data buffer 19 is switched from 2-7 demodulated data to a fixed pattern. Then, a prescribed number of data per sector can be fetched in before the next sector, and data free from parity error is stored in the read data buffer memory 19. Thus, data of the next recording/reproducing unit is stored in the correct position of a reproduced data fetching circuit in the case of the occurrence of step-out of the VFO clock, and the processing of following recording/reproducing units is executed without interruption.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a recording/reproducing device suitable for a rotary recording medium such as an optical disk or a magnetic disk, and particularly relates to a recording/reproducing device suitable for a rotating recording medium such as an optical disk or a magnetic disk. The present invention relates to a data acquisition method for a recording and reproducing apparatus that performs recording and reproducing by switching data recording and reproducing clock frequencies.

[Conventional technology]

In general, MCAV (ModifiedC
Instant Angular Velocity
) type recording and reproducing apparatus is known (for example, as one applied to an optical disk device, Japanese Patent Application Laid-Open No. 62-262
There are publications such as Publication No. 271. ). In this MCAV method,
The recording capacity of an optical disc is increased by dividing the recording surface of an optical disc into several concentric zones corresponding to the radial position, and making the recording/reproducing fundamental frequency of the outer zone higher than that of the inner zone. (In addition, normal MCAV
Details of the system will be described later with reference to FIGS. 3 and 7. ) [Problems to be Solved by the Invention] In general, when recording and reproducing data and taking the reproduced data into its acquisition circuit (read data buffer), data recording, reproduction,
It is necessary to determine the capture speed, and V representing this speed
The FO signal is recorded on the recording medium for each sector, which is a data recording/reproduction unit. During reproduction, a VFO circuit (phase synchronization circuit) generates a VFO clock synchronized with this VFO signal, and the reproduction data of each sector is discriminated and taken in by this VFO clock.

In the MCAV system, the recording/reproducing frequency may be approximately twice or more different between the inner circumference and the outer circumference of the disk recording medium. Therefore, during playback, if the playback signal (especially the playback VFO signal) drops due to a defect in the recording medium or dust attached to the recording medium, or its level drops, the VFO circuit becomes unlocked and the VFO clock frequency increases. is more than twice the recording/reproducing basic frequency (recording/reproducing reference clock) or less than 1/2.

In addition, in order to synchronize the reproduced signal synchronization circuit (VFO circuit) with the reproduced signal over such a wide frequency range, it is necessary to widen the pull-in range of this circuit, but this is due to the output synchronization clock (VFO circuit). This conflicts with the requirement to reduce deviation in clock frequency.

When the VFO circuit goes out of control and the frequency of the VFO clock deviates to the lower frequency side, the speed at which the playback data acquisition circuit (read data buffer) takes in data from the start point of the runaway slows down and starts taking in the data of the next sector. Because it is not possible to import one sector's worth of data by this time, (
(The data storage position (address) of the read data buffer is counted up by the VFO clock)
The data of the next sector is stored shifted in the read data buffer. Therefore, not only the data of the sector where the runaway occurred, but also the data of the subsequent sectors cannot be correctly captured.

On the other hand, if the frequency of the VFO clock goes out of control to the high frequency side, the read data buffer address (ADR3)
Since the count-up for one sector (by the VFO clock) ends before the end of the data part of one sector, the count-up of the address is interrupted at this point, and the count-up for the next sector (at the time of the DETSYNC signal, which will be described later) is stopped. Address count-up is restarted. However, if the runaway frequency of the VFO clock exceeds the address count up circuit of the read data buffer or the operating frequency of the read data buffer, a miscount will occur in the address count and a parity error will occur in the captured data. ,
Subsequent data processing would have to be aborted.

Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, and to use a VFO clock synchronized with a playback signal to transfer playback data to its capture circuit (read data buffer) for each predetermined recording/playback unit (sector). ) to import MCAV into
An object of the present invention is to provide a data capture method that prevents, when a VFO clock runs out of control, not only the recording and playback unit in which the runaway occurred, but also subsequent recording and playback units, from becoming impossible to capture normally in a recording and playback device such as a VFO clock. .

[Means to solve the problem]

In order to achieve the above object, the data acquisition method of the recording/reproducing apparatus of the present invention includes a means for detecting the out-of-synchronization (runaway, abnormality) of the VFO clock, and a means for detecting the out-of-synchronization (runaway, abnormality) of the VFO clock. and means for switching the reproduction data acquisition clock (address count up clock of the read data buffer) from the VFO clock to the recording and reproduction reference clock.

Conversely, when the VFO clock is out of synchronization, the capture of playback data is interrupted (the count-up of the read data buffer address is interrupted), and the capture of the next recording/playback unit (sector) is restarted from the specified position. It is composed of

Furthermore, when performing read-after-write, a spare area is provided on the recording medium for the recording unit (sector in which the VFO error has occurred), thereby improving the reliability of data during reproduction.

[Effect]

The effect based on the above configuration will be explained.

When an out-of-synchronization of the VFO clock is detected, the read data acquisition circuit (read data buffer) switches the acquisition clock (count-up clock) from the VFO clock to the recording/reproduction reference clock, thereby reproducing data within the recording/reproduction unit (sector). At this point, address count-up of the read data buffer is performed normally, and data from the next sector onward is stored in the correct position.

In addition, if the VFO clock is out of synchronization (VFO abnormality), the read data buffer will take in the data (
By interrupting the counting of addresses (address counting) and storing the data of the next recording/reproducing unit (sector) from a prescribed position, data subsequent to the next recording/reproducing unit can be stored at the correct address.

Furthermore, by providing a replacement area on the medium for the recording/playback unit (sector) in which a VFO clock out of synchronization (VFO abnormality) is detected using the read-after-write method, recordings in which a VFO abnormality occurs during playback can be The number of playback units (sectors) can be reduced, thereby reducing the number of recording and playback units (sequentials) that may cause data errors.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings in comparison with the prior art.

First, a conventional MCAV method for reproducing an optical disc will be described with reference to FIGS. 3 and 7. FIG. 3 shows the configuration of a reproducing circuit system in a conventional optical disc reproducing system, and FIG. 7 shows the configuration of a sector format written on the optical disc.

In FIG. 7, SM is a sector mark, AM is an address mark, 10 is identification information such as a track address and sector number,
CRC is cyclic redundancy code, 5Y
NC is a synchronization signal, and VFO is a signal with a fixed code pattern (for example, 8
byte length, 12 byte length), DATA is, for example, 120
This is 0 bytes of data.

The reproduced light output from the signal detector 1 of the optical head passes through a preamplifier 2 and then is input to a waveform shaping circuit 3 and a sector mark detection circuit 4. After the reproduced optical output is binarized by the waveform shaping circuit 3, it is passed through a phase synchronization circuit (VFO circuit, Variable
e Frequency 0scillator)
26. In the VFO circuit 26, the input signal (
A VFO clock is generated which is phase-synchronized with changes in the VFO CLK (a reproduction of the VFO signal shown in FIG. 7).

The data discrimination circuit 27 performs data discrimination using VFOCLK4 and outputs an RDDATA (read data) signal 5.

The reference clock generation synthesizer 6 generates a recording/reproduction reference clock (WRCL K, read/write clock) based on the clock frequency instruction 8 from the read/write control unit 7.
Generates 9. The frequency of WRCLK9 is switched to a value corresponding to the reproduction speed of data reproduced from the recording medium for each zone of the disk recording medium. The sector mark detection circuit 4 outputs an SM (sector mark) signal 10 upon detecting a special pattern at the beginning of the sector. The gate signal generation circuit 11 generates AMGT (address mark detection gate) signals 12 and 5YNCGT (sync mark detection gate) by counting WRCLK9.
A signal 13 is generated from the SM signal 10.

The mark detection circuit 14 generates a DETAM signal (a signal indicating that an address mark has been detected) 15 by detecting an address mark pattern during the AMGT period, and also generates a DETAM signal 15 (a signal indicating that an address mark has been detected).
By detecting the 5YNC pattern during the YNCGT period,
A DETSYNC signal (signal indicating that a sync pattern has been detected) 16 is generated. 2-7 demodulation circuit I7 is DE
Byte synchronization for demodulating the RDDATA signal 5 is performed using the TAM signal 15 or the DETSYNC signal 16. The serial-parallel conversion circuit 18 converts the serial format data after 2-7 demodulation into 8 bits + 1 parity and inputs it to a memory (read data buffer memory) 19 for storing reproduced data.

The 10 detection circuit 20 stores the 2-7 demodulated data after inputting the DETAM signal, performs a CRC check (cyclic redundancy check) on the ID section, and uses the ID value as the read/write control section 7 and RD start detection. input to circuit 21; The read/start detection circuit 21 receives a read start address instruction 2 from the read/write control unit 7.
2, and when this address matches the output from the ID detection circuit 20, the RDSTART signal (read start signal, reading start signal) 23 is sent to the address control circuit 24.
Output to.

The address control circuit 24 is controlled by the read/write control section 7.
The read data buffer 19 receives an instruction for the start position of the read data buffer address (START ADRS, start address expressed as a position in the buffer) and the number of transfer data (in bytes) through the path 25, and after inputting the RDSTART signal. While counting up address ADR3 by 1 every VFO clock, a data write signal WR to the read data buffer 19 is generated to cause the read data buffer 19 to take in data.

In the MCAV method, the playback speed (playback frequency) of recorded data is, for example, 2 in the inner zone and outer zone of the disc.
Opens more than twice, so the recording and playback reference clock WRCL
The frequency of K9 is more than doubled. Therefore, during playback, if a sufficient reciprocating signal cannot be obtained due to media defects, dust, etc., and as a result, the VFO circuit 26 becomes unlocked, VFOCLK4 becomes more than twice the recording reciprocating reference clock or less than 172. Become. Data fetching when the VFO circuit 26 goes out of control and the frequency of VFOCLK4 shifts from the low frequency side to the high frequency side will be explained with reference to FIG. 4, assuming that the start address of the read data buffer is 0.

When VFOCLK is normal, the address (ADRS) of the read data buffer is the initial value "0" as shown in FIG. 4(a), and the DE after turning on RDSTART23 is
TSYNC16 starts address count-up, and after counting a specified number of bytes, for example, 1200 bytes in the sector, the count-up is interrupted and the DE of the next sector is started.
After TSYNC, the count-up starts again.

On the other hand, when VFOCLK goes out of control to a low frequency, as shown in the figure...), the count-up speed from the start point Since the count up for one sector (1200 bytes) has not been completed, the data of the next sector will be stored in the read data buffer with a shift.

In other words, even if VFOCLK goes out of control, the playback speed from the disk recording medium does not decrease; at the end of one sector period, one sector worth of signals (1200 bytes) is played back, but the data The discrimination circuit 27 can only identify this reproduced signal as data equal to the number of VFOCLKs that have runaway to the lower side, so the address of the read data buffer does not reach 1200 and ends.
The addresses of subsequent sectors are also shifted in order, and the shifted addresses are stored in the read data buffer.

Therefore, it becomes impossible to correctly capture data not only in the sector where the VFO has runaway, but also in subsequent sectors.

In addition, if the VFO goes out of control at high frequencies, see (C) in the same figure.
As shown in the figure, the count-up of ADR5 ends before the end of the data portion, the address count-up is interrupted, and the address count-up is restarted from DETSYNC of the next sector. However, if the runaway of VFOCLK exceeds the operating frequency of the address count up circuit or data buffer memory, it may cause a miscount of ADR3 or a parity failure of the captured data, causing subsequent data processing to be halted. become.

(Embodiment 1) FIG. 1 is a configuration diagram of a reproducing circuit of an MCAV type optical disk device according to an embodiment (Embodiment 1) of the present invention. In FIG. 1, elements having the same names as those in FIG. 3 are given the same reference numerals and explanations are omitted, but FIG. 1 differs from FIG. 3 in that the following circuits are added.

(1) VFO output clock (VFOCLK) 4 and recording/reproduction reference clock WRCL from the start of data acquisition
As a means of counting the difference in the cumulative number of clocks of K9, UP
VFOCLK on the terminal.

Connect WRCLK to the DWN terminal and DE to the reset terminal.
When the output of the UP/DWN (up/down) counter 30° (21UP/DWN counter 30 connected to TSYNC exceeds the specified value, for example, ±80 counts), it is determined that the synchronization is out of synchronization, and the VFOERR (VFOI error) is determined. The comparison circuit 31° (3) outputs 0) VFOCLK and holds it until the SM multiplied signal arrives (3).
Switch 32° (4) to switch the DATA input to the read data buffer 19 to an 8-bit fixed pattern with parity (a type of dummy data that prevents the clock timing from shifting) when VFOERR occurs. Switch S WS2°. (5) 8-bit fixed pattern generator 34 with parity (
11111111) (odd parity).

(6) A memory that receives a report from the comparison circuit 31 regarding the determination result of the presence or absence of out-of-synchronization (VFO error) and stores the sector in which the VFO error has occurred (so that it can be identified by a relative address, etc.) 35. Next, the operation of this embodiment (FIG. 1) when a VFO abnormality occurs will be explained using FIG. 5.

At point A, VFOCLK4 shifts to the low frequency side and V
Assume that FOERR is detected. This VFOERR operates the switch 32 to switch the address control count up clock from VFOCLK4 to WRCLK9, and also changes the input data of the read data buffer 19 to 2-
7 Switch from demodulated data to fixed pattern. As a result, a predetermined number of data per sector (for example, 1200 bytes) can be taken in by the next sector, and data without parity errors can be stored in the read data buffer memory 19.

Furthermore, if such a VFOERR occurs during a Read After Write, the VFO error sector can be identified by the VFO error memory 35, so a replacement sector is taken for the sector where the VFOERR occurred.

(Example 2) A second example (Example 2) of the present invention will be described with reference to FIG.

In this embodiment as well, the same elements as those in the conventional example (Fig. 3) are given the same reference numerals and explanations are omitted.
(Fig. 3), the following circuit has been added.

+1) The same UP/DWN counter 30 and comparison circuit 31 as above (2) Address load circuit 40 This address load circuit 40 receives the input of the start address and the number of transfers from the read/write control circuit section 7 through the path 25. In response to this, the address control circuit 24 is set to transfer a start address and 1200 data (bytes) for one sector.

RDSTART (output of RD start detection circuit 28)
While ON, the start address set in the address control circuit 24 is increased by 1200 for each SM signal, and 1200 data transfers for one sector are set.

(3) Switch SW41 that turns off the input VFOCLK to the count-up clock terminal of the address control circuit 24 when VFORR occurs.Next, using FIG. The operation of the device when this occurs will be explained.

Now, at point A, the VFO shifts to the low frequency side, and the VFO
Assume that ERR is detected. The switch 41 is operated by this VFOERR, and the count up clock of the address control circuit 24 is turned off.

This interrupts the address count-up.

After that, when the SM double signal of the next sector is detected, the start position of the data of the next sector will be the value set by the address load 40 (1200 in this case), regardless of the VFOBRR occurrence position A in the previous sector. As a result, if VFOERR occurs in a certain sector, only that sector becomes defective, and the data import of subsequent sectors will not be delayed, and the data import from the next sector onward will be performed normally. can be done.

〔Effect of the invention〕

As described in detail above, according to the present invention, when the VFO clock is out of synchronization during data reproduction, the clock for capturing the reproduced data is switched to the recording/reproduction reference clock, or the synchronization Since the retrieval of playback data for the recording/playback unit is temporarily interrupted, the data for the next recording/playback unit can be stored in the correct position of the playback data acquisition circuit, and the processing of the subsequent recording/playback unit is also interrupted. It can be executed without any

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a reproducing circuit of an MCAV type optical disk device according to an embodiment of the present invention, and FIG. 2 is a configuration diagram of a reproducing circuit of an MCAV type optical disk device according to another embodiment of the present invention.
Fig. 3 is a block diagram of a reproducing circuit of a conventional optical disk device, Fig. 4 is an explanatory diagram of the operation of Fig. 3, Fig. 5 is an explanatory diagram of the operation of Fig. 1, and Fig. 6 is an explanation of the operation of Fig. 2. FIG. 7 is a configuration diagram of a sector format of an optical disc. 1... Optical head, 4... VFO clock, 6... Reference clock synthesizer, 7...
. . . Read/write control section, 9 . . . Recording/reproduction reference clock, 19 . . . Read data buffer (reproduction data acquisition circuit), 30 . . . Up/down counter. 31... Comparison circuit (out-of-synchronization detector), 32... Switch (switching means), 33... Switch, 34... Fixed pattern generator, 35... VFO abnormal sector memory, 40... Address load circuit, 41...
...Switch (interruption means).

Claims (1)

[Claims] 1. The fundamental frequency of recording and reproduction increases from the inner circumference to the outer circumference of the recording medium, recording and reproduction is performed for each recording and reproduction unit consisting of a predetermined number of data, and V synchronized with the reproduction signal.
In a data acquisition method of a recording and reproducing apparatus that inputs reproduced data into a reproduced data acquisition circuit using an FO clock, a detecting means for detecting an out-of-synchronization of the VFO clock, and a detecting means that takes in the reproduced data when the out-of-synchronization is detected. 1. A data acquisition method for a recording/reproducing apparatus, comprising: switching means for switching a clock to a recording/reproducing reference clock output from a recording/reproducing reference clock generator. 2. The fundamental frequency of recording and reproduction increases from the inner circumference to the outer circumference of the recording medium, and recording and reproduction is performed for each recording and reproduction unit consisting of a predetermined number of data, and the reproduction data is captured by a VFO clock synchronized with the reproduction signal. In a data acquisition method of a recording and reproducing device that inputs reproduced data into a circuit, the present invention includes a detecting means for detecting an out-of-synchronization of the VFO clock, an interrupting means for interrupting the incorporation of the reproduced data when the out-of-synchronization is detected; 1. A data acquisition method for a recording/reproducing apparatus, comprising: control means for controlling the next unit of recording/reproducing data to be stored from a predetermined storage position in the reproduction data acquisition circuit after an interruption. 3. The detection means is configured to detect the out-of-synchronization for each recording/reproduction unit during read-after-write, and when an out-of-synchronization is detected, detects a replacement area for the detected recording/reproduction unit. 3. A data importing method for a recording/reproducing device according to claim 1, wherein the data capturing method is provided in a recording medium. 4. The detection means includes a monitoring means for monitoring the difference in the cumulative number of clocks between the VFO clock and the recording and reproduction reference clock from the start of capturing reproduction data for each recording and reproduction unit,
4. A data acquisition method for a recording/reproducing apparatus according to claim 1, wherein the data acquisition method for a recording/reproducing apparatus is configured to determine that synchronization is out of synchronization when this difference exceeds a predetermined number. 5. The reproduction data is taken in after demodulating the reproduction data, converting it into parallel bits, and adding a parity bit, and when an out-of-synchronization of the VFO clock is detected, Claim 1 characterized in that a fixed pattern with a parity bit is taken in as pseudo data in place of the reproduced data.
5. The data acquisition method of the recording/reproducing device according to any one of items 4 to 4.