JP3582440B2 - Disc reproducing method, disc reproducing apparatus and integrated circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a disc reproducing apparatus, particularly a disc having an output rate conversion function capable of reproducing a disc in which a subcode such as time information is recorded together with an audio signal as main information, such as a digital audio disc, at N-times speed operation. Playback deviceofIt relates to an integrated circuit.
[0002]
[Prior art]
Japanese Patent Application Laid-Open No. Sho 62-150560 discloses a reproducing process for performing N-times speed reproduction and performing intermittent access when the information reading means is accidentally moved by external force or the like during reproduction of a disc. Then, the digital audio data reproduced from the compact disk (CD) is written in the memory, and while the information reading means is moved to a position before the track jump from the time when the track jump occurs, the writing of the reproduction data from the disk is performed in the memory. It is known that the data is stopped and read at a constant period of the sampling frequency. According to this, reproduction data to be converted from digital to analog is not discontinuous, and can be reproduced continuously.
[0003]
[Problems to be solved by the invention]
In the above-mentioned prior art, an abnormal reproduction state such as generation of noise or temporary suspension of reproduction does not occur between the time when the information reading means is accidentally moved and the time when the information reading means returns to the normal position. No consideration was given to data management for the purpose of connection. That is, the subcode of the time information is output at the read timing in order to correspond to the read position of the disk, but the reproduced audio data is temporarily written to the memory to absorb the uneven rotation of the disk, and is read from the crystal oscillator. Since the sub-code and the audio data are read at the timing specified by the clock of the fixed frequency, an accurate one-to-one correspondence cannot be provided.
[0004]
A first object of the present invention is to solve such a problem and make it possible to always make the reproduced sub-code correspond to the audio data exactly one-to-one. As a result, the data can be converted using the audio data and the sub-code. Disc playback device with output rate conversion function that enables accurate and continuous connectionIntegrated circuitIs to provide.
[0005]
Further, a second object of the present invention is to enable the reproduced sub-code and the audio data to always correspond exactly one to one, so that even if the data is intermittently read from the disk, the audio data can be reproduced. By connecting data accurately and continuously using data and sub-codes, it is not necessary to switch between an equalizer and clock reproduction to obtain an N × speed output and a normal output.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention providesIn an integrated circuit applied to a disk reproducing device having a pickup,An input terminal to which the modulated information data and control information corresponding to the information data are input, a demodulation means for demodulating the information data and the control information, and an error correction of the information data demodulated by the demodulation means Processing means for performing deinterleaving processing, a first output terminal from which the demodulated control information is output, and a one-to-one correspondence between the demodulated control information and the information data processed by the processing means. The second output terminal output with a relationship, the demodulated control information and the processed information data are stored in a storage unit, and the processed information data stored in the storage unit are stored in the storage unit. Control means for causing the demodulated control information to have a one-to-one correspondence and outputting the demodulated control information to the second output terminal.Control information is output from the first output terminal and the second output terminal to control a pickupIt is an integrated circuit.
In order to achieve the above object, the present invention provides a pickup for reading the information data and the control information from a disc on which the information data and the control information are recorded, and a demodulation of the information data and the control information read by the pickup. And performing error correction and deinterleaving of the demodulated information data, outputting demodulated control information, and storing the demodulated control information and the error corrected and deinterleaved information data in a first storage. Processing means for storing and outputting the information, second data storage means for storing the information data and control information output from the processing means in a one-to-one correspondence, and controlling the reading position of the pickup. Writing the information data to the second storage means using the first control means to perform the control and the control information output to the second storage means. Control means for controlling only the information data and outputting the information data from the second storage means, wherein the first control means controls the demodulated control information and the second storage means. A reading position of the pickup is controlled by using the control information output to the means.
[0007]
Also, the present inventionIn order to control the reading position of information reading means for reading information data and control information from a storage medium, the control information is sent from the first output terminal.The configuration is to be output.
[0008]
Further, the present invention providesInformation data and control information having a one-to-one correspondenceIsSaidWith a one-to-one correspondenceSaidBecause it is stored in a storage unit different from the storage unit used by the processing unitTo, Output from the second output terminal.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking a compact disc (CD) reproducing apparatus as an example.
[0012]
FIG. 1 is a block diagram showing an embodiment of a disk reproducing apparatus with an output rate conversion function according to the present invention, wherein 1 is a disk, 2 is a motor, 3 is a pickup servo circuit, 3 'is a motor servo circuit, and 4 is Pickup 5, preamplifier 8, subcode 8 including time information, 13 access data, 14 CD signal processing circuit, 15 RAM, 16 address information, 17 output data, 18 time information detector, 19 An address control circuit, 20 is overflow / underflow information, 21 is a system control microcomputer, 22 and 23 are intermittent access information, 24 is read information, 42 is a read clock, 44 is a read clock generator, 45 is a read clock generator, 46 is a switching signal, and 61 is a write address generation clock.
[0013]
A digital signal reproduced from a CD includes a subcode 8 in addition to audio digital data. In the subcode 8, as shown in FIG. 2, eight channels P to W are allocated to the area immediately after the frame synchronization signal, and the subcode 8 is completed in 98 frames including the subcode synchronization signals S0 and S1. In the Q channel of the subcode 8, time information and control signals are recorded, and an error detection code is added to enable high-reliability reproduction.
[0014]
In FIG. 1, the disk 1 is rotated at a speed N times the normal speed (normal reproduction) by a motor 2, and data is read from the disk 1 by a pickup 4 controlled by a pickup servo circuit 3. The reproduced data is supplied to the CD signal processing circuit 14 via the preamplifier 5 and the audio data to which the sub-code 8 including the time information is added as the access data 13 is N times the output rate at the standard speed. Is output at the output rate.
[0015]
The CD signal processing circuit 14 also outputs a write address generation clock 61 and a subcode 8 synchronized with the reproduction data. The write address generation clock 61 is transmitted to the address control circuit 19 together with the access data 13, and the subcode 8 is output to the subcode 8. Each is supplied to the system control microcomputer 21.
[0016]
The access data 13 having such an N-times output rate is written to and read from the RAM 15 controlled by the address control circuit 19. At this time, as the address information 16 of the RAM 15, a write address is generated from the write address generation clock 61 from the CD signal processing circuit 14 by the address control circuit 19, and a read address is generated from the standard speed read clock generation circuit 44. From the read clock 42. Accordingly, in the RAM 15, writing is performed at N times the standard speed, and reading is performed at the standard (1 ×) output rate.
[0017]
Here, the address control circuit 19 and its peripheral circuits will be described.
[0018]
The address control circuit 19 generates address information 16 which is a write address and a read address of the RAM 15. If the disk 1 is an audio disk, the system control microcomputer 21 determines from the subcode 8 that the reproduction signal is audio data, selects the standard speed read clock generation circuit 44 by the switching signal 46, and reads the standard speed read clock. The clock is supplied to the address control circuit 19. The address control circuit 19 generates a read address based on the standard speed read clock. Therefore, the access data 13 output from the CD signal processing circuit 14 at an N-fold output rate and written into the RAM 15 is read from the RAM 15 at a standard rate.
[0019]
By the way, the CD signal processing circuit 14 operates at N times speed, and the timing of writing to the RAM 15 is N times the standard speed, but the timing of reading audio data from the RAM 15 is the standard speed (1 × speed). Before reading all data from the RAM 15, the RAM 15 overflows. Therefore, the address control circuit 19 including the time information detecting section 18 and the system control microcomputer 21 perform write / read control for preventing such overflow.
[0020]
That is, the time information detecting section 18 of the address control circuit 19 detects the time information at the time of writing based on the access data 13, and uses the information and the disk read information 24 from the system control microcomputer 21 in the RAM 15. The time difference information between the time information at the time of writing and the time information at the time of reading is detected, and based on the detection result of the time difference information, it is monitored whether the RAM 15 overflows or underflows. When detecting that the RAM 15 has overflowed, the address control circuit 19 outputs write information 41 for inhibiting writing to the RAM 15, stops writing to the RAM 15, and supplies the overflow information 20 to the system control microcomputer 21. The system control microcomputer 21 generates the intermittent access information 22 and 23 using the overflow information 20 and the time information at the time of write prohibition, and supplies these to the pickup servo circuit 3 and the motor servo circuit 3 ', respectively. Thus, the pickup servo circuit 3 moves the pickup 4 to the next data position on the disk 1 to be connected.
[0021]
When detecting that the RAM 15 underflows, the address control circuit 19 outputs the write information 41 for releasing the write prohibition to the RAM 15 and outputs the underflow information 20 for re-accessing the disk 1 to the system control microcomputer 21. I do. As a result, the pickup 4 reads data to be subsequently connected from the disk 1 and writes the data to the RAM 15 again via the CD signal processing circuit 14.
[0022]
As described above, in this embodiment, the access data 13 output from the CD signal processing circuit 14 at an output rate N times the standard speed is temporarily stored in the RAM 15, and the reading / writing of the RAM 15 is performed so that the reading is performed at the standard speed. , The time difference between the N-fold operation speed of the system and the standard output speed of the output data can be absorbed, and the output data can be reproduced continuously.
[0023]
Next, the CD signal processing circuit 14 in FIG. 1 will be described with reference to FIG. In FIG. 3, 6 is a demodulation circuit, 7 is audio data, 9 is a data bus, 10 is an address control circuit 2, 11 is a RAM, and 12 is an audio data processing circuit. Reference numerals are given and duplicate description is omitted.
[0024]
In FIG. 3, reproduction data supplied from a preamplifier 5 is demodulated by a demodulation circuit 6 and separated into audio data 7 and a subcode 8. The subcode 8 is output from the CD signal processing circuit 14 as it is.
[0025]
The audio data 7 is written into the RAM 11 through the data bus 9 under the control of the address control circuit 10 in order to absorb jitter due to uneven rotation of the disk 1 and to perform error correction processing and deinterleave processing by the audio data processing circuit 12. It is. At this time, the subcode 8 is also written to the RAM 11 through the data bus 9. The audio data 7 and the subcode 8 written in the RAM 11 are read out from the RAM 11 under the control of the address control circuit 10, and the audio data 7 is interpolated by the audio data processing circuit 12, 8 is added and output from the CD signal processing circuit 14 as access data 13.
[0026]
The operation of the address control circuit 10 in FIG. 3 at this time will be described with reference to FIG. In this figure, 25 is a write address generation circuit, 26 is a write address, 27 is a read address generation circuit, 28 is a read address, 29 is an address monitoring circuit, and 30 is an address switching circuit, which corresponds to FIG. Are denoted by the same reference numerals, and redundant description is omitted.
[0027]
A write address 26 for writing to the RAM 11 is generated by a write address generation circuit 25 from a reproduction system clock synchronized with the reproduction data, and a read address 28 for reading from the RAM 11 is generated from a clock by a crystal oscillator (not shown). Generated by the circuit 27. Conventionally, the subcode 8 is not written in the RAM 11 but is output at the timing of reading the disk 1 in order to correspond to the reading position on the disk 1, but in this embodiment, the subcode 8 is 8 is also written and read from the data bus 9 to the RAM 11. At this time, the write address 26 and the read address 28 are switched by the address switching circuit 30. The address monitoring circuit 29 keeps an interval of ± 4 frames to absorb uneven rotation of the disk 1.
[0028]
The access data 13 thus obtained by the CD signal processing circuit 14 is supplied to an address control circuit 19 in FIG. 3, and the time information is detected by a time information detecting unit 18 to write the data corresponding to the capacity of the RAM 15 and write the data. To stop. The time information detecting unit 18 detects each time difference information based on the access data 13 and the read information 24 of the disk, and monitors the overflow / underflow of the RAM 15 based on the detection result of the time difference information. While detecting the address of data to be connected next, the overflow / underflow information 20 for re-accessing the disk 1 is output to the system control microcomputer 21.
[0029]
The operation of the address control circuit 19 at this time will be described with reference to FIG. However, in the figure, 31 is a time information detection circuit, 32 is time information, 33 is a write address generation circuit, 34 is a time information detection circuit, 35 is time information, 36 is a read address generation circuit, 37 is a difference detection circuit, 38 is difference information, 39 is an overflow / underflow detection circuit, 40 is a write control circuit, and 41 is write information.
[0030]
In the time information detecting section 18, time information is detected by the time information detecting circuit 31 from the access data 13 output from the CD signal processing circuit 14, and based on the disk read information 24 from the system control microcomputer 21. The read address of the RAM 15 generated at the rate of the read clock 42 is generated by the read address generation circuit 36, and the time information 35 at the time of audio output is detected by the time information detection circuit 34 from the read address. The time information 32 detected by the time information detection circuit 31 is supplied to the write address generation circuit 33, and the write address of the RAM 15 is generated at the rate of the write address generation clock 61. The write address and the read address are switched by the address switching circuit 30 ', and are supplied to the RAM 15 as address information 16.
[0031]
Further, the difference between the time information 32 detected by the time information detection circuit 31 and the time information 35 generated by the time information detection circuit 34 is detected by the difference detection circuit 37, and the difference information 38 between the write address and the read address of the RAM 15 is detected. Is supplied to the overflow / underflow detection circuit 39. The overflow / underflow detection circuit 39 detects overflow / underflow of the RAM 15 from the difference information 38 and supplies the overflow / underflow information 20 of the RAM 15 to the system control microcomputer 21 of FIG. When the RAM 15 overflows, it outputs write information 41 for prohibiting the writing.
[0032]
The system control microcomputer 21 outputs intermittent access information 22 and 23 using the overflow / underflow information 20 and the time information 32 at the time of write inhibition, and the pickup servo circuit 3 picks up based on the intermittent access information 22. 4 is moved to the next data position to be connected.
[0033]
When the overflow / underflow detection circuit 39 detects the underflow of the RAM 15 from the difference information 38, the write control circuit 40 outputs the write information 41 for canceling the write-protection, and the pickup 4 outputs the next write information. Is reproduced from the disk 1, and the reproduced data is written into the RAM 15 again as described above.
[0034]
As described above, in this embodiment, since the time information is added to the audio data output from the CD signal processing circuit 14, the connection point of the data can be accurately detected. Therefore, the output data is reproduced continuously.
[0035]
FIG. 6 is a block diagram showing another embodiment of a disc reproducing apparatus with an output rate conversion function according to the present invention as a CD-ROM reproducing apparatus. Reference numeral 43 denotes a CD-ROM signal processing circuit. Parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and redundant description is omitted.
[0036]
This embodiment is configured to be able to output data at a double speed when handling data, based on the utility of the CD-ROM as a database. On the other hand, when playing back a CD on which music data is recorded in this embodiment, the signal processing unit performs a double speed operation so that output data can be obtained at a standard speed. The CD-ROM is a system for managing data in sector units, and one sector is composed of 98 frames. Therefore, in order to perform standard reproduction of a CD on a CD-ROM, it is necessary to add a signal similar to a sector number to reproduction data of the CD.
[0037]
Hereinafter, the operation of the embodiment shown in FIG. 6 will be described with reference to FIG.
[0038]
When the disk 1 is a data disk as a CD-ROM, the system control microcomputer 21 determines that the reproduced signal is the data from the data disk 1 by the subcode 8 from the CD signal processing circuit 14, and The read clock 42 from the double-speed read clock generation circuit 45 is selected so that the output data 17 can be obtained at twice the speed from the RAM 15 as shown in FIG.
[0039]
If the disk 1 is an audio disk as a CD, the system control microcomputer 21 determines from the subcode 8 that the reproduced signal is audio data, and uses the switching signal 46 to output a read clock generation circuit for the standard speed. The read clock 42 from 44 is selected so that the output data 17 can be obtained from the RAM 15 at a standard speed as shown in FIG. The CD-ROM signal processing system operates at double speed, and the timing of writing the access data 13 to the RAM 15 is twice the standard speed. On the other hand, the timing at which data is read from the RAM 15 is the standard speed, and the RAM 15 overflows before all data is read. However, in this embodiment, the audio data 7 includes 98 frames containing time information. Is output from the CD signal processing circuit 14 with the addition of the sub-code 8, the data can be managed on a sector-by-sector basis, an accurate connecting point can be detected and a time difference can be detected. The time difference between the standard speed and the output speed of the output data 17 is absorbed.
[0040]
As described above, in this embodiment, since the access data 13 is added with the sub-code in the unit of 98 frames, the access data 13 is written into the RAM 15 and the output data is output by the address control circuit 19 of the CD-ROM signal processing circuit 43. By detecting the time difference between the access data 17 and the access data 13, measuring the overflow / underflow of the RAM 15, sending the intermittent access information 22 and 23, and detecting the time again to detect the correct connection point, the writing speed to the external RAM is reduced. Can be adapted to a CD-ROM system in which the reading speed is set to the standard speed by setting N to N times the standard speed, and the circuit can be shared.
[0041]
Further, this embodiment is also applicable to a mini-disc (MD) system in which data is compressed to one-fifth and recorded.
[0042]
FIG. 8 is a block diagram showing a specific example of the time information detecting circuit 18 shown in FIGS. 1, 3 and 6, wherein 24 'is an address setting clock, 24 "is an address load signal, 47 is a shift register, 48 is an information data latch circuit, 49 is an error detection circuit, 50 is an error detection result, 51 is a Q code register, 52 is time information, 53 is a BCD counter, 54 is a counter value, 55 is a setting address register, and 56 is a BCD counter. , 57 are counter values, 58 is a coincidence detection circuit, 59 is a coincidence detection result, and 60 is a needle jump detection circuit.
[0043]
First, the operation of this specific example will be described with reference to FIG. 9 assuming that the quadruple speed operation is an example and that there is no needle jump.
[0044]
The set value n from the system control microcomputer 21 is taken into the set address register 55 and loaded into the BCD counter 56. At the same time, the write address counter 33 and the read address counter 36 are reset.
[0045]
The access data 13 obtained by adding a signal similar to a sector number to the reproduction data of the CD using the subcode 8 is fetched into the shift register 47, and the information data is further stored in the information data latch circuit 48 and the subcode 8 The Q code is taken into the Q code register 51 and the error detection code is taken into the error detection circuit 49. If the error detection result 50 from the error detection circuit 49 indicates “no error”, the time information 52 of the BCD code taken into the Q code register 51 is loaded into the BCD counter 53, and the error detection result 50 If "error" is indicated, the BCD counter 53 counts up by one to the current value.
[0046]
The count value 54 of the BCD counter 53 and the count value 57 of the set value n of the BCD counter 56 are compared by a coincidence detection circuit 58, and the count value 54 of the BCD counter 53 is sequentially changed by the above operation, and finally the set value If the value matches n, the match detection result 59 of the match detection circuit 58 indicates this, indicating that the data reproduction position has reached the target position of the set value n set by the system control microcomputer 21. Based on the coincidence detection result 59, the BCD counter 56 and the write address generation circuit 33 for generating a write address to the RAM 15 start operating, and count up by one at a timing synchronized with the acquisition of the Q code of the Q code register 51, respectively. I will do it.
[0047]
The read address counter 36 also starts operating at the same time, and generates a read address in synchronization with the write clock 42.
[0048]
Since the write address and the read address to the RAM 15 are generated not by the BCD but by a binary number, the address of the RAM 15 can be effectively used even if it is generated based on the time information 52 which is the BCD code.
[0049]
The write address from the write address generation circuit 33 and the read address from the read address counter 36 are supplied to a difference detector 37, and difference information 38 indicating the difference is obtained. The difference information 38 is supplied to an overflow / underflow detection circuit 39, which detects whether the data stored in the RAM 15 overflows or underflows. In the case of overflow, a pause start signal is output from the overflow / underflow detection circuit 39 to stop writing to the RAM 15, and when an underflow is detected thereafter, a pause release signal is output and writing to the RAM 15 is performed again. Let it start.
[0050]
Here, in FIG. 9, the capacity of the RAM 15 is assumed to be a capacity of 5 addresses for the sake of simplicity. Therefore, the write address counter 33 also repeats the count of 0 to 4 of the read address counter 36.
[0051]
Therefore, in the RAM 15, one piece of information data is read while four pieces of information data are written. Therefore, during the period in which the n-th to (n + 3) -th pieces of input information data are sequentially written to the addresses 0 to 3, 1, when the (n + 1) th information data is read out, first, the (n + 4) th input information data is written into the address 4, and then (n + 5) ) -Th input information data is about to be written to address 0. However, when the difference (WR) between the write address and the read address is equal to or more than a value smaller than the number of addresses (capacity) in the RAM 15 by one or more, if the overflow occurs, the (n + 5) -th input information Writing data will overflow. For this reason, a pause start signal is output from the overflow / underflow detection circuit 39 to stop the writing to the RAM 15, and at the same time, the counting operation of the BCD counter 56 and the writing address counter 33 is stopped, and the count value at that time is reduced. Keep it as it is. Thus, the BCD counter 56 holds the count value 57 of the value (n + 5) as it is, and the write address counter 33 holds the address value of the value 0 as it is. However, reading from the RAM 15 is continued as it is.
[0052]
The system control microcomputer 21 captures the pause start signal as overflow information 20 and generates intermittent access information 22 and 23 using the pause start signal and the time information at the time of write inhibition as described above. And the motor servo circuit 3 '. Thus, the pickup servo circuit 3 moves the pickup 4 to the next data position on the disk 1 to be connected.
[0053]
During this time, the RAM 15 is being read, and when the RAM 15 underflows, a pause release signal is output from the overflow / underflow detection circuit 39, and the suspension of writing to the RAM 15 is released. Here, it is assumed that an underflow occurs when the difference (WR) between the write address and the read address becomes equal to or less than the number of sectors for one round of the disk 1, and that two sectors are recorded in one round of the disk 1. Then, underflow occurs when (WR) is 2 or less.
[0054]
Therefore, as described above, the write address W from the write address counter 33 is fixed at 0, so when the read address R from the read address counter 36 becomes 3, the write address corresponds to 5 which is further ahead. Therefore, the overflow / underflow detection circuit 39 determines that the RAM 15 has underflowed, generates a pause release signal, and starts writing to the RAM 15. Even when this writing starts, the write address W from the write address counter 33 is fixed at 0, and the count value of the BCD counter 56 is fixed at (N + 5). When the (n + 5) th data is reproduced from the disk 1, the count values of the BCD counters 53 and 56 match (n + 1), and a match detection result 59 is output from the match detection circuit 58 to output the BCD counter 56 and The write address counter 33 resumes operation. Therefore, data is written into the RAM 15 in the order of (n + 5) th, (n + 6),... From address 0 until the next overflow occurs.
[0055]
In this way, the writing operation is reliably restarted from the next data after the writing operation is stopped.
[0056]
Next, the operation of this specific example will be described with reference to FIG. Here, it is assumed that the needle jump occurs after the (n + 9) th data is reproduced, and then the (m) th data is reproduced.
[0057]
The needle jump detection circuit 60 determines that if there is no error in the reproduction data from the error detection result 50 and there is no predetermined difference (for example, 1) between the time information 52 and 54, discontinuity occurs in the reproduction data due to a needle jump or the like. Then, as in the case of the overflow, the operations of the BCD counter 56 and the write address counter 33 are stopped, and the (n + 10) th data is accessed. Then, when the (n + 10) th data is reproduced, the writing to the RAM 15 is restarted by the match detection result 59 of the match detection circuit 58.
[0058]
As described above, in this embodiment, even if the Q code of the subcode which is the time information of the BCD code is used, the address generation of the RAM 15 is performed in a binary number, and the standard speed reproduction at the time of the quadruple-speed operation is performed by effectively using the RAM 15. It is possible to correspond to. Further, even if a needle jump occurs due to vibration or the like, continuous reproduction can be performed by accurately connecting data.
[0059]
Also, if the CD signal processing circuit 14 in which the processing of the audio data and the subcode shown in FIGS. 1 and 3 are made to correspond one-to-one is one integrated circuit, the address control shown in FIGS. If the circuit 19 is combined as another integrated circuit, and if the CD-ROM processes ROM data and audio data, the CD-ROM signal processing circuit 43 of FIG. 6 is combined as another integrated circuit. By doing so, it can be deployed to each system.
[0060]
As described above, in this embodiment, an integrated circuit that associates audio data with time information on a one-to-one basis is separated from an integrated circuit that stores audio data and time information using the corresponding data. It is not limited to the form.
[0061]
Note that the numerical values shown in the above embodiments are examples, and the present invention is not limited to these.
[0062]
【The invention's effect】
As described above, according to the present invention, even when intermittent access is performed due to a track jump or the like, the time information is added to the data output from the signal processing unit, so that the data connection point can be accurately determined. The output data can be detected and reproduced continuously without discontinuity.
[0063]
In addition, data is once written to the external RAM and then read, the time difference between the write data and the read data is detected, the overflow of the RAM is detected, the writing to the RAM is prohibited, and the connection point of the correct data is detected and picked up. When an underflow is detected, intermittent access is performed to release the write prohibition to the RAM and restart the write. Even if the write to the RAM is N times the standard speed and the read is the standard speed, The output data can be reproduced continuously without discontinuity.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a disk reproducing apparatus according to the present invention.
FIG. 2 is a diagram showing a subcode format of a CD.
FIG. 3 is a block diagram showing an internal configuration of a CD signal processing circuit in FIG. 1;
FIG. 4 is a block diagram showing an address control circuit of the CD signal processing circuit in FIG. 3;
FIG. 5 is a block diagram showing an address control circuit in FIG. 1;
FIG. 6 is a block diagram showing another embodiment of a CD-ROM compatible disk reproducing apparatus according to the present invention.
FIG. 7 is a timing chart showing the operation of the embodiment shown in FIG.
FIG. 8 is a block diagram showing a specific example of a time information detection circuit in FIGS. 1, 3, 5, and 6;
9 is a timing chart showing the standard reproduction timing at the time of the quadruple speed operation in the specific example shown in FIG. 8 without the needle jump.
FIG. 10 is a timing chart showing the standard reproduction timing at the time of the quadruple speed operation when the specific example shown in FIG.
[Explanation of symbols]
1 disk
4 Pickup
6. Demodulation circuit
8 Subcode
10. Address control circuit
11 RAM
13 Access data
14 CD signal processing circuit
15 RAM
16 Address information
17 Output data
18 Time information detector
19 Control circuit
20 Overflow / underflow information
21 System control microcomputer
22, 23 Intermittent access information
24 Disk read information
39 Overflow / underflow detection circuit
40 Write control circuit
41 Write information
42 Read clock
44 Standard Speed Read Clock Generation Circuit
45 Double-speed read clock generation circuit
53,56 BCD counter
61 Write address generation clock

Claims (8)

In an integrated circuit applied to a disk reproducing device having a pickup,
An input terminal to which the control information corresponding to the information data and modulated information data is input,
Demodulating means for demodulating the pre SL information data and the control information,
Processing means for performing error correction and deinterleaving the information data demodulated by the demodulating means,
A first output terminal to which the demodulated control information is output,
A second output terminal and the processed information data is output with a one-to-one correspondence by said demodulated control information and said processing means,
Wherein the processed information data and demodulated control information is stored in the storage means, demodulation control information and the one-to-one correspondence with the information data are processed that it has been stored in said storage means the made to have and control means for outputting said second output terminal,
An integrated circuit, wherein control information is output from the first output terminal and the second output terminal to control the pickup . Oite to claim 1,
The information data and the control information having the one-to-one correspondence are stored in a storage unit different from the storage unit used by the processing unit while having the one-to-one correspondence, 2. An integrated circuit, which is output from an output terminal of (2). A pickup that reads the information data and the control information from a disc on which the information data and the control information are recorded,
The information data and control information read by the pickup are demodulated, error correction and deinterleaving of the demodulated information data are performed, demodulated control information is output, and the demodulated control information, error correction and data Processing means for storing the interleaved information data in the first storage means and then outputting the data;
Second storage means for storing the information data and control information output from the processing means in a one-to-one correspondence,
First control means for controlling a reading position of the pickup;
Controlling the writing of the information data to the second storage means using the control information output to the second storage means and controlling the information data to be output from the second storage means; 2 control means,
A disk reproducing apparatus, wherein the first control means controls a reading position of the pickup using the demodulated control information and the control information output to the second storage means . In claim 3,
The demodulated control information and the control information output to the second storage unit include time information of the information data,
The disc reproducing apparatus according to claim 2, wherein said second control means controls said second storage means so as to output said information data in the order of time indicated by said time information. In claim 3,
The demodulated control information and the control information output to the second storage unit include information indicating an order of the information data,
It said second control means, to output thus the information data to the information indicating the order, the disk reproducing apparatus, characterized by controlling the second storage means. Reading the information data and the control information from the disc on which the information data and the control information are recorded,
Demodulate the read information data and control information,
Perform error correction and deinterleaving of the demodulated information data,
Outputting the demodulated control information,
Storing the demodulated control information and the error-corrected and deinterleaved information data in a first storage unit, and outputting the data;
The output information data and the control information are stored in the second storage means in a one-to-one correspondence relationship,
Controlling the writing of the information data into the second storage means using the control information output to the second storage means, and controlling the information data to be output from the second storage means;
A disk reproducing method, wherein a reading position of the pickup is controlled using the demodulated control information and the control information output to the second storage means . In claim 6,
The demodulated control information and the control information output to the second storage unit include time information of the information data,
A disk reproducing method, wherein the second storage means is controlled so as to output the information data in the order of time indicated by the time information. In claim 6,
The demodulated control information and the control information output to the second storage unit include information indicating an order of the information data,
Disk playback method characterized by to output thus the information data to the information indicating the order, controls the second storage means.

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