JP2004087128A - Disk reproducing device and method for reproducing disk - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to cope with standard speed reproduction in N-speed operation as well as intermittent access caused by track skip in a conventional CD reproduction system. <P>SOLUTION: A disk reproducing device is provided with a memory 11 complying data reproduced from a disk 1 with time information and writing the data and the time information, and another external memory 15, so that time difference between the finally outputted data 17 and the data 13 in the course of access is detected by means of the time information detection circuit 18 of an address control circuit 19 to detect the overflow and underflow of the external memory 15, and the writing to the external memory 15 is controlled based on the detection result, the time difference between system operation speed and data output speed is absorbed even when the intermittent access is done by controlling a pickup 4, so as to obtain the continued data 17 correctly connected at the time of output. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a disk reproducing apparatus, and more particularly to a disk reproducing apparatus having an output rate conversion function capable of reproducing a disk, such as a digital audio disk, on which a subcode such as time information is recorded together with an audio signal as main information at N times speed operation. The present invention relates to an apparatus and an integrated circuit thereof.

Japanese Patent Application Laid-Open No. Sho 62-150560 discloses a reproducing process for performing N-times speed reproduction and performing intermittent access when the information reading means is accidentally moved by external force or the like during reproduction of a disc. Then, the digital audio data reproduced from the compact disk (CD) is written in the memory, and while the information reading means is moved to a position before the track jump from the time when the track jump occurs, the writing of the reproduction data from the disk is performed in the memory. It is known that the data is stopped and read at a constant period of the sampling frequency. According to this, reproduction data to be converted from digital to analog is not discontinuous, and can be reproduced continuously.

JP-A-62-150560

In the above-mentioned prior art, an abnormal reproduction state such as generation of noise or temporary suspension of reproduction does not occur between the time when the information reading means is accidentally moved and the time when the information reading means returns to the normal position. No consideration was given to data management for the purpose of connection. That is, the subcode of the time information is output at the read timing in order to correspond to the read position of the disk, but the reproduced audio data is temporarily written to the memory to absorb the uneven rotation of the disk, and is read from the crystal oscillator. Since the sub-code and the audio data are read at the timing specified by the clock of the fixed frequency, an accurate one-to-one correspondence cannot be provided.

A first object of the present invention is to solve such a problem and make it possible to always make the reproduced sub-code correspond to the audio data exactly one-to-one. As a result, the data can be converted using the audio data and the sub-code. It is an object of the present invention to provide a disk reproducing apparatus having an output rate conversion function capable of accurately and continuously connecting.

Further, a second object of the present invention is to enable the reproduced sub-code and the audio data to always correspond exactly one to one, so that even if the data is intermittently read from the disk, the audio data can be reproduced. By connecting data accurately and continuously using data and sub-codes, it is not necessary to switch between an equalizer and clock reproduction to obtain an N × speed output and a normal output.

In order to achieve the first object, the present invention provides a method for demodulating the modulated information data and the subcode reproduced from a disc by information reading means and detecting or correcting an error in the information data. Processing means for performing a predetermined process and outputting the information data and the subcode; and a first means for storing the information data or the information data and the subcode obtained by the processing means and outputting the information data Storage means; and first control means for controlling a write / read address of the first storage means, wherein the processing means includes: the information data and the sub-code for absorbing uneven rotation of the disk; And a second control means for controlling a write / read address of the second storage means, wherein the second control means is provided. In the information data, a write / read address is generated and read out so as to perform de-interleaving for returning the interleave performed at the time of recording, and the sub-code is always a specific information data and a specific sub-code. Then, an address is written to and read from the second storage means so that reading is performed in a one-to-one correspondence.

In order to achieve the second object, according to the present invention, the first control means for controlling a write / read address of the first storage means includes the second storage obtained by the processing means. First detecting means for detecting, from the subcode output via the means, an address at which the information data is written to the first storing means, and reading from the first storing means; Second detecting means for detecting second sector information indicating a read address of the information data, and comparing the detected first and second sector information with the first storing means. A third detecting means for detecting an overflow or an underflow of the stored data in the memory, and a third means for prohibiting writing to the first storing means when the third detecting means detects the overflow. Control means, fourth control means for moving the position of the reading means to a next data position using the first sector information at the time of write prohibition, and detecting the underflow by the third detecting means. And a fifth control means for releasing writing prohibition to the first storage means and enabling writing when the first clock means determines a first clock frequency for determining a writing speed to the first storage means. , The writing speed is determined to be N times the normal speed, and the second clock frequency for determining the reading speed to the first storage means is determined to be the normal speed.

By providing the processing means having the second control means, it becomes possible to store and read the sub-code in the second storage means, and the unevenness of rotation of the disk is absorbed for both the sub-code and the information data, The correspondence between the subcode on the disc and the information data can be maintained.

Further, by providing the first control means and the first storage means, it is possible to buffer data reproduced from a disk rotating at N times speed and to continuously read data at a normal speed. .

(4) Further, by dividing into the first integrated circuit and the second integrated circuit, the degree of freedom in system design is increased and development can be achieved. For example, the first integrated circuit can reliably add time information corresponding to continuous audio data on a one-to-one basis, and the second integrated circuit has an integrated circuit for CD-ROM processing that is also used as an integrated circuit dedicated to audio. There is an effect that a system such as a circuit can be developed.

As described above, according to the present invention, even when intermittent access is performed due to a track jump or the like, the time information is added to the data output from the signal processing unit, so that the data connection point can be accurately determined. The output data can be detected and reproduced continuously without discontinuity.

In addition, data is temporarily written to an external RAM and then read, a time difference between write data and read data is detected, an overflow of the RAM is detected, writing to the RAM is prohibited, and a connection point of correct data is detected and picked up. When the underflow is detected, intermittent access is performed to release the write-protection to the RAM and restart the write. Even if the write to the RAM is N times the standard speed and the read is the standard speed, The output data can be reproduced continuously without discontinuity.

Further, even if the time information of the BCD code is used, the write address to the external RAM is generated in a binary number, so that all the RAM addresses can be generated and used effectively.

Furthermore, by separating the integrated circuit for data processing from the integrated circuit for controlling writing / reading to / from the external RAM, the system can be developed not only for CD reproduction but also for CD-ROM and MD.

Hereinafter, embodiments of the present invention will be described with reference to the drawings by taking a compact disc (CD) reproducing apparatus as an example.

FIG. 1 is a block diagram showing an embodiment of a disk reproducing apparatus with an output rate conversion function according to the present invention, wherein 1 is a disk, 2 is a motor, 3 is a pickup servo circuit, 3 'is a motor servo circuit, and 4 is a pickup. 5 is a preamplifier, 8 is a subcode including time information, 13 is access data, 14 is a CD signal processing circuit, 15 is RAM, 16 is address information, 17 is output data, 18 is a time information detecting unit, and 19 is an address. A control circuit, 20 is overflow / underflow information, 21 is a system control microcomputer, 22 and 23 are intermittent access information, 24 is read information, 42 is a read clock, 44 is a read clock generator, 45 is a read clock generator, 46 Is a switching signal, and 61 is a write address generation clock.

The digital signal reproduced from the CD includes the subcode 8 in addition to the audio digital data. In the subcode 8, as shown in FIG. 2, eight channels P to W are allocated to the area immediately after the frame synchronization signal, and the subcode 8 is completed in 98 frames including the subcode synchronization signals S0 and S1. In the Q channel of the subcode 8, time information and control signals are recorded, and an error detection code is added to enable high-reliability reproduction.

In FIG. 1, the disk 1 is rotated at a speed N times the normal speed (normal reproduction) by the motor 2, and data is read from the disk 1 by the pickup 4 controlled by the pickup servo circuit 3. The reproduced data is supplied to the CD signal processing circuit 14 via the preamplifier 5 and the audio data to which the sub-code 8 including the time information is added as the access data 13 is N times the output rate at the standard speed. Is output at the output rate.

The CD signal processing circuit 14 also outputs a write address generation clock 61 and a subcode 8 synchronized with the reproduction data. The write address generation clock 61 is transmitted to the address control circuit 19 together with the access data 13, and the subcode 8 is output to the subcode 8. Each is supplied to the system control microcomputer 21.

The access data 13 having the N-times output rate is written to and read from the RAM 15 controlled by the address control circuit 19. At this time, as the address information 16 of the RAM 15, a write address is generated from the write address generation clock 61 from the CD signal processing circuit 14 by the address control circuit 19, and a read address is generated from the standard speed read clock generation circuit 44. From the read clock 42. Accordingly, in the RAM 15, writing is performed at N times the standard speed, and reading is performed at the standard (1 ×) output rate.

Here, the address control circuit 19 and its peripheral circuits will be described.

The address control circuit 19 generates address information 16 which is a write address and a read address of the RAM 15. If the disk 1 is an audio disk, the system control microcomputer 21 determines from the subcode 8 that the reproduction signal is audio data, selects the standard speed read clock generation circuit 44 by the switching signal 46, and reads the standard speed read clock. The clock is supplied to the address control circuit 19. The address control circuit 19 generates a read address based on the standard speed read clock. Therefore, the access data 13 output from the CD signal processing circuit 14 at an N-fold output rate and written into the RAM 15 is read from the RAM 15 at a standard rate.

By the way, the CD signal processing circuit 14 operates at N times speed, and the timing of writing to the RAM 15 is N times the standard speed, but the timing of reading audio data from the RAM 15 is the standard speed (1 × speed). Before reading all data from the RAM 15, the RAM 15 overflows. Therefore, the address control circuit 19 including the time information detecting section 18 and the system control microcomputer 21 perform write / read control for preventing such overflow.

That is, the time information detecting section 18 of the address control circuit 19 detects the time information at the time of writing based on the access data 13, and uses the information and the disk read information 24 from the system control microcomputer 21 in the RAM 15. The time difference information between the time information at the time of writing and the time information at the time of reading is detected, and based on the detection result of the time difference information, it is monitored whether the RAM 15 overflows or underflows. When detecting that the RAM 15 has overflowed, the address control circuit 19 outputs write information 41 for inhibiting writing to the RAM 15, stops writing to the RAM 15, and supplies the overflow information 20 to the system control microcomputer 21. The system control microcomputer 21 generates the intermittent access information 22 and 23 using the overflow information 20 and the time information at the time of write inhibition, and supplies these to the pickup servo circuit 3 and the motor servo circuit 3 ', respectively. Thus, the pickup servo circuit 3 moves the pickup 4 to the next data position on the disk 1 to be connected.

When detecting that the RAM 15 underflows, the address control circuit 19 outputs the write information 41 for releasing the write prohibition to the RAM 15 and outputs the underflow information 20 for re-accessing the disk 1 to the system control microcomputer 21. I do. As a result, the pickup 4 reads data to be subsequently connected from the disk 1 and writes the data to the RAM 15 again via the CD signal processing circuit 14.

As described above, in this embodiment, the access data 13 output from the CD signal processing circuit 14 at an output rate N times the standard speed is temporarily stored in the RAM 15, and the reading / writing of the RAM 15 is performed such that the reading is performed at the standard speed. , The time difference between the N-fold operation speed of the system and the standard output speed of the output data can be absorbed, and the output data can be reproduced continuously.

Next, the CD signal processing circuit 14 in FIG. 1 will be described with reference to FIG. In FIG. 3, 6 is a demodulation circuit, 7 is audio data, 9 is a data bus, 10 is an address control circuit 2, 11 is a RAM, and 12 is an audio data processing circuit. Reference numerals are given and duplicate description is omitted.

(3) In FIG. 3, the reproduction data supplied from the preamplifier 5 is demodulated by the demodulation circuit 6 and separated into audio data 7 and subcodes 8. The subcode 8 is output from the CD signal processing circuit 14 as it is.

The audio data 7 is written into the RAM 11 through the data bus 9 under the control of the address control circuit 10 in order to absorb jitter due to uneven rotation of the disk 1 and to perform error correction processing and deinterleave processing by the audio data processing circuit 12. It is. At this time, the subcode 8 is also written to the RAM 11 through the data bus 9. The audio data 7 and the subcode 8 written in the RAM 11 are read out from the RAM 11 under the control of the address control circuit 10, and the audio data 7 is interpolated by the audio data processing circuit 12, 8 is added and output from the CD signal processing circuit 14 as access data 13.

{Operation of the address control circuit 10 in FIG. 3 at this time will be described with reference to FIG. In this figure, 25 is a write address generation circuit, 26 is a write address, 27 is a read address generation circuit, 28 is a read address, 29 is an address monitoring circuit, and 30 is an address switching circuit, which corresponds to FIG. Are denoted by the same reference numerals, and redundant description is omitted.

A write address 26 for writing to the RAM 11 is generated by a write address generation circuit 25 from a reproduction system clock synchronized with the reproduction data, and a read address 28 for reading from the RAM 11 is generated from a clock by a crystal oscillator (not shown). Generated by the circuit 27. Conventionally, the subcode 8 is not written in the RAM 11 but is output at the read timing of the disk 1 in order to correspond to the reading position on the disk 1, but in this embodiment, like the audio data 7, the subcode 8 is output. 8 is also written and read from the data bus 9 to the RAM 11. At this time, the write address 26 and the read address 28 are switched by the address switching circuit 30. The address monitoring circuit 29 keeps an interval of ± 4 frames to absorb uneven rotation of the disk 1.

The access data 13 thus obtained by the CD signal processing circuit 14 is supplied to an address control circuit 19 in FIG. 3, and the time information is detected by a time information detecting unit 18 to write the data corresponding to the capacity of the RAM 15 and write the data. To stop. The time information detecting unit 18 detects each time difference information based on the access data 13 and the read information 24 of the disk, and monitors the overflow / underflow of the RAM 15 based on the detection result of the time difference information. While detecting the address of data to be connected next, the overflow / underflow information 20 for re-accessing the disk 1 is output to the system control microcomputer 21.

The operation of the address control circuit 19 at this time will be described with reference to FIG. However, in the figure, 31 is a time information detection circuit, 32 is time information, 33 is a write address generation circuit, 34 is a time information detection circuit, 35 is time information, 36 is a read address generation circuit, 37 is a difference detection circuit, 38 is difference information, 39 is an overflow / underflow detection circuit, 40 is a write control circuit, and 41 is write information.

In the time information detecting section 18, time information is detected by the time information detecting circuit 31 from the access data 13 output from the CD signal processing circuit 14, and based on the disk read information 24 from the system control microcomputer 21. The read address of the RAM 15 generated at the rate of the read clock 42 is generated by the read address generation circuit 36, and the time information 35 at the time of audio output is detected by the time information detection circuit 34 from the read address. The time information 32 detected by the time information detection circuit 31 is supplied to the write address generation circuit 33, and the write address of the RAM 15 is generated at the rate of the write address generation clock 61. The write address and the read address are switched by an address switching circuit 30 ′, and are supplied to the RAM 15 as address information 16.

Further, the difference between the time information 32 detected by the time information detection circuit 31 and the time information 35 generated by the time information detection circuit 34 is detected by the difference detection circuit 37, and the difference information 38 between the write address and the read address of the RAM 15 is detected. Is supplied to the overflow / underflow detection circuit 39. The overflow / underflow detection circuit 39 detects overflow / underflow of the RAM 15 from the difference information 38 and supplies the overflow / underflow information 20 of the RAM 15 to the system control microcomputer 21 of FIG. When the RAM 15 overflows, it outputs write information 41 for prohibiting the writing.

The system control microcomputer 21 outputs intermittent access information 22 and 23 using the overflow / underflow information 20 and the time information 32 at the time of write inhibition, and the pickup servo circuit 3 picks up based on the intermittent access information 22. 4 is moved to the next data position to be connected.

When the overflow / underflow detection circuit 39 detects the underflow of the RAM 15 from the difference information 38, the write control circuit 40 outputs the write information 41 for canceling the write-protection, and the pickup 4 outputs the next write information. Is reproduced from the disk 1, and the reproduced data is written into the RAM 15 again as described above.

As described above, in this embodiment, the time information is added to the audio data output from the CD signal processing circuit 14, so that the connection point of the data can be accurately detected. Therefore, the output data is reproduced continuously.

FIG. 6 is a block diagram showing another embodiment of a disc reproducing apparatus with an output rate conversion function according to the present invention as a CD-ROM reproducing apparatus. Reference numeral 43 denotes a CD-ROM signal processing circuit. The same reference numerals are given to the portions corresponding to No. 3 and the overlapping description will be omitted.

This embodiment is configured to output data at double speed when handling data, based on the value of use as a CD-ROM database. On the other hand, when playing back a CD on which music data is recorded in this embodiment, the signal processing unit operates at a double speed so that output data can be obtained at a standard speed. The CD-ROM is a system for managing data in sector units, and one sector is composed of 98 frames. Therefore, in order to perform standard reproduction of a CD on a CD-ROM, it is necessary to add a signal similar to a sector number to reproduction data of the CD.

Hereinafter, the operation of the embodiment shown in FIG. 6 will be described with reference to FIG.

When the disk 1 is a data disk as a CD-ROM, the system control microcomputer 21 determines that the reproduced signal is the data from the data disk 1 by the subcode 8 from the CD signal processing circuit 14, and The read clock 42 from the double-speed read clock generation circuit 45 is selected so that the output data 17 can be obtained at twice the speed from the RAM 17 as shown in FIG.

If the disk 1 is an audio disk as a CD, the system control microcomputer 21 determines from the subcode 8 that the reproduced signal is audio data, and uses the switching signal 46 to output a read clock generation circuit for the standard speed. The read clock 42 from 44 is selected so that the output data 17 can be obtained from the RAM 15 at a standard speed as shown in FIG. The CD-ROM signal processing system operates at double speed, and the timing of writing the access data 13 to the RAM 15 is twice the standard speed. On the other hand, the timing at which data is read from the RAM 15 is the standard speed, and if it is left as it is, the RAM 15 will overflow before all data is read. In this embodiment, however, the audio data 7 contains time information in units of 98 frames. Is output from the CD signal processing circuit 14 with the addition of the sub-code 8, the data can be managed on a sector-by-sector basis, an accurate connecting point can be detected and a time difference can be detected. The time difference between the standard speed and the output speed of the output data 17 is absorbed.

As described above, in this embodiment, since the access data 13 is added with the sub-code in units of 98 frames, the access data 13 is written in the RAM 15 and the output data is output by the address control circuit 19 of the CD-ROM signal processing circuit 43. By detecting the time difference between the access data 17 and the access data 13, measuring the overflow / underflow of the RAM 15, sending the intermittent access information 22 and 23, and detecting the time again to detect the correct connection point, the writing speed to the external RAM is reduced. Can be adapted to a CD-ROM system in which the reading speed is set to the standard speed by setting N to N times the standard speed, and the circuit can be shared.

The present embodiment is also applicable to a mini disc (MD) system in which data is compressed to one fifth and recorded.

FIG. 8 is a block diagram showing a specific example of the time information detecting circuit 18 shown in FIGS. 1, 3 and 6, wherein 24 'is an address setting clock, 24 "is an address load signal, 47 is a shift register, 48 is an information data latch circuit, 49 is an error detection circuit, 50 is an error detection result, 51 is a Q code register, 52 is time information, 53 is a BCD counter, 54 is a counter value, 55 is a setting address register, and 56 is a BCD counter. , 57 are counter values, 58 is a coincidence detection circuit, 59 is a coincidence detection result, and 60 is a needle jump detection circuit.

First, the operation of this specific example will be described with reference to FIG. 9 assuming that the quadruple speed operation is an example and there is no needle jump.

(4) The set value n from the system control microcomputer 21 is taken into the set address register 55 and loaded into the BCD counter 56. At the same time, the write address counter 33 and the read address counter 36 are reset.

The access data 13 obtained by adding a signal similar to a sector number to the reproduction data of the CD using the subcode 8 is fetched into the shift register 47, and the information data is further stored in the information data latch circuit 48, The Q code is taken into the Q code register 51 and the error detection code is taken into the error detection circuit 49. If the error detection result 50 from the error detection circuit 49 indicates "no error", the time information 52 of the BCD code taken into the Q code register 51 is loaded into the BCD counter 53, and the error detection result 50 If "error" is indicated, the BCD counter 53 counts up by one to the current value.

The count value 54 of the BCD counter 53 and the count value 57 of the set value n of the BCD counter 56 are compared by a coincidence detection circuit 58, and the count value 54 of the BCD counter 53 is sequentially changed by the above operation, and finally the set value If the value matches n, the match detection result 59 of the match detection circuit 58 indicates this, indicating that the data reproduction position has reached the target position of the set value n set by the system control microcomputer 21. Based on the coincidence detection result 59, the BCD counter 56 and the write address generation circuit 33 for generating a write address to the RAM 15 start operating, and count up by one at a timing synchronized with the acquisition of the Q code of the Q code register 51, respectively. I will do it.

The read address counter 36 also starts operating at the same time, and generates a read address in synchronization with the write clock 42.

(4) Since the write address and the read address to the RAM 15 are generated not by BCD but by a binary number, the address of the RAM 15 can be used effectively even if it is generated based on the time information 52 which is a BCD code.

The write address from the write address generation circuit 33 and the read address from the read address counter 36 are supplied to a difference detector 37, and difference information 38 indicating the difference therebetween is obtained. The difference information 38 is supplied to an overflow / underflow detection circuit 39, which detects whether the data stored in the RAM 15 overflows or underflows. In the case of overflow, a pause start signal is output from the overflow / underflow detection circuit 39 to stop writing to the RAM 15, and when an underflow is detected thereafter, a pause release signal is output and writing to the RAM 15 is performed again. Let it start.

Here, in FIG. 9, for simplicity of explanation, the RAM 15 has a capacity of 5 addresses. Therefore, the write address counter 33 also repeats the counting from 0 to 4 of the read address counter 36.

Therefore, in the RAM 15, one piece of information data is read while four pieces of information data are written. Therefore, during the period in which the n-th to (n + 3) -th input information data are sequentially written to the addresses 0 to 3, 1, when the (n + 1) th information data is read out, first, the (n + 4) th input information data is written into the address 4, and then (n + 5) ) -Th input information data is about to be written to address 0. However, when the difference (WR) between the write address and the read address is equal to or more than a value smaller than the number of addresses (capacity) in the RAM 15 by one or more, if the overflow occurs, the (n + 5) -th input information Writing data will overflow. For this reason, a pause start signal is output from the overflow / underflow detection circuit 39 to stop the writing to the RAM 15, and at the same time, the counting operation of the BCD counter 56 and the writing address counter 33 is stopped, and the count value at that time is reduced. Keep it as it is. Thus, the BCD counter 56 holds the count value 57 of the value (n + 5) as it is, and the write address counter 33 holds the address value of the value 0 as it is. However, reading from the RAM 15 is continued as it is.

The system control microcomputer 21 captures the pause start signal as overflow information 20 and generates intermittent access information 22 and 23 using the pause start signal and the time information at the time of write inhibition as described above. And the motor servo circuit 3 '. Thus, the pickup servo circuit 3 moves the pickup 4 to the next data position on the disk 1 to be connected.

(4) During this time, when the RAM 15 is being read, if the RAM 15 underflows, a pause release signal is output from the overflow / underflow detection circuit 39, and the suspension of writing to the RAM 15 is released. Here, it is assumed that an underflow occurs when the difference (WR) between the write address and the read address becomes equal to or less than the number of sectors for one round of the disk 1, and that two sectors are recorded in one round of the disk 1. Then, underflow occurs when (WR) is 2 or less.

Therefore, as described above, the write address W from the write address counter 33 is fixed to 0, so that when the read address R from the read address counter 36 becomes 3, the write address corresponds to 5 which is further ahead. Therefore, the overflow / underflow detection circuit 39 determines that the RAM 15 has underflowed, generates a pause release signal, and starts writing to the RAM 15. Even when the writing is started, the write address W from the write address counter 33 is fixed at 0, and the count value of the BCD counter 56 is fixed at (N + 5). When the (n + 5) th data is reproduced from the disk 1, the count values of the BCD counters 53 and 56 match (n + 1), and a match detection result 59 is output from the match detection circuit 58, and the BCD counter 56 is output. , The write address counter 33 resumes its operation. Therefore, data is written to the RAM 15 in the order of (n + 5) th, (n + 6),... From the address 0 until the next overflow occurs.

(4) In this way, the write operation is surely restarted from the data following the stop of the write operation.

Next, the operation of this specific example will be described with reference to FIG. 10 assuming that the operation is quadruple-speed operation and that there is a needle jump due to vibration. Here, it is assumed that the needle jump occurs after the (n + 9) th data is reproduced, and then the (m) th data is reproduced.

The needle jump detection circuit 60 determines that if there is no error in the reproduction data from the error detection result 50 and there is no predetermined difference (for example, 1) between the time information 52 and 54, discontinuity occurs in the reproduction data due to a needle jump or the like. Then, as in the case of the overflow, the operations of the BCD counter 56 and the write address counter 33 are stopped, and the (n + 10) th data is accessed. Then, when the (n + 10) th data is reproduced, the writing to the RAM 15 is restarted by the match detection result 59 of the match detection circuit 58.

As described above, in this embodiment, even if the Q code of the subcode which is the time information of the BCD code is used, the address generation of the RAM 15 is performed in a binary number, and the standard speed reproduction at the time of the quadruple speed operation is performed by effectively using the RAM 15. It is possible to correspond to. Further, even if a needle jump occurs due to vibration or the like, continuous reproduction can be performed by accurately connecting data.

Also, if the CD signal processing circuit 14 in which the processing of the audio data and the sub-code shown in FIGS. 1 and 3 are made to correspond one-to-one to one integrated circuit, if the audio reproduction only is used, the adlay control shown in FIGS. When the circuit 19 is combined as another integrated circuit, and the ROM data and the audio data are processed by the CD-ROM, the CD-ROM signal processing circuit 43 in FIG. 6 is combined as another integrated circuit. By doing so, it can be deployed to each system.

As described above, in this embodiment, an integrated circuit that associates audio data with time information on a one-to-one basis and an integrated circuit that stores audio data and time information using the corresponding data are separately provided. It is not limited to the example.

The numerical values shown in the above embodiments are merely examples, and the present invention is not limited to these numerical values.

FIG. 1 is a block diagram showing one embodiment of a disk reproducing apparatus with an output rate conversion function according to the present invention. It is a figure showing the subcode format of CD. FIG. 2 is a block diagram illustrating an internal configuration of a CD signal processing circuit in FIG. 1. FIG. 4 is a block diagram illustrating an address control circuit of the CD signal processing circuit in FIG. 3. FIG. 2 is a block diagram illustrating an address control circuit in FIG. 1. FIG. 14 is a block diagram showing another embodiment of a disc reproducing apparatus with an output rate conversion function compatible with a CD-ROM according to the present invention. 7 is a timing chart showing the operation of the embodiment shown in FIG. FIG. 7 is a block diagram illustrating a specific example of a time information detection circuit in FIGS. 1, 3, 5, and 6. 9 is a timing chart showing the standard reproduction timing at the time of the quadruple speed operation in the specific example shown in FIG. 8 without the needle jump. 9 is a timing chart showing the standard reproduction timing at the time of the quadruple speed operation when the specific example shown in FIG.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Disc 4 Pickup 6 Demodulation circuit 8 Subcode 10 Address control circuit 11 RAM
13 access data 14 CD signal processing circuit 15 RAM
16 Address Information 17 Output Data 18 Time Information Detector 19 Control Circuit 20 Overflow / Underflow Information 21 System Control Microcomputer 22, 23 Intermittent Access Information 24 Disk Read Information 39 Overflow / Underflow Detection Circuit 40 Write Control Circuit 41 Write Information 42 Read clock 44 Standard speed read clock generator 45 Double speed read clock generator 53, 56 BCD counter 61 Write address generation clock

Claims (5)

A reproducing apparatus for reproducing, from a disc, a subcode including digitized information data and time information based on a recording start end of the information data,
The reproduction output rate of the digitized information data is a normal output rate, while reproduction processing means for reproducing at N times the normal output rate;
Output rate conversion means for receiving the information data and the subcode reproduced by the reproduction processing means and converting an output rate reproduced at N times into a normal output rate;
Selecting means for selecting an output of the reproducing processing means and an output of the output rate converting means and outputting the selected signal as an output signal of the reproducing apparatus. A disk reproducing unit comprising: a rotating unit for rotating a disk on which digitized and modulated information data and a subcode including a cue signal of the information data and time information are recorded; and an information reading unit for reading information from the disk. In the device,
A process of demodulating the modulated information data and the subcode obtained by the information reading means, performing a predetermined process for detecting or correcting an error in the information data, and outputting the information data and the subcode Means,
A first storage unit that stores the information data obtained by the processing unit, or the information data and the subcode, and outputs the information data;
And first control means for controlling a write / read address of the first storage means.
The processing means includes:
Second storage means for storing the information data and the subcode to absorb rotation irregularities of the disk;
And second control means for controlling a write / read address of the second storage means.
In the second control means, the information data generates a write / read address so as to perform deinterleaving for restoring the interleave performed at the time of recording and is read, and the subcode always has a specific information. A disk reproducing device with an output rate conversion function, wherein an address is written to and read from the second storage means so that data and a specific subcode are read in a one-to-one correspondence. In paragraph 2,
The first control means for controlling a write / read address of the first storage means,
A first detection for detecting, from the subcode output from the second storage unit obtained from the processing unit, first sector information indicating an address at which the information data is written to the first storage unit; Means,
Second detecting means for detecting second sector information indicating a read address of the information data read from the first storage means;
Third detection means for comparing the detected first sector information and second sector information to detect overflow or underflow of data stored in the first storage means;
Third control means for prohibiting writing to the first storage means when the third detection means detects an overflow;
Fourth control means for moving the reading position of the reading means on the disk to a next data position by using the first sector information at the time of the write inhibition,
And a fifth control means for releasing writing prohibition to the first storage means and enabling writing when the third detection means detects an underflow,
A first clock frequency for determining a writing speed to the first storage means is determined so that the writing speed is N times a normal speed, and a first clock frequency for determining a reading speed to the first storage means is determined. 2. A disk reproducing apparatus having an output rate conversion function, wherein the clock frequency of the second is determined to be a normal speed. In claim 2,
The sub-code is obtained by adding an error detection code to the time information of a binary-coded decimal (BCD) code,
Having system control means for setting a reproduction start position of the disc,
The first control means for controlling a write / read address of the first storage means,
An error detection circuit for detecting an error in the reproduction data from an error detection code of the reproduction data of the disc;
A first BCD counting circuit that counts the time information in a binary-coded decimal system by looking at an error code of the detected reproduced data;
A second BCD counting circuit for counting the address of the reproduction start position set by the system control means in a binary-coded decimal system;
A match detecting circuit for detecting a match between a first address by the first BCD counting circuit and a second address by the second BCD counting circuit;
When the match detection circuit detects a match between the first and second addresses, a write / read address of the first storage means is generated in a binary system, and write / read control is performed. Disk playback device with rate conversion function. A disk comprising: a rotating means for rotating a disk on which sub-codes including digitized and modulated information data and a cue signal of the information data and time information are recorded; and information reading means for reading information from the disk. A reproducing apparatus, wherein the integrated circuit is connected to the information reading means, processes an output of the information reading means and outputs information data,
A process of demodulating the modulated information data and the subcode obtained by the information reading means, performing a predetermined process for detecting or correcting an error in the information data, and outputting the information data and the subcode A first integrated circuit including means;
A first storage unit that stores the information data obtained by the processing unit, or the information data and the subcode, and outputs the information data;
And a second integrated circuit including first control means for controlling a write / read address of the first storage means.
The processing means includes:
Second storage means for storing the information data and the subcode to absorb rotation irregularities of the disk;
Second control means for controlling a write / read address of the second storage means,
In the second control means, the information data generates a write / read address so as to perform deinterleaving for restoring the interleave performed at the time of recording and is read, and the subcode always has a specific information. An integrated circuit of a disk reproducing apparatus with an output rate conversion function, wherein an address is written to and read from said second storage means so that data and a specific subcode are read one-to-one.

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