JP2000149446A - Disk reproducing device and its integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cope with not only an intermittent access owing to track jumping in a conventional CD reproducing system but also standard speed reproduction at the time of operation at a N times speed. SOLUTION: This device is provided with a memory 11 in which data reproduced from a disk 1 and correspondent temporal information are written together, and, further, an outer memory 15. In this case, the time difference between data 17 finally outputted and data 13 during access is detected by a temporal information detecting circuit 18 in an address control circuit 19, an overflow and an underflow of the outer memory 15 are detected, the writing in the outer memory 15 is controlled based on this detected result, even when an intermittent access is performed by controlling a pickup 4, the time different between system operation speed and data output speed is absorbed, and continuous data 17 being coupled normally are obtained at the time of output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk reproducing apparatus, and more particularly, to a disk in which a subcode such as time information is recorded together with an audio signal as main information, such as a digital audio disk, at N times speed operation. The present invention relates to a disk reproducing apparatus having an output rate conversion function and an integrated circuit thereof.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. Sho 62-150560 discloses a reproduction process in which N-times speed reproduction is performed, and intermittent access is performed when an information reading means is accidentally moved by an external force or the like during reproduction of a disc. As disclosed in Japanese Patent Application Laid-Open No. H11-284, while digital audio data reproduced from a compact disk (CD) is written into a memory and the information reading means is moved to a position before the track jump from the time when the track jump occurs, the data is read from the disk by the memory. There is known a technique in which writing of reproduction data is stopped and reading is performed at a constant period of a sampling frequency. According to this, reproduction data to be converted from digital to analog is not discontinuous, and can be reproduced continuously.

[0003]

In the above-mentioned prior art, an abnormal reproduction state such as generation of noise or a temporary suspension of reproduction may occur during a period from when the information reading means is accidentally moved to when it returns to a normal position. However, no consideration was given to data management for accurately and continuously connecting reproduced data. That is, the sub-code of the time information is output at the read timing in order to correspond to the read position of the disk, but the reproduced audio data is once written to the memory to absorb the uneven rotation of the disk, and is read from the crystal oscillator. Since the sub-code and the audio data are read at the timing specified by the clock of the constant frequency, an accurate one-to-one correspondence cannot be provided.

[0004] A first object of the present invention is to solve such a problem and to make it possible to always accurately and one-to-one correspondence between reproduced sub-codes and audio data. As a result, it is possible to use such audio data and sub-codes. Another object of the present invention is to provide a disk reproducing apparatus having an output rate conversion function capable of connecting data accurately and continuously.

A second object of the present invention is to enable the reproduced sub-code and the audio data to always correspond exactly one-to-one, so that even if data is intermittently read from the disk. Another object of the present invention is to eliminate the need for switching between an equalizer and a clock to obtain an N-times output and a normal output by accurately and continuously connecting data using such audio data and subcodes.

[0006]

In order to achieve the first object, the present invention demodulates the modulated information data and the subcode reproduced from a disk by information reading means, Performing predetermined processing for detecting or correcting the error of the information, outputting the information data and the subcode, and storing the information data obtained by the processing means, or the information data and the subcode. A first storage unit for outputting information data, and a first control unit for controlling a write / read address of the first storage unit, wherein the processing unit absorbs rotation unevenness of the disk. A second storage means for storing the information data and the subcode, and a second control means for controlling a write / read address of the second storage means. At a, the second control means,
The information data is written / written so as to perform deinterleaving to restore the interleaving performed at the time of recording.
A read address is generated and read, and the sub-code is written to and read from the second storage means such that the specific information data and the specific sub-code are always read one-to-one. Generate.

In order to achieve the second object,
According to the present invention, the first control means for controlling a write / read address of the first storage means reads the information from the subcode output via the second storage means obtained from the processing means. First detection means for detecting first sector information indicating an address at which data is written to the first storage means, and second sector indicating a read address of the information data read from the first storage means A second detecting means for detecting information; and a second detecting means for comparing the detected first sector information with the second sector information to detect overflow or underflow of data stored in the first storage means. (3) detecting means, third control means for prohibiting writing to the first storage means when the third detecting means detects an overflow, and first control means for prohibiting writing to the first storage means. Fourth control means for moving the position of the reading means to a data position to be connected to next using the sensor information, and writing inhibition to the first storage means when the third detecting means detects an underflow. And a fifth control means for enabling writing by setting the first clock frequency for determining the writing speed to the first storage means such that the writing speed is N times the normal speed. And the second clock frequency for determining the reading speed to the first storage means is determined to be the normal speed.

As described above, the provision of the processing means having the second control means makes it possible to store and read out the sub-code in the second storage means, and both the sub-code and the information data are stored on the disk. Rotational unevenness is absorbed, and the correspondence between the subcode and the information data on the disc can be maintained.

In addition, by providing the first control means and the first storage means, the data reproduced from the disk rotating at N times speed is buffered and the data is continuously read at the normal speed. be able to.

[0010] Further, the division into the first integrated circuit and the second integrated circuit increases the degree of freedom in system design and allows development. For example, the first integrated circuit can reliably add time information corresponding to continuous audio data on a one-to-one basis, and the second integrated circuit has an integrated circuit for CD-ROM processing that is also used as an integrated circuit dedicated to audio. There is an effect that a system such as a circuit can be developed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking a compact disc (CD) reproducing apparatus as an example.

FIG. 1 is a block diagram showing an embodiment of a disk reproducing apparatus having an output rate conversion function according to the present invention, wherein 1 is a disk, 2 is a motor, 3 is a pickup servo circuit, and 3 'is a motor servo circuit. 4 is a pickup, 5 is a preamplifier, 8 is a subcode including time information,
13 is access data, 14 is a CD signal processing circuit, 15
Is RAM, 16 is address information, 17 is output data, 1
8 is a time information detector, 19 is an address control circuit, 20 is overflow / underflow information, 21 is a system control microcomputer, 22 and 23 are intermittent access information, 24 is read information, 42 is a read clock, and 44 is a read clock generator. Circuit, 45 is a read clock generation circuit, 46 is a switching signal, and 61 is a write address generation clock.

Digital signals reproduced from a CD include:
A subcode 8 is included in addition to the audio digital data. In the subcode 8, as shown in FIG. 2, eight channels P to W are allocated to the area immediately after the frame synchronization signal, and the subcode 8 is completed in 98 frames including the subcode synchronization signals S0 and S1. In the Q channel of the subcode 8, time information and control signals are recorded, and an error detection code is added to enable high-reliability reproduction.

In FIG. 1, the disk 1 is rotated at N times the speed of a standard speed (normal reproduction) by a motor 2, and data is read from the disk 1 by a pickup 4 controlled by a pickup servo circuit 3. The reproduced data is supplied to the CD signal processing circuit 14 via the preamplifier 5, and the processed audio data to which the sub-code 8 including the time information is added is used as the access data 13 as N times the output rate at the standard speed. Output at the output rate.

The CD signal processing circuit 14 outputs a write address generation clock 61 and a subcode 8 in synchronization with the reproduction data. The write address generation clock 61 is transmitted to the address control circuit 19 together with the access data 13 by the subaddress 8. The codes 8 are supplied to the system control microcomputer 21 respectively.

The access data 13 having the N-times output rate is supplied to the RA controlled by the address control circuit 19.
It is written to and read from M15. RAM at this time
15 as address information 16, an address control circuit 19
Thus, the write address is generated from the write address generation clock 61 from the CD signal processing circuit 14, and the read address is generated from the read clock 42 from the standard speed read clock generation circuit 44. Therefore, in the RAM 15, writing is performed at N times the standard speed and reading is performed at the standard (1 ×) output rate.

Here, the address control circuit 19 and its peripheral circuits will be described.

In the address control circuit 19, address information 1 which is a write address / read address of the RAM 15 is stored.
6 is generated. When the disk 1 is an audio disk, the system control microcomputer 21 determines from the subcode 8 that the reproduced signal is audio data, selects the standard speed read clock generation circuit 44 by the switching signal 46, and reads the standard speed read clock. The clock is supplied to the address control circuit 19. The address control circuit 19 generates a read address based on the standard speed read clock. Therefore, the access data 13 output from the CD signal processing circuit 14 at an N-fold output rate and written into the RAM 15 is read from the RAM 15 at a standard rate.

The CD signal processing circuit 14 operates at N times speed, and the timing of writing to the RAM 15 is N times normal speed.
Although the speed is twice as fast, the timing for reading the audio data from the RAM 15 is the standard speed (1 × speed).
5 overflows. Therefore, the address control circuit 19 including the time information detecting section 18 and the system control microcomputer 21 perform write / read control for preventing such overflow.

That is, the time information detecting section 18 of the address control circuit 19 detects the time information at the time of writing based on the access data 13.
RAM 1 using the disk read information 24 from
5, the time difference information between the time information at the time of writing and the time information at the time of reading is detected, and based on the detection result of the time difference information, it is monitored whether the RAM 15 overflows or underflows. And the address control circuit 1
9 detects that the RAM 15 has overflowed, outputs write information 41 for inhibiting writing to the RAM 15, stops writing to the RAM 15, and supplies overflow information 20 to the system control microcomputer 21. The system control microcomputer 21 uses the overflow information 20
And the intermittent access information 22 and 23 are generated using the time information at the time of the write prohibition and are supplied to the pickup servo circuit 3 and the motor servo circuit 3 ', respectively. As a result, the pickup servo circuit 3 moves the pickup 4 to the next data position on the disk 1 to be connected.

When detecting that the RAM 15 underflows, the address control circuit 19 outputs write information 41 for canceling the write-protection to the RAM 15, and
Underflow information 20 for re-accessing the system is output to the system control microcomputer 21. As a result, the pickup 4 reads data to be subsequently connected from the disk 1 and writes the data to the RAM 15 again via the CD signal processing circuit 14.

As described above, in this embodiment, the access data 13 output from the CD signal processing circuit 14 at an output rate N times the standard speed is temporarily stored in the RAM 15 and read out from the RAM 15 so that reading is performed at the standard speed. By controlling the writing / reading, the time difference between the N-times operating speed of the system and the standard output speed of the output data can be absorbed,
Output data can be reproduced continuously.

Next, the CD signal processing circuit 14 in FIG. 1 will be described with reference to FIG. However, in FIG.
6 is a demodulation circuit, 7 is audio data, 9 is a data bus, 10
, Address control circuits 2 and 11 are RAMs, and 12 is an audio data processing circuit. The parts corresponding to those in FIG.

In FIG. 3, reproduction data supplied from a preamplifier 5 is demodulated by a demodulation circuit 6 and separated into audio data 7 and a subcode 8. The subcode 8 is output from the CD signal processing circuit 14 as it is.

The audio data 7 passes through the data bus 9 under the control of the address control circuit 10 in order to absorb jitter due to uneven rotation of the disk 1 and to perform error correction processing and deinterleave processing by the audio data processing circuit 12. RAM
11 is written. At this time, the subcode 8 is also written to the RAM 11 through the data bus 9. RAM11
The audio data 7 and the sub-code 8 written in the sub-code 8 are read out from the RAM 11 under the control of the address control circuit 10, and the audio data 7 is interpolated by the audio data processing circuit 12, and then the sub-code 8 Are output from the CD signal processing circuit 14 as access data 13.

At this time, the address control circuit 10 in FIG.
Will be described with reference to FIG. However, in the figure,
25 is a write address generation circuit, 26 is a write address, 27 is a read address generation circuit, 28 is a read address, 29 is an address monitoring circuit, 30 is an address switching circuit, and portions corresponding to those in FIG. And a duplicate description will be omitted.

A write address 26 for writing to the RAM 11 is generated by a write address generation circuit 25 from a reproduction system clock synchronized with the reproduction data.
A read address 28 for reading from 1 is generated by a read address generation circuit 27 from a clock by a crystal oscillator (not shown). Conventionally, the subcode 8 is stored in the RAM 11 in order to correspond to the reading position on the disk 1.
The subcode 8 is not written to the disk 1 but is output at the read timing of the disk 1. In this embodiment, however, the subcode 8 is also written and read from the data bus 9 to the RAM 11 in the same manner as the audio data 7. At this time, the write address 2
6 and the read address 28 are switched by the address switching circuit 30. Further, the address monitoring circuit 29
The intervals between the frames are maintained to absorb uneven rotation of the disk 1.

The access data 13 thus obtained by the CD signal processing circuit 14 is supplied to an address control circuit 19 in FIG. 3, and the time information detecting section 18 detects the time information, and writes the time information by the capacity of the RAM 15; , Stop the writing. The time information detecting section 18 detects each time difference information based on the access data 13 and the read information 24 of the disk, and monitors the overflow / underflow of the RAM 15 based on the detection result of the time difference information. While detecting the address of the data to be connected next, the overflow / underflow information 20 for re-accessing the disk 1 is output to the system control microcomputer 21.

The operation of the address control circuit 19 at this time will be described with reference to FIG. However, in the figure, 31 is a time information detection circuit, 32 is time information, 33 is a write address generation circuit, 34 is a time information detection circuit, 35 is time information, 36 is a read address generation circuit, 37 is a difference detection circuit, 38 is difference information, 39 is an overflow / underflow detection circuit, 40 is a write control circuit, and 41 is write information.

In the time information detecting section 18, the time information detecting circuit 31 detects time information from the access data 13 output from the CD signal processing circuit 14, and reads the disk read information 24 from the system control microcomputer 21.
Generated at the rate of read clock 42 based on
The read address of M15 is read address generation circuit 36.
The time information 35 at the time of audio output is detected by the time information detection circuit 34 from the read address. The time information 32 detected by the time information detection circuit 31 is supplied to the write address generation circuit 33, and the write address of the RAM 15 is generated at the rate of the write address generation clock 61. The write address and the read address are switched by the address switching circuit 30 ′, and are supplied to the RAM 15 as address information 16.

Further, a difference between the time information 32 detected by the time information detection circuit 31 and the time information 35 generated by the time information detection circuit 34 is detected by a difference detection circuit 37, and R
Overflow / underflow detection circuit 3 as difference information 38 between write address and read address of AM 15
9. The overflow / underflow detection circuit 39 detects the overflow / underflow of the RAM 15 from the difference information 38 and generates the overflow / underflow information 20 of the RAM 15 as shown in FIG.
Is supplied to a write control circuit 40, and outputs write information 41 for prohibiting writing when the RAM 15 overflows.

The system control microcomputer 21 uses the overflow / underflow information 20 and the time information 32 at the time of write prohibition to make the intermittent access information 22, 23.
The pickup servo circuit 3 moves the pickup 4 to the next data position to be connected based on the intermittent access information 22.

When the overflow / underflow detection circuit 39 detects the underflow of the RAM 15 from the difference information 38, the write control circuit 40 outputs the write information 41 for canceling the write prohibition, 4 reproduces the data to be subsequently connected from the disk 1 and causes the reproduced data to be written into the RAM 15 again as described above.

As described above, in this embodiment, since the time information is added to the audio data output from the CD signal processing circuit 14, the connection point of the data can be accurately detected. In order to perform the time difference absorption, the output data is continuously reproduced.

FIG. 6 is a block diagram showing another embodiment of a disc reproducing apparatus with an output rate conversion function according to the present invention as a CD-ROM reproducing apparatus.
-A ROM signal processing circuit, and portions corresponding to FIGS. 1 and 3 are denoted by the same reference numerals, and redundant description will be omitted.

This embodiment is configured to output data at double speed when handling data, based on the value of use as a database of a CD-ROM. On the other hand, when playing back a CD on which music data is recorded in this embodiment, the signal processing section performs a double speed operation so that output data can be obtained at a standard speed. Also, CD-
The ROM is a system for managing data in sector units, and one sector is composed of 98 frames. So, C
In order to perform standard reproduction of a CD with a D-ROM, it is necessary to add a signal similar to a sector number to reproduction data of the CD.

The operation of the embodiment shown in FIG. 6 will be described below with reference to FIG.

When the disk 1 is a data disk as a CD-ROM, the system control microcomputer 21
The sub-code 8 from the signal processing circuit 14 determines that the reproduced signal is data from the data disk 1, and the switching signal 46 causes the double-speed read clock generation circuit 4
5 is selected so that the output data 17 can be obtained from the RAM 15 at a double speed as shown in FIG.

When the disk 1 is an audio disk as a CD, the system control microcomputer 21 determines that the reproduced signal is audio data based on the subcode 8 and, based on the switching signal 46, reads the signal for the standard speed. The read clock 42 from the clock generation circuit 44 is selected, and FIG.
As shown in (b), the output data 17 is obtained from the RAM 15 at a standard speed. The CD-ROM signal processing system operates at twice the speed, and the timing of writing the access data 13 to the RAM 15 is twice the standard speed. On the other hand, the timing at which data is read from the RAM 15 is the standard speed, and if the data is read as it is, the RAM 15 will overflow before all the data is read. Since the sub-code 8 is added and output from the CD signal processing circuit 14, the data can be managed on a sector-by-sector basis, an accurate connection point is detected and a time difference is detected. The time difference between the standard speed and the output speed of the output data 17 is absorbed.

As described above, in this embodiment, since the access data 13 is added with the sub-code in the unit of 98 frames, the access data 13 is written into the RAM 15 and the address control circuit 19 of the CD-ROM signal processing circuit 43 is written. To detect the time difference between the output data 17 and the access data 13, measure the overflow / underflow of the RAM 15, send the intermittent access information 22, 23, detect the time again, and detect the correct connection point, so that the external RAM can be detected. Can be applied to a CD-ROM system in which the writing speed is set to N times the standard speed and the reading speed is set to the standard speed, and the circuit can be shared.

This embodiment is also applicable to a mini-disc (MD) system in which data is compressed to one-fifth and recorded.

FIG. 8 is a block diagram showing a specific example of the time information detecting circuit 18 shown in FIGS.
Is an address setting clock, 24 "is an address load signal, 47 is a shift register, 48 is an information data latch circuit, 49 is an error detection circuit, 50 is an error detection result, 51 is a Q code register, 52 is time information, and 53 is time information. A BCD counter, 54 is a counter value, 55 is a setting address register, 56 is a BCD counter, 57 is a counter value, 58 is a match detection circuit, 59 is a match detection result, and 60 is a needle jump detection circuit.

First, the operation of this specific example will be described with reference to FIG. 9 assuming that the operation is quadruple-speed operation and that there is no needle jump.

Set value n from system control microcomputer 21
Is loaded into the setting address register 55 and loaded into the BCD counter 56. At the same time, the write address counter 33 and the read address counter 36 are reset.

The access data 13 obtained by adding a signal similar to a sector number to the reproduction data of the CD using the subcode 8 is fetched into the shift register 47.
The information data is taken into the information data latch circuit 48, the Q code of the subcode 8 is taken into the Q code register 51, and the error detection code is taken into the error detection circuit 49, respectively. If the error detection result 50 from the error detection circuit 49 indicates “no error”, the time information 52 of the BCD code taken into the Q code register 51 is loaded into the BCD counter 53, and the error detection result 50 "Incorrect"
, The BCD counter 53 increments the current value by one.
Just count up.

The count value 54 of the BCD counter 53 and B
The coincidence detection circuit 58 compares the count value 57 of the set value n of the CD counter 56 with the count value 57.
When the count value 54 of the D counter 53 sequentially changes and finally coincides with the set value n, the coincidence detection result 59 of the coincidence detection circuit 58 indicates this, and the data reproduction position is the same as the set value n set by the system control microcomputer 21. The target position has been reached. Based on the coincidence detection result 59, the BCD counter 56 and the write address generation circuit 33 for generating a write address to the RAM 15 start operating, and count up by one at a timing synchronized with the acquisition of the Q code of the Q code register 51, respectively. I will do it.

The read address counter 36 also starts operating at the same time, and generates a read address in synchronization with the write clock 42.

Since the write address and the read address to the RAM 15 are generated not by BCD but by binary numbers,
Even if it is generated based on the time information 52 which is a BCD code,
The address of the RAM 15 can be used effectively.

The write address from the write address generation circuit 33 and the read address from the read address counter 36 are supplied to a difference detector 37, and difference information 38 indicating the difference is obtained. This difference information 38 is supplied to an overflow / underflow detection circuit 39,
Whether the data stored in the AM 15 overflows or underflows is detected. In the case of overflow, a pause start signal is output from the overflow / underflow detection circuit 39 to stop writing to the RAM 15, and when an underflow is detected thereafter, a pause release signal is output and writing to the RAM 15 is performed again. Let it start.

Here, in FIG. 9, for simplicity of explanation, the capacity of the RAM 15 is set to a capacity of 5 addresses.
Therefore, the write address counter 33 also repeats the count from 0 to 4 of the read address counter 36.

Therefore, in the RAM 15, one piece of information data is read while four pieces of information data are written, so that the n-th to (n + 3) -th input information data are sequentially written to addresses 0 to 3. During the period, the n-th information data of address 1 is read, and then (n +
When the 1) th information data is read, first,
The (n + 4) th input information data is written to address 4, and then the (n + 5) th input information data is written to address 0. However, here, the difference (WR) between the write address and the read address indicates that the RAM 1
If the number of addresses is smaller than the number of addresses (capacity) by one by one or more, and if an overflow occurs, the writing of the (n + 5) th input information data will overflow. Therefore, a pause start signal is output from the overflow / underflow detection circuit 39 and the RAM 1
5 is stopped, and at the same time, the counting operation of the BCD counter 56 and the write address counter 33 is stopped, and the count value at that time is held as it is. Thus, the BCD counter 56 holds the count value 57 of the value (n + 5) as it is, and the write address counter 33 holds the address value of the value 0 as it is. However, reading from the RAM 15 is continued as it is.

The system control microcomputer 21 captures this pause start signal as overflow information 20 and
As described above, the intermittent access information 22 and 23 are generated by using this and the time information at the time of write prohibition, and these are supplied to the pickup servo circuit 3 and the motor servo circuit 3 ', respectively. As a result, the pickup servo circuit 3 moves the pickup 4 to the next data position on the disk 1 to be connected.

During the reading of the RAM 15 during this time, when the RAM 15 underflows, a pause release signal is output from the overflow / underflow detection circuit 39, and the stop of writing to the RAM 15 is released. Here, it is assumed that an underflow occurs when the difference (WR) between the write address and the read address becomes equal to or less than the number of sectors for one round of the disk 1, and that two sectors are recorded in one round of the disk 1. Then, (W-
When R) is 2 or less, underflow has occurred.

Therefore, as described above, the write address W from the write address counter 33 is fixed to 0, so that when the read address R from the read address counter 36 becomes 3, the write address is advanced by 5 The overflow / underflow detection circuit 39 determines that the RAM 15 has underflowed, generates a pause release signal, and starts writing to the RAM 15. Even when the writing is started, the write address W from the write address counter 33 is fixed at 0, and the count value of the BCD counter 56 is fixed at (N + 5). When the (n + 5) th data is reproduced from the disc 1, the count values of the BCD counters 53 and 56 match (n + 1), and a match detection result 59 is output from the match detection circuit 58 to output the BCD
The counter 56 and the write address counter 33 resume operation. Therefore, the RAM 15 stores addresses 0 to (n
Data is written in the order of (+5) th, (n + 6),... Until the next overflow occurs.

In this way, the write operation is surely restarted from the next data after the stop of the write operation.

Next, the operation of this specific example will be described with reference to FIG. 10 assuming that the operation is quadruple-speed operation and that there is a needle jump due to vibration. Here, (n + 9)
It is assumed that the needle jump occurs after the data of the (m) th is reproduced, and then the data of the (m) th is reproduced.

The needle jump detection circuit 60 calculates the error detection result 50
No error is found in the reproduction data and the time information 52, 54
If there is no predetermined difference (e.g., 1) between them, it is determined that discontinuity has occurred in the reproduced data due to a stitch, etc., and the operations of the BCD counter 56 and the write address counter 33 are stopped as in the case of the overflow described above. And (n + 1
And 0) -th data is accessed. And
When the (n + 10) th data is reproduced, the writing to the RAM 15 is restarted by the match detection result 59 of the match detection circuit 58.

As described above, in this embodiment, even if the Q code of the subcode which is the time information of the BCD code is used, the address generation of the RAM 15 is performed in a binary number, and
It is possible to cope with standard speed reproduction at the time of quadruple speed operation by effectively using M15. Also, even if the needle jumps due to vibration etc.,
It is possible to perform continuous reproduction by accurately connecting data.

Further, if the CD signal processing circuit 14 in which the processing of the audio data and the subcode shown in FIGS. 1 and 3 are made to correspond one-to-one is one integrated circuit,
The address control circuit 19 shown in FIG. 1 and FIG. 3 is combined as another integrated circuit.
When processing data and audio data, the CD-
By combining and configuring the ROM signal processing circuit 43 as another integrated circuit, it can be applied to each system.

As described above, in this embodiment, an integrated circuit that associates audio data with time information on a one-to-one basis and an integrated circuit that stores audio data and time information using the corresponding data are separated. The present invention is not limited to the embodiment of reproduction.

It should be noted that the numerical values shown in the above embodiments are merely examples, and the present invention is not limited to these.

[0062]

As described above, according to the present invention,
Even in the case of intermittent access due to a track jump or the like, since the time information is added to the data output from the signal processing unit, the connection point of the data can be accurately detected,
The output data can be reproduced continuously without discontinuity.

Further, the data is once written to the external RAM and then read, the time difference between the write data and the read data is detected, and the RAM overflow is detected by detecting the RAM overflow.
When the underflow is detected by detecting the connection point of the correct data and detecting the underflow, intermittent access to release the write prohibition to the RAM and restart the write is performed, and the write to the RAM is stopped. Even when the reading is performed at the standard speed at N times the standard speed, the output data can be reproduced continuously without discontinuity.

Further, even if the time information of the BCD code is used, since the write address to the external RAM is generated in a binary number, all the RAM addresses can be generated and used effectively.

Further, an integrated circuit for data processing;
Separating the integrated circuit for controlling writing / reading to / from the external RAM is not limited to CD playback, but also to CD-ROM and M-ROM.
D and the like can be developed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a disk reproducing apparatus according to the present invention.

FIG. 2 is a diagram showing a subcode format of a CD.

FIG. 3 is a block diagram showing an internal configuration of a CD signal processing circuit in FIG. 1;

FIG. 4 is a block diagram showing an address control circuit of the CD signal processing circuit in FIG. 3;

FIG. 5 is a block diagram showing an address control circuit in FIG. 1;

FIG. 6 is a block diagram showing another embodiment of a CD-ROM compatible disk reproducing apparatus according to the present invention.

FIG. 7 is a timing chart showing the operation of the embodiment shown in FIG.

FIG. 8 is a block diagram showing a specific example of a time information detection circuit in FIGS. 1, 3, 5, and 6;

9 is a timing chart showing the standard reproduction timing at the time of the quadruple speed operation in the specific example shown in FIG. 8 without the needle jump.

FIG. 10 is a timing chart showing the standard reproduction timing at the time of the quadruple speed operation when the specific example shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Disc 4 Pickup 6 Demodulation circuit 8 Subcode 10 Address control circuit 11 RAM 13 Access data 14 CD signal processing circuit 15 RAM 16 Address information 17 Output data 18 Time information detection unit 19 Control circuit 20 Overflow / underflow information 21 System control microcomputer 22, 23 Intermittent access information 24 Disk read information 39 Overflow / underflow detection circuit 40 Write control circuit 41 Write information 42 Read clock 44 Standard speed read clock generation circuit 45 Double speed read clock generation circuit 53, 56 BCD counter 61 Write address Generation clock

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshifumi Takeuchi 292 Yoshidacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Video Media Research Laboratory, Hitachi, Ltd. No. 1 Inside Semiconductor Design & Development Center, Hitachi, Ltd.

Claims (5)

[Claims] 1. A reproducing apparatus for reproducing, from a disk, digitized information data and a subcode including time information based on a recording start end of the information data from a disk, a reproduction output rate of the digitized information data is as follows. A reproduction processing means for reproducing at N times the normal output rate, and the information data and the subcode reproduced by the reproduction processing means as inputs, and an output rate reproduced at N times as normal. A disc reproducing apparatus comprising: an output rate converting means for converting an output rate into an output rate; and a selecting means for selecting an output of the reproducing processing means and an output of the output rate converting means and outputting the output signal of the reproducing apparatus. 2. A rotating means for rotating a disc on which digitized and modulated information data and a subcode including a cue signal of the information data and time information are recorded, and an information reading means for reading information from the disc. And demodulating the modulated information data and the subcode obtained by the information reading means, and performing a predetermined process for detecting or correcting an error in the information data. Processing means for outputting the sub-code; first storage means for storing the information data obtained by the processing means, or the information data and the sub-code, and outputting information data; and the first storage First control means for controlling a write / read address of the means, wherein the processing means comprises: A second storage unit that stores the information data and the subcode, and a second control unit that controls a write / read address of the second storage unit, in order to absorb unevenness; In the control means (2), the information data is read / written by generating a write / read address so as to perform deinterleaving for returning the interleave performed at the time of recording, and the subcode always includes the specific information data. A disk reproducing apparatus for generating an address for writing and reading data in and from the second storage means so that reading is performed in a one-to-one correspondence with a specific subcode. 3. The apparatus according to claim 2, wherein said first control means for controlling a write / read address of said first storage means outputs said data via said second storage means obtained from said processing means. First detection means for detecting, from the subcode, first sector information indicating an address at which the information data is written to the first storage means; and a read address of the information data read from the first storage means A second detecting means for detecting second sector information indicating the first and second sector information, and comparing the detected first and second sector information with each other to detect overflow or overflow of data stored in the first storing means. Third detection means for detecting an underflow, third control means for inhibiting writing to the first storage means when the third detection means detects an overflow, Fourth control means for moving the reading position of the reading means on the disk to the next data position using the first sector information at the time of write inhibition, and the third detecting means detects an underflow And a fifth control means for releasing the write-protection to the first storage means and enabling the writing when the first clock means, and a first clock frequency for determining a writing speed to the first storage means. Is determined so that the writing speed is N times the normal speed, and the second clock frequency for determining the reading speed to the first storage means is determined to be the normal speed. Disc playback device. 4. The system control means according to claim 2, wherein said sub-code is obtained by adding an error detection code to said time information of a binary-coded decimal (BCD) code, and setting a reproduction start position of said disc. An error detection circuit for detecting an error in the reproduction data from an error detection code of the reproduction data of the disk, the first control means controlling a write / read address of the first storage means; A first BCD counting circuit that counts the time information in a binary-coded decimal system by looking at the error code of the reproduced data that has been read out, and converts the address of the reproduction start position set by the system control unit into a binary-coded decimal system. The second B counting with
A CD counting circuit; and a match detecting circuit for detecting a match between a first address by the first BCD counting circuit and a second address by the second BCD counting circuit. 1. A disc reproducing apparatus characterized in that upon detecting coincidence of a second address, a write / read address of the first storage means is generated in a binary system, and write / read control is performed. 5. A rotating means for rotating a disk on which digitized and modulated information data and a subcode including a cue signal of the information data and time information are recorded, and information reading for reading information from the disk. Means for processing the output of said information reading means and outputting information data, wherein said modulated information data obtained by said information reading means and Demodulate the sub-code, perform a predetermined process to detect or correct the error of the information data,
A first integrated circuit including a processing unit that outputs the information data and the subcode; and a second integrated circuit that stores the information data obtained by the processing unit or the information data and the subcode and outputs the information data. 1 storage means, and a second integrated circuit including a first control means for controlling a write / read address of the first storage means, wherein the processing means is provided for absorbing uneven rotation of the disk. And a second storage means for storing the information data and the subcode, and a second control means for controlling a write / read address of the second storage means. The information data is generated and read out of a write / read address so as to perform deinterleaving for restoring the interleave performed at the time of recording, and is read out. Generating an address to be written to and read from the second storage means such that reading is always performed so that specific information data and specific subcode have a one-to-one correspondence. .