JP3302737B2 - Disc reproducing apparatus and signal processing circuit thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for reproducing an optical disk such as a CD (compact disk) and, more particularly, to a target reproduction output data based on sub-code time information.
The present invention relates to a reproducing apparatus which can always obtain the same reproduction output data when searching for data.

[0002]

2. Description of the Related Art Currently, in the field of audio equipment, an audio signal is converted to a P signal in order to perform recording and reproduction with high density and high fidelity.
2. Description of the Related Art There is known a digital recording / reproducing system which converts a signal into a digitized signal by a CM (Pulse Code Modulation) technique, records the signal on a recording medium such as a disk or a magnetic tape, and reproduces the signal. In particular, a CD in which a bit string corresponding to digitized data is formed on a disk having a diameter of 12 cm and which is read optically is most widely used. In such a disk reproducing apparatus, an optical pickup element having a built-in semiconductor laser or photoelectric conversion element is moved linearly from the inner peripheral side to the outer peripheral side of the disk, and the CD is kept at a constant linear velocity (CLV). : ConstantLinear Veloc
)), the data recorded on the CD
Data is read. The CD stores digital data (main information data) obtained by converting an analog audio signal into PCM with 8 bits. Digital data is 8
24 symbols each having one bit as one symbol are defined as one frame, and data is stored in a form in which this frame is repeated. In this disc, a cross interleave lead solomon (CIRC) code is used as an error correction code. The 24-symbol digital data is supplied to a C2 sequence parity generation circuit via a scrambling unit, and parity data Q for C2 sequence error correction of 4 symbols is generated.

The digital data and the parity data Q are supplied to a C1 sequence parity generation circuit via an interleave circuit to generate 4-symbol C1 sequence error correction parity data P of four symbols. The 32-symbol data consisting of the 24-symbol digital data and the 4-symbol parity data P and Q is added with 8-bit subcode data after passing through one frame delay circuit. The subcode data and the data of 32 symbols are EFM (Eight to Fourteen).
Modulation) Modulation is applied. A 3-bit margin bit is added between the modulated 14-bit symbols, and a 24-bit frame period signal is added at the beginning. Thus, 588-bit data is recorded on the disc as one frame. In this case, since the bit clock is 4.32 MHz, data is recorded on the disk at 136 μsec (7.35 KHz) per frame. One subcode frame is composed of 98 frames, and is recorded on a disk at 75 Hz (13.3 msec) per subcode frame.

[0004] The disk reproducing apparatus separates a synchronizing signal from the digitized data read from the compact disk, and then demodulates the data by EFM to generate parity data P and Q.
Are separated into a 32-symbol word component and a sub-code data component. Then, a C1 sequence error correction process is performed on the word component based on the parity data P. 24 symbol digital data and 4 symbol parity data
After the deinterleaving process, the data Q
The C2 sequence error correction processing is performed based on the data Q. And
The digital data of 24 symbols is D / A (Digital to
Analogue) The signal is supplied to a conversion circuit and an analog signal processing circuit and is reproduced as an audio signal. By the way, the so-called track jump, in which the optical pickup element is skipped from the track currently being traced to another track, may occur due to vibration or shock applied from the outside during reproduction of the disk. In such a case, the subcode data
Using the time information included in the data, the pickup is returned to the original track and the playback operation is continued,
Playback is temporarily suspended until the pickup returns to the original track and resumes playback.

Therefore, in order to prevent interruption of reproduction, a buffer memory having a storage capacity larger than the amount of data reproduced during the time required for the pickup to return to the original track is used, and the buffer memory becomes full. Until it becomes
The disk reproduction speed is controlled so that the disk is reproduced at a higher speed than a predetermined speed and a predetermined amount of data is always stored in the buffer memory. The reproduction data is written to the buffer memory sequentially according to the reproduction speed of the disk, and the read from the buffer memory is sequentially read at a predetermined speed. The write address always precedes the read address and the reproduction data corresponding to the address difference.
The data capacity serves as a buffer when a track jump occurs. The detection of a track jump is performed based on the time information of the subcode Q channel. The absolute time of the disk is continuously recorded on the subcode Q channel, and when this discontinuity is detected, it is determined that a track jump has occurred. The subcode forms one block with 98 frames.

[0006]

As shown in FIG. 5, when a track jump is detected after the subcode block of the absolute time (N-1) is reproduced, the subcode immediately before the track jump is detected.
The write address (WA) of the last data (a) of the data block (N-1) is recorded. Then, the subcode block of the absolute time (N) is searched, and the writing is restarted with the write address of the first data (b) as (WA + 1). By sequentially reading the reproduction data written in the buffer memory at a predetermined speed in this manner, even if a track jump occurs, the reproduction data can be continuously output without interrupting the reproduction data. It is necessary to output. In a conventional disk reproducing apparatus, a disk is driven by a disk motor, data recorded on the disk is read by an optical pickup, and the read data is RF.
Supplied to the circuit. The RF circuit extracts a focus error signal and a tracking error signal from the output of the optical pickup, supplies the signal to the servo control circuit, binarizes the reproduced signal, and supplies the signal to the signal processing circuit as an EFM signal. The signal processing circuit performs EFM demodulation, subcode demodulation, error correction processing and the like, and supplies the output DATA signal to the buffer memory control circuit.

The buffer memory control circuit controls writing and reading of the DATA signal to and from the buffer memory. The DATA signal read from the buffer memory is supplied to a digital / analog converter via a buffer memory control circuit.
Data (DAC). The output of the DAC is supplied to a low-pass filter (LPF), and the output of the LPF becomes a reproduced audio output AOUT signal. FIG. 8 shows a conventional signal processing circuit, for example. The EFM signal from the RF circuit is input to the PLL circuit 60 and then to the EFM demodulation circuit 61. A PLL clock (reproduction clock) synchronized with the EFM signal for reading the EFM signal by the PLL circuit 60
Is generated and supplied to the EFM demodulation circuit 61. On the other hand, the subcode data of the demodulated EFM signal (SUB
Q) is supplied to a sub-code demodulation circuit 64, where it is demodulated and output to the system controller 11 (see FIG. 2). Since the PLL clock is also supplied to the sub-code demodulation circuit 64, the sub-code data is output in synchronization with the reproduced clock.

As described above, since the sub-code data is output in synchronization with the reproduction clock synchronized with the rotation of the disk motor, the reproduction is output in synchronization with the system reference clock generated by the crystal oscillator or the like. There is jitter between the data and the data. Therefore, for example, a track jump occurs as described above, and even when the subcode block (N) is searched, a shift corresponding to the jitter occurs. The data a in FIG.
As shown in FIG. 7, after the search, data a 'or data
A ″. For example, when the jitter absorbing ability is ±
In the case of 6 frames, jitter of a maximum of 12 frames occurs, and discontinuity occurs in writing to the buffer memory. Therefore, even if it is read, the playback data is continuously
Data cannot be output. The present invention has been made under such circumstances, and synchronizes sub-code data with reproduction data.
It is an object of the present invention to provide a disk reproducing apparatus for continuously and accurately reproducing information data recorded on a disk even when a track jump occurs due to disturbance or the like during reproduction of the disk.

[0009]

The present invention is characterized by synchronizing reproduced data with the subcode data by synchronizing the subcode data with a system reference clock.

That is, the disk reproducing apparatus of the present invention comprises:
Means for reading the information data from the disc on which the information data is recorded as reproduction data and subcode data; and binarizing the reproduction data and the subcode data read from the information data reading means to EFM.
A signal generating means, a clock reproducing means for generating a reproduced clock synchronized with the EFM signal, and a synchronizing signal of the EFM signal separated by the reproduced clock.
Means for demodulating an FM signal; means for writing the EFM-demodulated subcode data and the reproduced data to a memory in synchronization with the reproduction clock; and means for synchronizing with an externally supplied system reference clock from the memory. A first feature is that a means for reading the subcode data and the reproduction data is provided.

An optical pickup element for reading reproduction data and subcode data from a disc on which information data is recorded; an EFM signal generation circuit for binarizing the reproduction data and subcode data to generate an EFM signal; A PLL circuit for generating a reproduction clock synchronized with the EFM signal, an EFM demodulation circuit for separating the synchronization signal of the EFM signal by the reproduction clock, and synchronizing the EFM demodulated subcode data and the reproduction data with the reproduction clock. And a memory for reading the subcode data and the reproduction data in synchronization with a system reference clock.

The signal processing circuit according to the present invention provides an EF obtained by binarizing read reproduction data and subcode data.
A clock recovery means for generating a reproduction clock synchronized with the M signal; a means for separating a synchronization signal of the EFM signal by the reproduction clock and demodulating the EFM signal;
Means for writing the M-demodulated sub-code data and the reproduction data to a memory in synchronization with the reproduction clock; and the sub-code data and the reproduction data from the memory in synchronization with an externally supplied system reference clock. And means for reading out the data.

[0013]

The sub-code data is synchronized with the reproduction data by synchronizing with the system reference clock.
For example, when the subcode data of the absolute time (N) is searched, the reproduced data is always the same data. Therefore, the reproduced data can be continuously obtained by writing the reproduced data to the buffer memory means in units of sub-code blocks and sequentially reading the data.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 2 is a block diagram of the disk reproducing apparatus of this embodiment. In the figure, a disk 1 such as a CD is driven by a disk motor 2 and is rotating.
Data recorded by the optical pickup element (PU) 3 is read from the rotating disk 1, and the read data is supplied to an EFM signal generation circuit (hereinafter, referred to as an RF circuit) 4. . The RF circuit 4 extracts a focus error signal and a tracking error signal from the output of the optical pickup element, supplies the focus error signal and the tracking error signal to the servo control circuit 5, binarizes the reproduction signal, and converts the reproduced signal into an EFM signal, for example, a deco signal. To a signal processing circuit 6 such as The servo control circuit 5 controls the focus of the optical system of the optical pickup element 3 so that the focus error signal becomes zero, and the tracking error signal becomes zero. A tracking servo circuit for controlling the tracking of the optical system of the optical pickup element 3, and a spindle motor for rotating the disk 1 at a predetermined rotation speed.
Spindle motor for controlling a disk motor 2 such as a motor
And a thread servo control circuit for moving the optical pickup element to a target track position of the disk 1 designated by the system controller.

The signal processing circuit 6 performs read clock generation, EFM demodulation, subcode demodulation, error correction processing and the like of the EFM signal, and supplies the output DATA signal to the buffer memory control circuit 7. The buffer memory control circuit 7
It controls writing and reading of the DATA signal to and from the buffer memory 8. DATA read from buffer memory 8
The signal is supplied to the DAC 9 via the buffer memory control circuit 7. The output of the DAC 9 is supplied to the LPF 10, and the output of the LPF 10 becomes a reproduced audio output AOUT signal. The signal processing circuit 6 will be described with reference to a block diagram showing details of the signal processing circuit 6 in FIG. The EFM signal supplied from the RF circuit is input to the PLL circuit and the EFM demodulation circuit 61. A PLL clock synchronized with the EFM signal for reading the EFM signal is generated by the PLL circuit 60 and supplied to the EFM demodulation circuit 61. Also, EF
The M signal is separated from the synchronizing signal by the EFM demodulation circuit 61, EFM demodulated by the EFM demodulation circuit 61, and one symbol of sub-code data per frame, 32 symbols of data including parity data, Data of 33 symbols in total
The data is written to the memory 62 as data. The memory 62 is used as a jitter absorbing memory and an error correcting interleaving memory.

Writing to the memory 62 is performed by a reproduction PLL.
By performing the reading in synchronization with the clock and reading in synchronization with the system reference clock of the crystal system, the time axis jitter component by the disk motor 2 can be absorbed. The output of the memory 62 is supplied to an error correction circuit 63, and C1,
The C2 sequence error correction is performed. The data for which the error correction processing has been completed is read from the memory 62 again, and
It is supplied to the output circuit 65. When there is uncorrectable data in the error correction circuit 63, the output circuit 65 performs processing such as average value correction processing and muting, and then outputs it as a DATA signal. Referring to FIG.
2 will be described. This figure shows a memory map showing the state in the memory 62, in which a row represents a symbol address having 33 symbols including a subcode symbol (SUB), and a column comprises a frame address consisting of 98 frames. Is represented. The frame address is divided into one for error correction interleaving and one for jitter absorption. The memory 62 included in the signal processing circuit 6 performs the following four processes.

(1) Processing for writing EFM demodulated subcode symbols and data of 32 symbols (this processing is denoted by W). (2) Subcode symbol reading and C1 sequence symbol read / write processing for C1 sequence error correction processing (this processing is denoted by C1).
(3) C2 sequence symbol read / write processing for C2 sequence error correction processing (this processing is denoted as C2).
(4) Read processing for outputting to the output circuit (this processing is indicated as R). Here, only the write process (1) is written to the memory at a timing synchronized with the PLL clock of the reproduction system. Other read / write processing is performed by a crystal system reference clock. Therefore, the jitter of the sub-code symbol and the data symbol of 32 symbols is absorbed by the memory. In this example, the reading of the subcode symbol is
It is performed at the time of error correction processing of one sequence, but can be performed at any timing as long as jitter is absorbed.
However, it is most efficient to read the sub-code symbols during the error correction processing of the C1 sequence.

The sub-code demodulation circuit 64 reads the sub-code data from which the jitter component has been absorbed from the memory 62, performs a sub-code demodulation process, and executes the system controller 11 shown in FIG. Output to The subcode data is one symbol per frame (8 bits: P, Q, R, S,
T, U, V, W channels) and 98 frames
One block is constituted by the system. S at the beginning of the block
There are two O and S1 synchronization patterns and the remaining 96
The symbols correspond to the subcode data. Subcode 8
The following information is recorded in the Q channel among the bits. That is, the lead-in area of the disc (radius 23
２５25 mm) includes TOC (Table of Contens) information indicating the number of songs recorded on the disc and their start times, and the program area (radius 25 to 58) of the disc.
mm), a track number, an index, an elapsed time in the track, absolute time information, and the like recorded on the disc are recorded. The system controller 11 shown in FIG.
A control signal is supplied to the servo control circuit 5 in order to search for a desired music piece based on the time information obtained from the channel Q, and the position of the pickup 3 is controlled.

As described above, the sub-code symbol is written by the memory 62, so that the jitter is absorbed in the memory 62. Therefore, since the sub-code data and the reproduction output data are synchronized, the sub-code is
When the target reproduction output data is searched based on the time information of the data Q channel, the same reproduction output data can always be obtained. Even if such a disk reproducing apparatus of the present invention is used, for example, when a track jump occurs and the track returns to the original track and reproduction is resumed as described below, the present invention is applied without losing the continuity of data. be able to. In this reproducing apparatus, when an optical pickup traces a track formed on a disk to read data, the optical pickup serves as a pickup element provided in the optical pickup due to externally applied vibration or the like. A so-called track jump, in which the objective lens is skipped from the track currently being traced to another track, may occur.

When the system controller 11 has the subcode Q
The continuity of the absolute code of the channel is checked, and if discontinuity is detected, it is determined that a track jump has occurred. For example,
After correctly reproducing to the absolute time (N-1), the absolute time (X-
If the track jump is made to 1), the system controller 11 detects the track jump after reproducing the absolute time (X), searches for the absolute time (N-1), and picks up the pickup 3.
Is supplied to the servo control circuit 5 so as to return to the original track. After reproducing the absolute time (N-1), it is detected that the track has returned to the original track. When a track jump occurs as described above, if it is reproduced at a predetermined speed, the time required for the pickup 3 to return to the original track,
Playback is paused. Therefore, a buffer memory 8 having a storage capacity equal to or larger than the amount of data reproduced during the time required for the pickup 3 to return to the original track is used as the buffer memory of the system, and until the buffer memory 8 becomes full. Reproduces at a higher speed than a predetermined reproduction speed. The buffer memory control circuit 7 sequentially writes the DATA signals to the buffer memory 8 according to the reproduction speed of the disk, reads out the DATA signals sequentially at a constant speed, and supplies the same to the DAC 9.

The write address always precedes the read address, and the reproduction data amount corresponding to the difference between the write address and the read address becomes a buffer when a track jump occurs. The buffer memory control circuit 7 calculates the difference between the write address and the read address. Based on the calculation result, the system controller 11 reproduces the disk so that a predetermined amount of buffer in the buffer memory 8 is always secured. Control the speed. FIG. 4 shows the state of the address of the buffer memory 8 controlled by the buffer memory control circuit. The vertical axis indicates the memory address, and the horizontal axis indicates the time. The read address always advances at a constant speed. Initially the buffer is empty, so the disc plays faster than a certain speed. Therefore, the write address also advances faster than the read address. At time T0, the buffer becomes full and the disk playback speed returns to the constant speed. At time T1, a track jump occurs, and writing of valid data is interrupted. At time T2, the track returns to the original track and reproduction is started based on the time information of the subcode Q channel. At this time, since the buffer is almost empty, the disk is reproduced again at a higher speed than the constant speed, and the buffer becomes full at time T3.

When a track jump occurs as described above, the buffer memory control circuit 7 writes a write address of the last data (a) of the reproduced data of the block of the absolute time (N-1) that has been correctly reproduced. (WA) is stored, the system controller 11 returns to the original track, and when the block of the absolute time (N) is reproduced, the first data (b) is reproduced.
From the write address (WA + 1).
FIG. 5 shows the relationship between the subcode Q channel and reproduced data when a track jump occurs. As shown in the figure,
Last data of the absolute time (N-1) before the occurrence of a track jump
The data (a) and the write address of the first data (b) of the absolute time (N) at the time of returning to the original track and restarting the reproduction after the occurrence of the track jump are continuous. Therefore,
By sequentially reading out these data, the AOUT signal can be output continuously. A disk reproducing apparatus is a system configured by attaching a semiconductor chip or other components in which various integrated circuits are incorporated to a circuit board, for example,
In the present invention, a signal processing circuit is incorporated in the semiconductor chip S (see FIG. 2). The signal processing circuit and the system controller (microcomputer) can be incorporated in the same semiconductor chip.

FIG. 6 illustrates the synchronization of the constituent circuits of the signal processing circuit incorporated in the semiconductor chip S. In this signal processing circuit, as shown in FIG. 1, the PLL circuit 60 generates a PLL clock synchronized with the EFM signal,
This is supplied to the EFM demodulation circuit 61. After the EFM signal is separated from the synchronization signal by the EFM demodulation circuit 61,
EFM demodulation is performed by the FM demodulation circuit 61 and written into the memory 62. The memory 62 is used as a jitter absorbing memory and an error correcting interleaving memory. Writing to the memory 62 is performed in synchronization with a reproduction PLL clock, and reading is performed in synchronization with a crystal system reference clock. The output of the memory 62 is supplied to an error correction circuit 63. The data for which the error correction processing has been completed is read from the memory 62 again, supplied to the output circuit 65 in synchronization with the system reference clock, and output therefrom as a DATA signal. A memory 62, an error correction circuit 63, a subcode demodulation circuit 64, and an output circuit 65 constituting the signal processing circuit perform signal processing in synchronization with the system reference clock. The system reference clock is generated by a clock oscillator that oscillates a crystal and is supplied to each circuit. The clock oscillator is mounted on a circuit board separately from the semiconductor chip.

[0024]

As described above, according to the present invention, the sub-code data and the reproduction data are synchronized, and therefore, when the target reproduction output data is searched based on the time information of the sub-code Q channel, the same is always obtained. Can be obtained. Therefore, for example, even if a track jump occurs and the track returns to the original track and reproduction is resumed, the continuity of data is not lost.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal processing circuit of the present invention.

FIG. 2 is a block diagram of a disk reproducing apparatus according to the present invention.

FIG. 3 is a memory map diagram of the memory of FIG. 1;

FIG. 4 is an address state diagram of a buffer memory.

FIG. 5 is an explanatory diagram showing a relationship between a subcode Q channel and reproduced data according to the present invention.

FIG. 6 is an explanatory diagram showing a relationship between a system reference clock generated by a clock oscillator of the present invention and a circuit synchronized with the system reference clock.

FIG. 7 is an explanatory diagram showing a relationship between a subcode Q channel and reproduction data in a conventional example.

FIG. 8 is a block diagram of a conventional signal processing circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 disc 2 disc motor 3 optical pickup element 4 RF circuit 5 servo control circuit 6 signal processing circuit 7 buffer memory control circuit 8 buffer memory 9 digital / analog converter (DAC) 10 low-pass filter (LPF) DESCRIPTION OF SYMBOLS 11 System controller 60 PLL circuit 61 EFM demodulation circuit 62 Memory 63 Error correction circuit 64 Subcode demodulation circuit 65 Demodulation circuit

Claims (3)

(57) [Claims] A means for reading the information data from a disk on which the information data is recorded as reproduction data and subcode data; and a method for converting the reproduction data and the subcode data read from the information data reading means into binary data. Means for generating a reproduced clock synchronized with the EFM signal; means for demodulating the EFM signal; means for reproducing the EFM demodulated subcode data and the reproduced data. A disk comprising: means for writing to a memory in synchronization with a clock; and means for reading out the subcode data and the reproduction data from the memory in synchronization with a system reference clock supplied from outside. Playback device. 2. An optical pickup element for reading reproduction data and subcode data from a disc on which information data is recorded, and binarizing the reproduction data and the subcode data into an EFM.
An EFM signal generation circuit for generating a signal; and a PL for generating a reproduction clock synchronized with the EFM signal.
An L circuit; an EFM demodulation circuit for separating a synchronization signal of the EFM signal by the reproduction clock; writing EFM demodulated subcode data and reproduction data in synchronization with the reproduction clock; and synchronizing with a system reference clock. A disk reproducing device comprising a memory for reading subcode data and reproduction data. 3. A clock reproducing means for generating a reproduction clock synchronized with an EFM signal obtained by binarizing read reproduction data and subcode data; means for demodulating the EFM signal; and EFM demodulation. Means for writing the read subcode data and the reproduced data to a memory in synchronization with the reproduction clock; and reading the subcode data and the reproduction data from the memory in synchronization with a system reference clock supplied from the outside. A signal processing circuit.