JPH0191377A - Data reproducing device - Google Patents

Abstract

PURPOSE:To remarkably shorten a reproducing time by executing complementary data interpolation among respective reproduced data reproduced in a tape- shaped recording medium in which data corresponding to the same information is recorded over plural tracks in case said each reproduced data is unable of being corrected for the error. CONSTITUTION:One-field-quantity of digital video data outputted from an A/D converter 12 is written in a field memory 13 corresponding to an operation through operational members, and this one-field-quantity of video data is recorded over many tracks. In case the recording is executed with H1, a drum 50 is rotated by an angle theta, then, during the subsequent rotation of the drum 50 for (180-theta), the data is reproduced by a head H2. This reproduced output is inputted to a demodulator 22, then an error detecting circuit 23 detects the number of pieces of data errors and their generation patterns. In the event of an error, whether or not an error correction is possible is judged, and in case the correction is possible, the drum 50 is returned, the data is updated to correct data, and the following recording action is started. In such a way, the reliability of reproduced data can be improved.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a data reproducing device, and particularly to a data reproducing device that plays a tape-shaped recording medium in which a predetermined amount of data is recorded on a large number of tracks arranged in parallel at a predetermined speed. The present invention relates to a device that transports and reproduces data.

<Prior Art> Conventionally, data recorders for recording digital data have been proposed, including those using a disk-shaped recording medium such as a floppy disk, and those using a tape-shaped recording medium.

However, in this type of cheater recorder, the loss of recorded data is a fatal defect. Therefore, when recording data, it is essential to check the recorded data in order to guarantee the reliability of the recorded data, so-called verification.

This verification is performed in conventional data recorders using a method suitable for the recording method, recording medium, and other conditions.

FIG. 7 is a diagram showing a recording trajectory on a recording medium by a general data recorder using a disk-shaped recording medium, and FIG. 8 is a diagram for explaining data arrangement on the recording trajectory in FIG. 1 is a disk-shaped recording medium, 2a, 2b, 2c,
2d indicates a recording trajectory in which one sector is recorded. In this type of data recorder, a plurality of sectors are recorded as shown in FIG. 8(b) in response to index pulses as shown in FIG. 8(a). In Figure 8(a), G
The portion indicated by AP indicates a portion where no data is recorded. 1
Data is arranged in the two sectors as shown in FIG. 8(c'). In the figure, DATA is the main data to be recorded, DATASync is data for synchronizing the main data,
ID is Sara data such as control data, ID5yn
c is data for synchronizing Sara data, and CRCC is a well-known cyclic code (hereinafter referred to as CRCC).

In this type of data recorder, verification is performed by reproducing the data immediately after recording, using the reproduced CRCC to observe the occurrence of data errors, and if it is determined that many data errors occur, The same data was recorded again in the same phase portion above.

On the other hand, in a data recorder using a tape-shaped recording medium, as shown in Figure i9, there is a recording rad 5 located upstream in the transport direction of the tape 3 (indicated by arrow 4) and a worn verify rad 5 located downstream. A verification head 6 is installed to verify the occurrence of errors in data recorded by the recording spatula 145.
Observe using a regenerated CRCC or parity check coat. If a large number of data errors occur, transport of the tape 3 is stopped and data recording is interrupted.

Furthermore, when data is reproduced, if uncorrectable data occurs, the tape 3 is rewound and the same track is repeatedly reproduced until the error can be corrected, thereby increasing the reliability of the reproduced data. It was thought that

<Problem to be solved by the invention> However, the amount of data that can be recorded in the data recorder using the disk-shaped recording medium described above is limited, and it is not suitable for storing huge amounts of data. do not have. On the other hand, data recorders that use tape-shaped recording media either record a relatively large amount of data or stop recording when a data error occurs during recording, so the average data transmission hit rate must be kept small. Unavoidably, the recording time becomes extremely long. Further, even during reproduction, it takes an extremely long time to rewind the tape and reproduce data on the same track due to 1σ, which generates uncorrectable data. The fact that recording and reproducing takes a long time in this way significantly reduces the usefulness of the cheater recorder, and has hindered the widespread use of data recorders using tape-shaped recording media.

<Means for Solving the Problems> For this purpose, the data reproducing device according to the present invention has the following features:
In a device that reproduces data by conveying a tape-shaped recording medium in which a predetermined amount of data is recorded or a large number of tape-shaped recording media arranged in parallel at a predetermined speed, it is possible to reproduce data by transporting a plurality of tracks on which a predetermined amount of data is recorded. When it is impossible to correct errors in data sequentially reproduced from the tracks, data is interpolated complementary to each reproduced data of the plurality of tracks and then output.

<Operation> By configuring as described above, when data relating to the same information is recorded across multiple tracks, even if it is impossible to correct errors in reproduced data for all tracks, there is a high probability that complementary data will be generated. Data interpolation makes it possible to eliminate error data and significantly shorten the time required for reproduction.

<Example> Examples of the present invention will be described below.

FIG. 2 is a diagram showing a schematic configuration of a data recording/reproducing apparatus according to an embodiment of the present invention. In the figure, reference numeral 11 denotes a terminal to which an analog video signal obtained from a camera or the like (not shown) is input.
The data recorder of this embodiment converts this analog video signal into digital data and records and reproduces it.

12 is an analog digital (A/D) converter that digitizes the analog video signal input to the terminal 11;
13 is a field memory capable of storing one field of a digitized video signal; 14 is an address control circuit 115 that controls write and read addresses of the field memory 13; and an address control circuit 115 that stores data other than video data such as control data and character data. (hereinafter referred to as ID) and outputs it as PCM data after performing interleaver processing, addition of redundant codes such as error detection code and error correction code, etc. to the 16-bit data and ID. 17 is a PCM processor 16
a modulator that digitally modulates the PCM data output from the
18 is a recording amplifier.

Also, SWI, SW2. SW3 has a changeover switch, 21 is a reproducing amplifier, 22 is a demodulator corresponding to the modulator 17, and 23 is a data error detection code using the error detection code and error correction code in the PCM data obtained through the demodulator 22. Error detection circuit for detecting the number of occurrences, occurrence pattern, etc., 2
4 is a system control circuit that controls the entire device; 25 is a PC
31 is a complementary interpolation circuit which is a characteristic element of the present invention; 26 is a PCM
An ID processing circuit outputs various control data and data other than video data based on the ID obtained from the processor 25; 27 is a field memory that receives video data output from the interpolation circuit 31; 28 is a field memory 27 write and output circuit; An address control circuit 29 controls the read address, and a digital circuit 29 converts the digital video data read from the field memory 27 into analog and outputs it.
An analog (D/A) converter 30 is an output terminal for an analog video signal.

H1 and H2 are respectively rotary heads, and their arrangement will be explained with reference to FIGS. 3(A) and 3(B). Figure i3 (A>
As shown in the figure, the heads H1 and H2 are mounted on a rotating cylinder 50 with a phase difference of 180°, and the magnetic tape T is wound around the cylinder 50 over an angular range of less than 1806 degrees (θ°). has been done.

The head H1 is used for data recording and reproduction, and the head H2 is used for data reproduction.As shown in FIG. Rotate on different planes of rotation. This distance X is considered as a correction of the recording track pitch if recording is performed only by the head H1 and is sufficiently small compared to the track length or the recording track pitch. As a result, the heads H1 and H2 take the center line of the trace locus as shown in FIG.

Data recording and reproducing operations in the data recorder configured as described above will be explained below.

FIG. 5 is a flow chart showing the operation of the system control circuit 24 during data recording, and the operation during data recording will be described below with reference to the flow chart of FIG. Note that during data recording, the switches SWI and SW3 are each connected to the R side.

One field of digital video data output from the A/D converter 12 is stored in the field memory 13 in accordance with the operation of an operation member (not shown). Since the bit rate of digital data obtained by digitizing video signals in real time is extremely high, the field memory 13 is
To output 8 minutes of video data, that is, still image data, with a reduced bit rate. Accordingly, this 8 minute video data will be recorded over a large number of tracks.

In step 101 of FIG. 5, an ID is set by the ID processing circuit 15, but this ID! It includes track number data and the like indicating whether the data is recorded in the middle track of the field's worth of video data.

When the recording head H1 reaches a predetermined rotational phase, data for one track is recorded by the head H1 via the R side terminal of SW3 (step 102). This recording ends when the drum 50 rotates 00 times, and the tram 50 (
180-.theta.) After 0 rotations, the reproducing head H2 has reached the starting end of the track just recorded, and this track is reproduced by the reproducing head H2 (step 103).

The reproduction signal of the reproduction head H2 is input to the demodulator 22 via the R side terminal of SWl and the recording amplifier 21, and the error detection circuit 23 uses the error correction code etc. output from the demodulator 22 to detect data errors. The number, occurrence pattern, etc. are detected. At this time, if it is determined in step 104 that a data error has not occurred, the track number data, etc.
D is updated in step 105), and the data to be recorded next is transferred from the field memory 13 to the PCM processor 16.
(step 106). If the data to be recorded is completed, the process is completed according to this flowchart, and if the data is not completed, step 10 is performed.
Returning to step 2 (step 1o7), new data is recorded on the next track.

On the other hand, if it is determined in step 104 that a data error has occurred, the number of data errors occurring is checked in step 108, and the pattern of data error occurrence is checked in step 109. Based on these checks, if it is determined in step 110 that error correction is possible, the process returns to step 102 via steps 105 and 106, and new data is similarly recorded on the next track.

If it is determined in step 110 that error correction is not possible, the process returns to step 102 without updating the ID or data, and the same data is recorded again on the next track.

In the process according to the flowchart of FIG. 5, the processing time from the end of regeneration in step 103 to the start of regeneration in step 102 is set so that it is within the period of 50 or 00 revolutions of the cylinder. Not even.

As mentioned above, if it is determined by the verification immediately after recording that the recorded data cannot be corrected, the same data will be recorded repeatedly, and the rotation of the drum 50 and the running of the DESO T will be stopped. Highly reliable data can be recorded without any trouble. Therefore, data recording is performed one after another, and highly reliable data can be recorded in a short period of time.

FIG. 6 is a flowchart for explaining the operation of the system control circuit 24 during reproduction by the apparatus shown in FIG. 2, and FIG. 1 is a diagram showing an example of the configuration of the complementary interpolation circuit 31 in FIG. The operation during reproduction will be described below using these drawings.

During playback, the switches SWI and SW2 are connected to the P side, respectively, and the switch SW2 is controlled by a control circuit (not shown) to switch between A and 8 every time the head drum 50 rotates 180''.
Connected alternately to both terminals.

After the ID reproduced by the head H1 is read (step 201), if it is determined in step 202 that data has been recorded, it is determined from the output of the error detection circuit 23 whether or not a data error has occurred. (Step 203). If no data error has occurred, the process advances to step 219.

On the other hand, if a data error has occurred, based on the detection result of the error detection circuit 23, the number of errors occurring is checked (step 205) and the error occurrence pattern is checked (step 206). A determination is made as to whether or not the error can be corrected. If the error can be corrected, error correction processing is performed in step 208, and then the process proceeds to step 219. If it is determined that error correction is not possible, wait until switch SW2 is connected to the B side, and head H
The ID output from 2 is read out (step 209),
Operations similar to steps 203 to 208 are performed on the reproduced data from head H2 (steps 213 to 21
8).

After that, when the switch SW2 is connected to the A side again, the ID reproduced by the head H1 is read out (step 2
09), the aforementioned track number data in the currently read ID is compared with the track number data in the previously read ID. Along with this, it is determined whether the track to be reproduced this time and the track reproduced immediately before have data relating to the same information, that is, whether the data has been updated (step 221). If the data has not been updated, it can be determined that the track is the second or subsequent track of a portion where the same data was recorded over multiple tracks due to parsing and refining during recording, and in this case, the step Return to 202. If the data has been updated, the complementary interpolation circuit 31 outputs the data in step 223.

The operation of the complementary interpolation circuit 31 will be described below with reference to FIG. WCL in the figure is a word clock supplied from the system control circuit 24, and is synchronized with each word of data indicated by Data in the figure. Data is data output from the PCM processor 25, and has already been subjected to error correction processing. EF is an error flag that is supplied from the PCM processor 25 and indicates whether the data is an error.

The input data Data is supplied to a random access memory (RAM) 51 as a buffer memory and A inputs of a multiplexer (MPX) 56. RAM51
The address of the RAM 51 is determined by an address counter 52 that counts the word clock WCL, and the write mode and read mode of the RAM 51 are determined for each word by an error flag EF. That is, only words with no errors are written into the RAM 51, and when a word with an error is being input, the RAM 51 is in the read mode. On the other hand, the MPX 56 outputs the input data to the B side when a word containing an error is input, and to the A side when a word without an error is input.

RT is sent from the system control circuit 24 to step 22 in FIG.
3 is an output trigger signal provided in connection with 3. This trigger signal RT is determined in units of data for one track,
Determine whether or not to output data from the MPX56.

When the data to be outputted in step 223 in the flowchart of FIG. 6 is error-free data including error-corrected data, if no errors occur at all, the MPX56 always inputs the data to the A side. The data will be output. On the other hand, if the data includes error data in which an error has occurred, the data read from the RAM 51 is output while the error data is being input. By the time the MPX 56 enters the output mode, data for 2x tracks will have been input. Here, X is the number of tracks on which data relating to the same information is continuously recorded. During this time, the RAM 51 replaces addresses in which data errors have occurred one after another with words without data errors, and finally two
x) Regarding data for a rack, data without data errors is output unless all data errors occur in words at the same address.

Error 1 sotsu EF is connected to RA via inverter 53.
Each word address is stored in a predetermined area in M51, and this area is also rewritten every time the error flag EF is input. For data in this area, please refer to MPX56
It is reset immediately after reading, that is, by the edge of the trigger signal RT. When data is read from the RAM 51, an error flag indicating whether or not the read word has caused a data error is output to the inverter 54. This flag is counted by the counter 55, and if the count value VT is "1" or more, then the MPX5
This indicates that the data output from 6 contains a data error.

Here, when the trigger signal RT is at a high level, if the count value VT of the counter 55 is greater than or equal to rlJ, it is also possible to rewind the tape by a predetermined amount and reproduce the same track again. However, this is effective only when extremely high reliability is required, and if interpolation can be performed using other methods, such as in the case of data related to image information, as in this embodiment, the playback time will be long. In that sense, I don't like it.

With the configuration of the reproducing system as described above, data can be reproduced with high reliability without stopping tape transport, and the reproducing time is significantly shortened compared to conventional data recorders.

<Effects of the Invention> As explained above, according to the data reproducing device of the present invention, the time required for reproducing data can be significantly shortened, and the applications of data recorders using tape-shaped recording media can be expanded. .

[Brief explanation of the drawing]

Fig. fjSi is a diagram showing the main part configuration of a reproduction system of a cheater recorder as an embodiment of the present invention. FIG. 2 is a diagram showing the overall schematic configuration of a cheater recorder as an embodiment of the present invention, FIGS. 3A and 3B are diagrams showing the head arrangement of the recorder in FIG. 2, and FIG. Fig. 5 is a flowchart for explaining the operation of the system control circuit during recording by the recorder shown in Fig. 2; A flowchart for explaining the operation of the system control circuit during playback of the recorder. FIG. 7 is a diagram showing a recording trajectory of a recording medium by a general data recorder using a disk-shaped recording medium. FIG. 8 is a diagram for explaining the data arrangement on the recording trajectory in FIG. 6, and FIG. 9 is a diagram showing an example of a conventional data recorder using a tape-shaped recording medium. In the figure, H1 is the first rotary head, H2 is the second rotary head, T is the tape, 16.25 is the PCM processor, 23 is the error detection circuit, 24 is the system control circuit, 31 is the complementary interpolation circuit, and 51 is the Random access memory 56 is a multiplexer.

Claims (1)

[Claims] A device that reproduces data by conveying at a predetermined speed a tape-shaped recording medium in which a large number of tracks on which a predetermined amount of data are recorded are arranged in parallel, and the data relating to the same information is recorded. A data reproducing apparatus characterized in that when data sequentially reproduced from a plurality of tracks cannot be error corrected, data is interpolated complementary between each reproduced data of the plurality of tracks and then outputted.