JPS63211923A - Error correction decoder - Google Patents

Abstract

PURPOSE:To attain an operation similar to that of a conventional decoder by one memory by using data free from error flag in a data signal transmitted later to rewrite the memory. CONSTITUTION:A data signal extracted sequentially from plural transmission lines is fed to an error detection decoder 2 using an error detection code C1. A control signal switched between a 1st and subsequent reproductions when two recordings fed to a terminal 4 are reproduced sequentially, and an error flag X sent from the decoder 2 are fed to a write control circuit 5 and a write control signal is fed to a write control terminal WE of the memory 3. Thus, the data D and the error flag X of a first data signal are written once in the memory 3, and only the data D free from error flag X in the latter data signal is rewritten. Thus, similar error correction decoding is applied to that of a conventional decoder and a signal subjected to error correction decoding is extracted from an output terminal 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction decoding device applied to recording and reproducing audio signals of, for example, a digital VTR.

[Summary of the invention]

The present invention relates to an error correction decoding device, in which when the same signal is transmitted two or more times, the data of the first supplied data signal and an error flag are written in a memory, and the data is detected from the later supplied data signal. By rewriting the memory according to the detected error flag, the memory capacity used for error correction decoding is reduced.

[Conventional technology]

When transmitting digital data signals, there is a risk that errors may occur in the data due to dropouts or noise in the transmission path. In response to this problem, various error detection and correction methods have been proposed.

That is, for example, in FIG. 2, a large number of data D are expanded two-dimensionally as shown in FIG. 2 to form a data map, and an error correction code C2 is generated for each vertical data block of this data map. . Furthermore, an error detection code C1 is generated for each horizontal data block of the data map including this correction code C2. And these data D, codes C1, C
2 are transmitted in a predetermined order.

Therefore, when decoding a data signal transmitted in this way, the transmitted data signal is first developed in the same manner as in Figure 8 above to form a data map, and this map is shown, for example, by the dashed line in the figure. Error detection is performed using error detection code CI for each horizontal data block.

As a result, the presence or absence of an error is detected for each data block in the horizontal direction, and an error flag X is set on all data included in the data block in which an error has been detected, as shown in FIG.

Next, for each data block in the vertical direction as shown by the dashed-dotted line in B in the figure, error correction is performed using the error correction code C2 for the data included therein, in which the error flag X has been set. Errors are corrected and the digital data is decoded.

However, when such an error correction decoding method is applied to a system that uses, for example, a magnetic recording/reproducing device as a transmission path, the occurrence rate of errors due to drop-out on the transmission path is high, so that the data block in which an error is detected is The number of will increase. For this reason, the number of data with error flag X set during error correction increases, and there is a high possibility that error correction using error correction code C2 becomes impossible.

On the other hand, when recording an audio signal in a digital VTR, for example, as shown in FIG. It has been considered to repeatedly record the same data signal on one acoustic signal recording section. According to this, if an error is not detected in one of the data blocks from the two recording sections during reproduction, that data block can be used, and the number of data blocks in which an error is detected can be substantially reduced. .

Therefore, an apparatus as shown in FIG. 4 was devised as an error correction decoding apparatus for data signals recorded in this manner.

In the figure, data signals from two recording sections of acoustic signal A are sequentially supplied to an input terminal (11), and this input terminal (
11) is supplied to an error detection decoder (12) using an error detection code CI, and an error flag X is formed when an error is detected. A memory in which the formed error flag X and data D are provided in parallel (
13a) Commonly supplied to (13b).

In addition, a control signal for switching between the first and second reproduction when the two recording sections mentioned above are sequentially reproduced is supplied to the write control circuit (15) through the terminal (14), and the write control circuit (15) is switched by this control signal. The control signal is memo'J (13a) (
13b) is supplied to the write control terminal -E.

As a result, data D and error flag X from one of the two recording sections are written to the memory (13a), and
Data D from the other side and error flag X are stored in the memory (13
b).

Furthermore, the corresponding data D is sequentially read out from these memories (13a) and (13b) and sent to the data selector (16).
), and the corresponding error flag X is also supplied to the selector control circuit (17). When there is no error flag X in both, for example, data D from the memory (13a) is selected and supplied to the data input of the error correction decoder (18) using the error correction code C2, and only one of the data has an error flag X. If there is, data D from the memory without the error flag X is selected and supplied to the decoder (I8). On the other hand, when both have error flags X, for example, data D from the memory (13a) is selected and supplied to the decoder (18), and the error flag X from the control circuit (17) is ) is fed to the error flag input.

In this way, if no error is detected in one of the data D from the two recording sections, that data D is sent to the decoder (18
), and a signal subjected to error correction decoding by this decoder (18) is taken out to an output terminal (19).

However, in this device, a memory for storing data D and error flag X is required for each transmission path.
Therefore, there was a risk that the configuration of the device would become extremely complicated and large.

By the way, for example, in the above-mentioned digital VTR, there are cases where the entire video signal (■) and the two audio signals A at both ends are time-axis compressed and recorded and played back within one field period, or when the video signal (■) is recorded and played back in one field. If the recording and reproduction of the audio signal A is performed during the field period and the overramp period before and after that, the recording and reproduction of the two audio signals A are performed in different periods, and when reproducing one and the other. The other reproduced signals are to be extracted sequentially.

This application focuses on this point.

[Problem that the invention seeks to solve]

As described above, in the conventional technology, since a memory or the like is provided for each transmission path, there are problems such as the overall configuration of the device becomes extremely complicated and large.

[Means for solving problems]

The present invention provides a method for decoding a signal obtained by repeatedly transmitting a data signal to which an error detection code generated from this data is added together with data D, two or more times. )) for detecting errors using the above error detection code (decoder (2)
), writes the data in the first transmitted data signal and the error flag X detected by the error detection to the memory (3), and writes the data transmitted later (to the terminal (4)). The above-mentioned memory is rewritten according to the above-mentioned error flag in which the above-mentioned error in the signal is detected (write control circuit (5)
) is an error correction decoding device.

[Effect]

According to this, by rewriting the memory with data without an error flag among the data signals transmitted later, that data will be left in the memory when no error is detected on one side, and one memory The same operation as before is performed, and the configuration of the device can be made simple and small.

〔Example〕

In FIG. 1, data signals sequentially extracted from a plurality of transmission paths, such as the two audio signal recording units in the above-mentioned digital VTR, are supplied to an input terminal (1);
A data signal from this input terminal (1) is supplied to an error detection decoder (2) using an error detection code C1. The data D from this decoder (2) and the error flag X detected for each data block described above are stored in the memory (3).
).

In addition, the write control circuit includes a control signal supplied to the terminal (4) for switching between the first and second reproductions when the above-mentioned two recordings are sequentially reproduced, and an error flag X from the decoder (2). (5), and in this control circuit (5), a write control circuit signal is formed during the entire period of the first reproduction and a period without error flag X of the subsequent reproduction, and this write control signal is stored in the memory. January 3) is supplied to the write control terminal WE.

As a result, in the memo January 3), the data D and error flag X of the first data signal are all written once, and only the data D without the error flag X of the subsequent data signal is rewritten. Therefore, in the memo January 3), the first data signal has an error flag X, and the later data signal has data D without an error flag For data D that does not have an error flag X and has an error flag X in a later data signal, the first data D that does not have an error flag X is left, and when no error is detected on either side, that data D is left.

Therefore, the data D from this memory (3) and the error flag X are sent to an error correction decoder (6) using an error correction code C2.
, error correction decoding similar to the conventional one is performed, and the error correction decoded signal is taken out to the output terminal (7).

In this way, the data signal supplied to the input terminal <11 is subjected to error correction, etc., and then taken out to the output terminal (7), but according to the above-mentioned device, errors in the data signal transmitted later are detected. By rewriting the memory with data without a flag, the data will remain in the memory even if an error is not detected on one side, and the same operation as before can be performed with one memory, making the device simpler and smaller. can do.

In addition, in the above-mentioned device, the conventional data selector (16
) and selector control circuit (17) can also be omitted,
The configuration of the device can be further simplified.

Furthermore, in the above-described apparatus, the decoder (2) may also have some error correction capability.

Furthermore, in the above-described apparatus, the number of data signal transmission paths may be three or more, and in that case, the above-described operation can be repeated.

〔Effect of the invention〕

According to this invention, by rewriting the memory with data without an error flag among the data signals transmitted later, the data is left in the memory when no error is detected on one side, and one The memory now performs the same operations as before, making it possible to simplify and downsize the device configuration.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an example of a device for realizing the present invention,
FIGS. 2 to 4 are diagrams for explaining conventional techniques. (1) is an input terminal, (2) is an error detection decoder, (3)
is the memory, (4) is the control terminal, (5) is the write control circuit,
(6) is an error correction decoder, and (7) is an output terminal.

Claims (1)

[Claims] In decoding a signal obtained by repeatedly transmitting a data signal to which an error detection code generated from the data is added together with the data, the error detection is performed on the transmitted data signal. It has means for performing error detection using a code, and writes the data in the first transmitted data signal and the error flag detected by the error detection in the memory, and also writes the data in the data signal transmitted later. An error correction decoding device that rewrites the memory according to the detected error flag.