JP3282551B2 - Digital information recording method and recording apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information signal recording method , and more particularly to a digital information recording method and recording method suitable for recording audio and video inputted as fixed-length packets. Related to the device.

[0002]

2. Description of the Related Art The Journal of the Institute of Television Engineers of Japan Vol. 47, No. 4 (1.
993) as described on pages 494 to 497,
A system has been considered in which digital software such as audio and video is transmitted via radio waves and cables, and recorded at homes.

[0003]

When inputting audio or video digital software in the above-mentioned prior art, it is conceivable that the input digital signal has a fixed-length packet configuration.

[0004] For example, as shown in FIG.
And an input digital signal 40 comprising an audio signal 43
, A header-41 is added to the packet to form one packet of 188 bytes. In each packet, the header-41 includes a 1-byte synchronization signal 44,
The remaining data section 46 may be a video signal 42 or an audio signal 43 or additional information (not shown).

In a recording apparatus, an input signal is generally recorded on a recording medium by dividing the input signal into fixed-length blocks.

For example, in a digital VTR for consumer use, as shown in FIG.
0, 3 byte ID signal 51, 77 byte data 54
Alternatively, one block is recorded by 90 bytes of C2 parity 52 for error correction and C1 parity 53 of 8 bytes for error correction.

The digital signal 40 shown in FIG. 3 is converted to a consumer digital VTR having the recording format of FIG.
When recording by the method, the packet length of the input signal is different from the block length of the recording signal.

In a conventional recording apparatus, when recording a signal having a packet length different from the block length of a recording signal, the packet must be divided irregularly, and the synchronous relationship between the packet and the block cannot be maintained. There is a problem that block management becomes impossible and it becomes difficult to determine a variable speed reproduction area in variable speed reproduction.

An object of the present invention is to solve such a problem,
It is an object of the present invention to provide a digital information recording method and a recording apparatus capable of recording a digital signal having a packet length different from the block length of a recording signal, by regularly dividing the recording signal into block lengths of the recording signal.

[0010]

In order to achieve the above object, in a recording method for recording a digital signal, which is composed of a packet of a data and inputted, on a recording medium in units of blocks, the method includes the steps of : A de
Packet with L data added to the data (however,
(A + L) is an even number, and the data included in the m pieces of the extended packets is divided into n blocks (where (a + L) ×
m / n is a natural number, and a, m, and n are natural numbers. The data divided into the blocks includes j (j) including at least a block number for identifying the n blocks. It is recorded by adding the data of a natural number).

[0011]

The ratio between the data amount of m packets and the number of data that can be recorded in each block of the recording signal is a simple integer ratio (m / m).
n), the data of m packets can be completely recorded in n blocks, the block management of the recording signal for the packet of the input signal can be easily performed, and at least the block number By adding j pieces of data including, it is possible to reliably identify n blocks.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a recording format of a digital information recording apparatus according to the present invention. 4, reference numerals 105 to 109 denote respective recording blocks, reference numeral 50 denotes a recording synchronization signal, reference numeral 51 denotes an ID signal, reference numeral 102 denotes a block ID indicating a block number or the like, reference numeral 103 denotes data, and reference numeral 53 denotes a C1 parity. Is the same as the block configuration in the recording format. Also, 114 and 115 are headers, 112 and 113 in the packet shown in FIG.
Is additional data consisting of 2 bytes.

Here, the data of two packets of the input digital signal 40 having the packet structure shown in FIG. 3 is divided into five blocks.

That is, the head of the data portion (77 bytes of the data 54 in FIG. 3) of each block is used as a block ID for identification of 5 blocks, and the remaining 76-byte portion 103 contains two packets. Are arranged.
The first packet is 36 bytes in the first half 110 of block 0 (105), block 1 (106), and block 2 (107), 38 bytes in the second half 111 of block 2 (107), block 3 (108), and block 4 2 in (109)
Put the packet eyes. Further, by adding 2 bytes each of the additional data 112 after the first packet and the additional data 113 after the second packet, all five blocks can be converted into a packet signal of 76 bytes. The recording format can be completed in two packets and five blocks.

The additional data 112 and 113 need only add two bytes after each packet signal.
The same operation is performed for each block, and the operation can be performed with simple processing.

In general, recording with additional data has the disadvantage of increasing redundancy, but adding several bytes as in the present embodiment does not cause a substantial problem. Rather, by facilitating the management between the packets of the input signal and the blocks of the recording signal, a very large effect can be obtained when selecting a reproduction area, for example, at the time of variable speed reproduction. . If the present invention is not used, the synchronous relationship between the packet and the block cannot be maintained, and the management between the packet and the block becomes practically impossible.

Further, by providing the additional data 112 and 113 with parity for error correction, it is effective to improve the reliability of a reproduced signal in recording and reproducing. This parity is represented by a CRC code, a lead-Solomon code, etc.
An error correction code used in normal digital transmission may be used. Also, as this correction code block, 1
It may be completed in packets, completed in 5 blocks of 2 packets, or completed in 2 × n packet−5 × n block (n is a natural number) block.

Incidentally, the additional data 112 and 113 are
2 blocks 2 (107) as 4 bytes in 4 locations
Of the center 112 of the
However, in this case, it is necessary to change the processing in the odd-numbered packet and the even-numbered packet, so that there is a disadvantage that the processing becomes complicated. Therefore, it is better to use the present invention. .

FIG. 2 shows a recording / reproducing apparatus for a digital information signal having a recording format according to the present invention. 3, reference numeral 300 denotes a recording processing circuit; 32, an input terminal for inputting an input packet signal 40;
Header-detection circuit for detecting 1, 114, 115, 21
Is a data addition circuit for adding additional data 112 and 113, 22 is a storage circuit, 35 is an address generation circuit for controlling the address of the storage circuit 22, and 37 is a block ID 102.
, A coding circuit 23 for adding parities 52 and 53, a modulation circuit 24,
25 is a switch, 30 is a rotary head, and 31 is a magnetic tape. Further, 301 is a reproduction processing circuit, 26 is a demodulation circuit, 27 is an error correction circuit, 28 is a block number detection circuit, 29 is a storage circuit, 34 is an address generation circuit for controlling an address of the storage circuit 29, and 33 is a reproduced packet signal. Output terminal.

At the time of recording, the headers 114 and 115 are detected from the packet signal 40 input at the input terminal 32 and the address generation circuit 35 is controlled so that the data is stored in the format shown in FIG. A write address for the circuit 22 is generated. Further, additional data is written to the positions 112 and 113 using the data adding circuit 21. This data may be fixed data, or may be parity for error correction as described above. When writing parity,
The data addition circuit 21 functions as a parity addition encoding circuit. The block ID 102 is added by the block number adding circuit 37. The signal once stored in the storage circuit 22 is read out again, a C2 parity 52 and a C1 parity 53 are added by the encoding circuit 23, and further, the recording synchronization signal 50 and the ID signal b51 are added by the modulation circuit 24.
And the like, and a modulation process, and is recorded on the magnetic tape 31 by the rotary head 30 via the switch 25.

At the time of reproduction, a reproduction signal reproduced by the rotary head 30 is sent to the demodulation circuit 26 via the switch 25 to detect the recording synchronizing signal 50 and the like. The error is corrected using the C2 parity 52 and written into the storage circuit 29. At this time, the block ID is detected by the block number detection circuit 28.
By detecting 102 and controlling the address generation circuit 34, the write state of the storage circuit 29 is reproduced to the same state as the recording format of FIG. Under the control of the address generation circuit 34, a signal excluding the additional data 112 and 113 is read out of the signals stored in the storage circuit 29, and the packet signal 40 is reproduced and output from the output terminal 33.

Further, as additional data 112 and 113,
When parity is used, as shown in FIG. 5, by detecting and correcting errors by the parity detection circuit 36, the reliability of the reproduced signal can be improved.

In FIG. 3, the synchronization signal 44 of the 4-byte header 41 is predetermined fixed data, and therefore need not always be recorded on the tape 31.

FIG. 6 shows the recording format in this case. The headers -162 and 163 have only three bytes of the header information 45 shown in FIG.
0 and 161 are 3 bytes. When the additional data is some kind of information such as parity, the amount of information increases, and in the case of parity in particular, there is an effect that the detection capability and the correction capability in parity detection are improved.

FIG. 7 shows a block diagram of a recording / reproducing apparatus for this format.

At the time of recording, the address generation circuit 35 functions so that the signal other than the synchronization signal 41 among the input packet signals 40 is stored in the storage circuit 22.

At the time of reproduction, a synchronizing signal 41 is added to the signal read from the storage circuit 29 by the synchronizing signal adding circuit 38 to reproduce the same packet structure as the packet signal 40 and output from the output terminal 33. .

As described above, the additional data 112, 1
13, 160 and 161 can be used as parity for error detection and correction. In this case, the larger the number of data, the higher the capability. Therefore, block ID1
By omitting 02, the amount of additional data may be increased.

FIG. 8 shows the recording format in this case. In the figure, reference numeral 180 denotes a macro synchronization signal indicating that the block is at the head of block 0 (105). The headers -162 and 163 are 3 bits from which the synchronization signal 44 is deleted, as in FIG. The additional data 181 and 182 have 5 bits, and when used as parity, the detection capability and correction capability can be improved.

The addition of the macro synchronization signal 180 may be performed by either the data adding circuit 21 or the block number adding circuit 37.

In the above description, the additional data at the time of recording has been described.
The addition of the data 112 and 113 is performed at the time of writing to the storage circuit 22 and the deletion of the additional data 112 and 113 at the time of reading is performed at the time of reading the storage circuit 29. However, the reverse operation may be performed. That is, additional data 112 and 11 at the time of recording
3 may be added when the storage circuit 22 is read, and the additional data 112 and 113 during reproduction may be deleted when the storage circuit 29 is written.

Further, the addition of the block ID 102 at the time of recording by the block number adding circuit 37 is performed at the time of reading the storage circuit 22, but may be performed at the time of writing to the storage circuit 22.

Further, it has a block length different from that of FIG.
The present invention can be used in a recording apparatus having a recording format as shown in FIG. In FIG.
The data section 84 has 112 bytes. FIG. 9 shows packet division in this case. In this case, 4 packets-7 blocks are completed. 8-byte additional data 215 to 218 is added to each packet. This additional data may be used as parity.

[0035]

According to the present invention, in a recording method and a recording apparatus for recording a digital signal having a fixed-length packet structure, a digital signal having a packet length different from the block length of the recording signal is regularly recorded. Recording can be performed by dividing the signal into block lengths, and a synchronous relationship between packets and blocks can be maintained.

The use of parity for error detection or error correction of data contained in a packet as data to be added has the effect of improving the reliability of data during recording and reproduction.

[Brief description of the drawings]

FIG. 1 is a format diagram showing an embodiment of a digital information recording system according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a digital information recording device according to the present invention.

FIG. 3 is a diagram illustrating a packet structure of an input signal.

FIG. 4 is a diagram illustrating an example of a recording format of the recording apparatus.

FIG. 5 is a block diagram showing another configuration example of the digital information recording device according to the present invention.

FIG. 6 is a format diagram showing another embodiment of the digital information recording system according to the present invention.

FIG. 7 is a block diagram showing another configuration example of the digital information recording device according to the present invention.

FIG. 8 is a format diagram showing another embodiment of the digital information recording system according to the present invention.

FIG. 9 is a diagram illustrating another example of the recording format of the recording apparatus.

FIG. 10 is a format diagram showing another embodiment of the digital information recording system according to the present invention.

[Explanation of symbols]

20: header detection circuit, 21: data addition circuit, 28
... Block number detection circuit, 35 ... Address generation circuit, 3
6 ... Parity detection circuit, 37 ... Block number adding circuit,
38: synchronization signal adding circuit, 40: input packet signal, 4
1 ... header, 44 ... sync signal, 50 ... recording sync signal,
51: ID signal, 54: Data, 102: Block I
D, 103 ... data, 112, 113 ... additional data, 1
14, 115 ... header, 160, 161 ... additional data
162, 163: header, 180: macro synchronization signal, 181, 182: additional data

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Takao Arai 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd. Image Media Research Laboratories 58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 20/12 H04N 5/92

Claims (2)

(57) [Claims] 1. A recording method for recording a digital signal, which is constituted by a packet of a data and inputted, on a recording medium in block units, is included in said one packet.
Enlarged packet with L data added to a data
(Where (a + L) is an even number), and the data included in the m pieces of the extended packets is divided into n blocks (where (a
+ L) × m / n is a natural number, and a, m, and n are natural numbers.
And the data divided into the respective blocks is recorded by adding j data (j is a natural number) including a block number for identifying at least the n blocks. Digital information recording method . 2. A method digital signals input to constitute a packet with a number of data, in a recording apparatus for recording on a recording medium in units of blocks, from the input means and the signal obtained by said input for inputting the digital signal the Packet
Head detecting means for detecting the head, and the detected packet
A data included in the one packet based on the head of
With L data added to the enlarged packet ((a +
L) is a first data adding means constituting an even number);
The data included in the m pieces of the enlarged packets generated by the first data adding means is divided into n blocks (where (a +
L) × m / n is a natural number, a, m, and n are natural numbers), and data for each block divided by the dividing means is used to identify at least the n blocks. j pieces containing block number (j is a natural number) recording for recording the second data adding means for adding data of the additional data in the second de <br/> over data adding means on the recording medium digital information recording apparatus characterized in that it comprises means.