JPH038176A - Method and device for verification in recording digital data - Google Patents

Abstract

PURPOSE:To perform the verification without increasing the number of times of an access of a buffer memory by executing the verification by comparing a first and a second verifying parities. CONSTITUTION:Data from a PCM signal input terminal 110 is inputted to a first parity generating circuit 131 through a buffer memory 109 and generates a verifying parity. The parity generated at every 1 frame is delayed by a delaying circuit 132 by the time corresponding to about 3 frames. A second parity generating circuit 133 also generates a second verifying parity against a reproduced PCM signal in the same way as the circuit 131. Subsequently, the parities from the circuits 132, 133 are compared by a comparing circuit 134, and in the case they do not coincide with each other, a verifying error signal is fetched to the outside from a terminal 135. In such a way, the verification can be executed without increasing the number of times of an access of the buffer memory.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a verification method and apparatus for digital data recording.

(Prior Art) Recent advances in magnetic recording technology have made it possible to realize magnetic recording and reproducing devices for high-density human bases. An example of this is a digital audio recorder (hereinafter abbreviated as DAT).

This is for recording and reproducing an audio signal, which has been converted into a digital signal by pulse code modulation (hereinafter abbreviated as PCM), onto a magnetic tape.

DAT uses the so-called helical scan azimuth recording method to record information at a high recording density of 61 kilobits per inch with a trunk pitch of 13.6 μm and a recording density of 61 kilobits per inch. For two hours, it is possible to record approximately 1.4 gigabytes of digital data.

For this reason, recently, it is being considered to use DAT not only for recording PCM audio signals (but also as a data recording device for computers, etc.).

FIG. 2(a) is a diagram showing an example of the configuration of a rotary head section of a DAT, and FIG. 2(b) is a diagram showing a recording track pattern on a magnetic tape by the rotary head.

The rotating drum 201 has four magnetic heads 202.20.
3.204.205 are attached and rotated in the direction shown by arrow B.

The magnetic heads 202 and 204 are read (reproduction) heads and have different azimuth angles. Further, the magnetic heads 203 and 205 are writing (recording) heads, and the recording head 203 is connected to the reproducing head 202.
The recording head 205 has an azimuth angle corresponding to that of the reproducing head 204.

The magnetic tape 206 is attached to the rotating drum 201 at its rotation angle of 9.
0'' and is transported in the direction shown by arrow A. As a result, a recording track pattern as shown in FIG. 2(b) is formed on the magnetic tape 206.

In the rotary magnetic head having such a configuration, during reproduction, recorded data is reproduced by the reproduction heads 202 and 204. Also, when recording, tc! 1 in recording head 203
IC truck! Immediately after M, the track is played back by the playback head 202, and immediately after the recording head 205 records the next one trunk, the track is played back by the playback head 204, thereby making it possible to monitor the playback simultaneously during data recording.

In a recording/reproducing device with a high recording density such as a DAT, the data error rate is relatively high, and high data reliability is ensured by using an error correction code based on coding theory.

In this method, redundant data called parity is recorded together with recorded data during recording, and during reproduction, the position where an error occurs and the correct value are calculated from the data and parity.

In DAT, one track is one unit of error correction, and parity for error correction processing is added to 2880 bytes of the digitized audio signal, and a total of 4096 bytes of data are recorded on one track.

According to such an error correction method with high correction ability, even if the error rate before correction is very bad at 10-2, the error rate after error correction is less than 10-11, so even at high recording density, the error rate is high. Gain reliability.

FIG. 3 is a diagram showing an example of the circuit configuration of the DAT. In this example, audio signals are recorded and reproduced using a magnetic head having the configuration shown in FIG.

A PCM signal encoded by an A/D converter (not shown) or the like is input to the PCM input terminal 110, and the PCM signal is temporarily stored in the buffer memory 109.

The PCM signal stored in the buffer memory 109 is read out by the recording system signal processing circuit 111, where it is added with parity and address information, search information (subcode), etc., and then digitally modulated. The signal is sent to the recording amplifier 112.

The recording amplifier 112 energizes the recording heads 203 and 205 with appropriate current and voltage according to the input digital signal, thereby recording the digital signal on the magnetic tape.

Next, the digital signals reproduced by the reproduction heads 202 and 204 are amplified and waveformed in the reproduction amplifier 123 and sent to the PLL 122. Note that the playback amplifier 123 has two playback heads 202 and 204,
A switch is included to select which side is in contact with the magnetic tape.

The PLL 122 reproduces a clock that follows fluctuations of the reproduced signal on the time axis. The reproduction signal processing circuit 121 receives and receives the reproduced signal and clock, performs decoding based on the parity, and then converts the signal into a PCM.
Output a signal. This PCM signal is transmitted to the PCM output terminal 12.
Output from 0 to the outside.

The drum control circuit 126 controls the motor drive circuit 127 so that the magnetic heads 202 to 205 rotate at a constant angular velocity.
to control the rotational speed of a drum motor (not shown).

The synchronization circuit 130 synchronizes the reproduction signal processing circuit 121 with the recording signal processing circuit 111 when simultaneously monitoring playback during recording, and when performing post-recording in which only a portion of the tape that has already been stored is rewritten. This is to synchronize the recording signal processing circuit 111 with the reproduction signal processing circuit 121.

Dubbing in DAT is used when only information such as a flag used for search is rewritten while leaving the audio signal intact.

The ATF detection circuit 124 extracts a tracking servo signal (ATF signal) from the reproduction signal output from the reproduction amplifier 123 and supplies it to the capstan control circuit 125 as a tracking error signal.

The capstan control circuit 125 refers to the tracking error signal output from the ATF detection circuit 124 so that the magnetic tape runs at a constant speed during recording, and so that the playback head correctly traces the recording track during playback. The motor drive circuit 127 is controlled to control the rotational speed of a capstan motor (not shown).

Such error correction codes and recording/reproducing apparatuses using error correction codes are discussed in Japanese Patent Laid-Open Publications No. 188314/1988 and No. 215013/1989.

By the way, very high reliability is required for computer storage devices, so after data is recorded, the recorded data is read out and checked to see if the read data matches the recorded data. Verification is performed.

When a recording defect is detected through verification, generally a retry is performed to record to the same portion again, or alternative processing is performed to record the data in that portion to another portion of the recording medium.

Verification in conventional magnetic disk devices and magnetic tape devices involves storing data to be recorded on a recording medium in a memory as well, and immediately after recording, reading out the data in the recorded portion and storing it in the memory. Compare it with the data you set,
In some cases, it is determined that recording has been performed normally when a match occurs, and in others, an error detection code called a cyclic redundancy code (hereinafter abbreviated as CRC) is used to check read data for errors.

FIG. 4 is a diagram for explaining an example of a verify method employed in a conventional magnetic disk device.

When storing data, as shown in Figure (a),
CR of original data 401 of a certain size to be recorded
C is calculated by the CRC calculation means 402 and added to the original data 401 to generate CRC-attached data 403,
Record this on a magnetic disk. The CRC is used not only during verification, which will be described later, but also for error detection during data reproduction.

Verification is performed by reproducing the CRC-attached data 403 immediately after recording, and the following method is known.

In the first method, as shown in FIG. 4(b), calculations for CRC calculation are performed on the data part of the CRC-attached data 404 read from the magnetic disk using the same method used during recording (402). The CRC which is the fft calculation result is compared with the read CRC (405). The verification result is output from the verify flag output terminal 407.

The second method is a method that does not use CRC, and is shown in the same figure (C
), the original data 401 is also held in the computer's memory during recording, and the CRC that reproduces it is
It is compared with the data section of the attached data 404 (406). The verification result is output from the verify flag output terminal 408.

(Problems to be Solved by the Invention) Since the DAT was originally a PCM audio recording and reproducing device for consumer use, it was sufficient to have a simultaneous playback monitoring function, and a verify function was not particularly necessary. However, when using this as an auxiliary storage device for a computer, it is necessary to perform verification to improve reliability as a storage device.

Furthermore, even when used as an audio signal recording device, a verify function may be required depending on its importance. However, when attempting to apply the above-described verification method to DAT, the following problems occur.

(1) In the method described with reference to FIG. 4(C) above, in which the original data is also held in the computer memory during recording and compared with the reproduced data, the number of accesses to the buffer memory 109 is It is necessary to read the original data twice: (1) to read the original data for recording on the magnetic tape, and (2) to read the original data to compare the original data with the reproduced data.

That is, in order to perform verification, the number of accesses to the buffer memory 109 must be increased by one in order to compare the original data and reproduced data.

However, unlike conventional magnetic disks and magnetic tapes, DAT uses complex error correction codes with high correction ability, so it requires a lot of attention to the buffer memory when encoding and decoding error correction codes. An access is being made and the buffer memory is nearly occupied.

Therefore, it is very difficult to increase the number of accesses to the buffer memory for verification.

(2) Furthermore, in the verification method shown in Figure 4(C), it is necessary to store the original data in memory and compare it with the reproduced data. A memory capacity of 8192 bytes or more is required, which poses a problem in terms of circuit integration.

(3) In addition, as in the verification method explained with reference to FIG.
If verification is performed based on the match, the above (1) and (2)
), but if no recording is performed at all due to foreign matter adhering to the head, the previously stored data with CRC will be played back and compared against this. Because of this, defects cannot be detected.

When recording data at a high recording density like DAT, the gap width of the magnetic head is very small, approximately 20 μm, and the head is easily clogged, so accidents like this where no recording is performed at all occur. There is a high possibility that this will occur. A similar situation also occurs due to disconnection or short circuit of the head.

SUMMARY OF THE INVENTION An object of the present invention is to provide a verification method and apparatus for digital data recording that solves the problems described below and enables highly reliable verification without increasing the number of accesses to a buffer memory. be.

(Means for Solving the Problems) In order to solve the above problems, the present invention takes the following measures.

(1) The first step based on the digital data to be recorded.
a first parity generating means for generating verify parity; a delay circuit for outputting the first verify parity after a scheduled time delay; a recording means for recording digital data on a magnetic recording medium; and a magnetic recording medium. a reproducing means for reproducing digital data recorded on the digital data; a second parity generating means for generating a second verify parity based on the reproduced digital data; and a first verify parity output from the delay circuit. and a second verifying parity outputted from the second parity generating means, and determining that correct recording has been performed when the first and second verifying parities are the same. I did it like that.

(2) The recording means added an error correction code to the digital data and recorded it, and the reproduction means corrected the digital data by 37 times based on the error correction code added to the digital data.

(3) At least one of the recording means and the reproducing means further includes means for reducing the correction ability of the error correction code during verification execution.

(Function) According to the configuration described above, the following effects are achieved.

(1) Since verification is performed by comparing the first verify parity and the second verify parity, the number of accesses to the buffer memory during verification is reduced by the number of times the original data is recorded on the magnetic tape. This is done only when reading, and verification can be performed without increasing the number of accesses.

Furthermore, since the verify parities are compared, a defect can be detected even if no recording is performed due to foreign matter adhering to the recording head.

Further, since the delay to cope with the time delay from recording to reproduction only needs to be applied to the verify parity, a large capacity memory is not required.

(2) Since a means for reducing the correction ability of the error correction code at the time of verification is provided, it becomes possible to detect errors within the range that can be corrected by the error correction code at the time of verification.

(Example) The present invention will be described in detail below with reference to the drawings.

In this embodiment, verification is realized in a magnetic tape recording/reproducing apparatus equipped with a rotary head as shown in FIG.

In order to perform verification, it is desirable to immediately read back the recorded data and compare it, so the configuration is such that the data can be read immediately after writing using two sets of recording heads and reproducing heads.

FIG. 5 shows the data recording format adopted by DAT. FIG. 5(a) shows the track format. One track is roughly divided into five areas, in order: subcode area, ATF area, data area, and ATF area.
Area and subcode area.

Note that the angle shown in each area is the angle at which the magnetic tape corresponding to each area is wrapped around the magnetic head.

Subcode areas are provided at both ends of the track, and record information used for access, such as track numbers. The data area is provided in the center of the track, and records data and parity for data error correction. Two ATF areas are provided between the data area and the subcode area, and a signal for tracking servo that controls the drum motor so that the magnetic head traces the center of the track during reproduction is recorded. The data area and subcode area are divided into blocks, with the data area having 128 blocks and the subcode area having 8 blocks each.
One block at a time.

FIG. 5(b) shows the structure of one block among the 128 blocks constituting the data area.

One block consists of 288 bits (36 bytes). A special signal called 5YNC indicating the beginning of a block is stored in the first byte, and by detecting this 5YNC, byte synchronization and block synchronization during playback are established.

The next 1 byte is an ID code, in which various flags related to the recording format are stored. Next is the block address, in which data indicating the number of the block among the data blocks with self-strength < 128g is stored. The next parity stores a bit-by-bit exclusive OR of the ID code and block address, and is used to detect errors in the ID code and block address.

The next 256 bits (32 bytes) store data and/or error correction code parity.

FIG. 6 is a diagram showing the format of an error correction code used in DAT. In particular, only 128 data blocks from one track are extracted and rearranged.

The vertical column at the left end of the figure is the brightest block (block number 0), and from left to right, block numbers 1, 2, and 3 are shown.
,...127. The data located at the top of one block is the first data, that is, the first byte following the parity (symbol number 0), and 32 bytes of data are sequentially arranged from top to bottom with symbol number 1.
They are lined up as 2.3,...31.

The first error correction code (hereinafter abbreviated as C1) is an error correction code that is completed for each track, that is, one block is one sequence, and is used to correct errors within the block. Of the 32 bytes, 28 bytes are data and 4 bytes are parity.
2, 28) Reed-Solomon code.

The part shown as 01 in FIG. 6 is this parity, and has the ability to detect errors of up to 4 bytes in one block. Alternatively, it is possible to correct errors of up to 2 bytes in one block.

The second error correction code (hereinafter abbreviated as C2) is for correcting errors in the horizontal direction in FIG. 6, that is, for correcting errors in a certain part of each of a plurality of blocks. is also performed for symbols with the same symbol number every four blocks.

For example, the block number is 0.4.8.12,...
Of the 32 blocks of 124 blocks, each symbol number is 0, and a total of 32 bytes constitutes one sequence of 02 blocks.

Similarly, the block numbers are C5, 9, 13,...125, and each symbol number is 0 data, 1 data, etc. There are 4 combinations of block numbers and 28 symbol numbers ( There are a total of 112 sequences (28×4) of C2 codes (excluding CI parity).

C2 contains the beginning of one series (corresponding to the left side in Figure 6)
A (32,26) Reed-Solomon code is used in which 13 bytes are data, the next 6 bytes are parity, and the next 13 bytes are data.

During encoding during recording, a C2 parity is generated from the recorded data, and then a 01 parity is generated from this recorded data and the C2 parity.

When encoding during playback, C1 parity is first encoded, and then C2 is encoded while referring to the previous 01 parity result.
Performs parity compounding. This results in a maximum burst correction capacity of 500 bytes or more.

FIG. 1 is a diagram showing the circuit configuration of a DAT which is an embodiment of the present invention, and the same reference numerals as in FIG. 3 represent the same or equivalent parts.

This embodiment implements verification in the conventional DAT shown in FIG.

The first parity generation circuit 131 receives PCM data input from the PCM signal input terminal 110 into the buffer memory 1.
09, generates a first verify parity for the recorded data, and outputs it.

Since this verifying parity does not need to have a correction ability, it is sufficient that it is simpler than the parity used as an error correction code in DAT, and its details will be explained later with reference to FIG. 8.

Generation of the first verify parity is performed for each frame in synchronization with the recording system signal processing circuit 111. One frame is a unit of recording and playback consisting of two tracks, and P
There is a capacity of 5760 bytes for CM data.

The delay circuit 132 is
The first verify parity generated for each frame is delayed by a time corresponding to approximately three frames. This time includes the processing time in the recording signal processing circuit 111 and the reproduction signal processing circuit 121, the recording head 203, 205, and the reproduction head 202, 204.
Attachment corresponds to the sum of the delay times caused by a 90'' misalignment.

The second parity generation circuit 133, like the first parity generation circuit 131, generates a second verify parity for the reproduced PCM signal.

Comparison circuit 134 compares the first and second verify parities output from delay circuit 132 and parity generation circuit 133, respectively, and outputs a verify error signal if they do not match. This verify error signal is taken out from the verify error signal output terminal 135.

FIG. 7 is a diagram showing the operation timing of this embodiment regarding verification, and the signals shown in (b) to (h) in the figure correspond to signals b-h shown in FIG. 1, respectively. .

FIG. 7(a) shows the frame synchronization signal FSYC of the recording system signal processing circuit 111. This signal has a period of one frame, and the first half of one frame is at a high level (hereinafter referred to as
(represented by "H"), the latter half is a low level (hereinafter represented by "L")
becomes.

FIG. 2B shows PCM data that is input to the input terminal 110 and then output from the buffer memory. This is P
Since it is a CM signal, it is manually input at a constant rate (192,000 bytes/second in this embodiment), but for convenience, in FIG. 7, each frame is shown with a delimiter and a frame number.

FIG. 4E shows the first verify parity generated and output by the first parity generation circuit 131 based on the recorded data. In this embodiment, the first verify parity is generated for each frame, and is output immediately after data input for one frame is completed. That is, the first verify parity, which is parity based on recording data, is generated in synchronization with FSYNC of the recording system.

(d) in the figure is a delayed output obtained by delaying the first verify parity (e) by the delay circuit 132. This is generated by the second parity generation circuit 133 based on the reproduced data, which will be described later, and is output. It is output at the same timing as the second verify parity (h).

In the delay circuit 132 of this embodiment, the recording system FSYN
A delay Δt1 of three cycles synchronized with C(a) and a delay Δt2 for synchronization with the rising edge of the reproduction system FSYNC(+) are provided.

FIG. 7(e) shows the recording signals given to the recording heads 203 and 205, in which "+" indicates the signal supplied to the recording head 203, and "-" indicates the signal supplied to the recording head 205. .

The recording signal (e) for one frame is subjected to predetermined signal processing by the signal processing circuit 111 (addition of error correction code,
Addition of search information, addition of tracking signal,
modulation, etc.), and after a time period equivalent to about 1.5 frames has elapsed from the beginning of the p-chi data (b), the magnetic head 2
03.205, two tracks were recorded.

It should be noted that since the period during which the recording head contacts the tape corresponds to 90'' of the drum 201, the recording signal is an intermittent signal.

FIG. 7(i) shows the frame synchronization signal FSYNC of the reproduction system. The playback system FSYNC is the playback head 202.204.
Since the mounting angles of the recording heads 203 and 205 on the drum 201 are different by 909 degrees, the FSYN of the recording system
The phase is delayed by 90 degrees with respect to C.

FIG. 7(r) shows reproduction signals detected by the reproduction heads 202 and 204. This corresponds to the recording signal (C) and is delayed by a time corresponding to the rotation angle of the drum 201 of 90 degrees with respect to the recording signal (e).

FIG. 7(g) shows output data output from the output terminal 120. This is obtained from the reproduced signal (f), and due to signal processing such as error correction by the reproduction system signal processing circuit 121, it is approximately 1.
It is output after a time period equivalent to 5 frames has elapsed. In the figure, like the PCM data (b), each frame is shown with a delimiter and a frame number.

FIG. 7(h) shows a second verify parity which is a parity based on reproduced data output from the second parity generation circuit 133. In this embodiment, the second verify parity is generated for each frame, and the generated parity is output immediately after output of one frame of data is completed.

In other words, the second verify parity is the F of the reproduction system.
Output in synchronization with SYNC. Here, verification can be performed by comparing the delayed first verification parity (d) with the second verification parity (11).

According to this embodiment, the number of accesses to the buffer memory during verification is only when reading the original data for recording on the magnetic tape, so verification can be performed without increasing the number of accesses. . Furthermore, since the parities are compared, it is possible to detect a defect even if no recording is performed due to foreign matter adhering to the recording head.

FIG. 8(a) is a diagram showing the configuration of the first and second parity generation circuits of this embodiment. Here, the parity for verification is generated using a cyclic redundant code using a generator polynomial.

In the initial state, the shift registers 810, 811, and 812 are all reset and 0'' is stored in them.

PCM data for recording or reproduction is serially input to the input terminal 801 . Input data is input to one input terminal of exclusive OR gate 814, and its output signal is input to 5-bit shift register 810. The output signal of the final stage of shift register 810 is input to one input terminal of exclusive OR gate 815, and its 8-output signal is input to 7-bit shift register 811.

The output signal of the final stage of the shift register 811 is inputted to one input terminal of the alistic OR gate 816, and the output signal is inputted to the 4-bit shift register 812. The output signal of the M final stage of the shift register 812 is fed back to the other input terminal of the exclusive OR gates 814, 815, and 816.

When the data processing for one frame is completed, a 16-bit parity is formed in the shift registers 810, 811, and 812. This is held by a latch 8]3 and outputted in 16 bits in parallel from a parity output terminal 805 as a verify parity.

Next, a reset signal is applied from a reset terminal (not shown) to generate parity for verifying the next frame, and the shift registers 810, 811, and 812 are reset.

FIG. 8(b) is a block diagram showing the configuration of another parity generation circuit. This uses arithmetic sum as the parity for verification.

The D flip-flop 824 has been reset and stores 0'' in the initial state.The input terminal 821 has
PCM data for recording or reproduction is input serially. The manual data is converted into 16-bit parallel data by a shift register 822 and input to one input terminal of an adder circuit 823.

The output signal of the D flip-flop 824 is input to the other input terminal of the adder circuit 823, and the adder circuit 823 outputs the sum of these and holds it in the D flip-flop 824 as new data.

The above operation is performed for every 16 bits of input data, and when the calculation for one frame of data is completed, the data in the D flip-flop 824 is held in the latch 825 and output from the parity output terminal 825.

In the above embodiment, the verification parity is a 16-pin CRC or an arithmetic sum parity, but it can also be used for error detection and correction using a 32-bit or other bit length CRC or Reed-Solomon code. It is also possible to use codes.

Further, in this embodiment, the verification parity is generated in units of one frame, but it is also possible to set other data lengths to one unit.

Furthermore, in this embodiment, the reproduction system signal processing circuit 12
Since verification is performed on data that has been subjected to error correction processing in accordance with No. 1, errors within the range that can be corrected by the error correction code cannot be detected at the time of verification.

However, at the time of verification, the error correction method in the reproduction system signal processing circuit 121 is switched to a correction method with low correction capability (in the limit, no correction), or the reproduction system signal processing circuit 121 switches the error correction method to a signal indicating the error correction status. (for example, error detection flag) and manage it,
Errors that can be corrected by error correction codes can also be detected during verification.

(Effects of the Invention) As is clear from the above description, the following effects are achieved according to the present invention.

(1) Since verification is performed by comparing the first verify parity and the second verify parity, verification can be performed without increasing the number of accesses to the buffer memory.

(2) Since the verify parities are compared, it is possible to detect a defect even if no recording is performed due to foreign matter adhering to the recording head.

(3) Since the delay to cope with the time delay from recording to reproduction only needs to be applied to the verify parity, a large capacity memory is not required.

(4) Since a means for reducing the correction ability of the error correction code during verification is provided, errors within the range that can be corrected by the error correction code can also be detected during verification.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of a DAT that is an embodiment of the present invention. FIG. 2(a) is a diagram showing an example of the configuration of a rotating head portion of a DAT. FIG. 2(b) is a diagram showing a recording track pattern on a magnetic tape. FIG. 3 is a diagram showing the circuit configuration of a conventional DAT. FIG. 4 is a diagram for explaining an example of a conventional verify method. FIG. 5 is a diagram showing a data recording format adopted by DAT. FIG. 6 is a diagram showing the format of an error correction code used in DAT. FIG. 7 is a diagram showing the operation timing of this embodiment regarding verification. FIG. 8 is a diagram showing the configuration of a parity generation circuit according to the present invention. 109... Buffer memory, 111... Recording system signal processing circuit, 112... Recording amplifier, 121... Playback system signal processing circuit, 122... PLL, 123... Playback amplifier, 124... ATF Circuit, 125... Capstan control circuit, 126... Drum control circuit, 127...
・Motor drive circuit, 130...Synchronization circuit, 131...
・First parity generation circuit, 132...Delay circuit, 1
33... Second parity generation circuit, 134... Comparison circuit, 201... Rotating drum, 202.204... Playback head, 203.205... Recording head

Claims (4)

[Claims] (1) A verification method for recording digital data by forming diagonal tracks on a magnetic recording medium using a rotating head, in which a first verification parity is generated based on the digital data to be recorded; reproducing the digital data recorded on a magnetic recording medium; generating second verify parity based on the reproduced digital data in the same manner as the first verify parity generation; The first verify parity is delayed by a scheduled time so that the output timing of the first verify parity matches the output timing of the first verify parity, and these are compared, and the first and second verify parities are the same. A verification method for digital data recording, characterized in that it is determined that correct recording has been performed when . (2) In a verification device used when recording digital data by forming diagonal tracks on a magnetic recording medium using a rotating head, the first verification parity is determined based on the digital data to be recorded. a first parity generating means for generating parity; a recording means for recording the digital data on a magnetic recording medium; a reproducing means for reproducing the digital data recorded on the magnetic recording medium; , a second parity generating means that generates a second verify parity using the same method as the first verify parity generation; and an output timing of the first verify parity at the output timing of the second verify parity. a delay circuit that delays and outputs the first verify parity by a predetermined time so that the first verify parity is delayed and outputted by a predetermined time so that the first verify parity output from the delay circuit and the second verify parity output from the second parity generating means match; and means for generating a determination output by comparing the first and second verify parities, and determines that correct recording has been performed when the first and second verify parities are the same. Verification device for digital data recording. (3) The recording means adds an error correction code to digital data and records the same, and the reproduction means corrects the digital data based on the error correction code added to the reproduced digital data. A verification device for digital data recording according to claim 2. (4) The verification device for digital data recording according to claim 3, wherein the reproducing means further comprises means for reducing the correction ability by the error correction code during verification execution.