JPS61170962A - Recording and reproducing device of digital signal - Google Patents

Abstract

PURPOSE:To attain TBC processing without disturbing the order of reproduction data even if a digital signal is recorded or reproduced with the use of plural tracks by providing an address discontinuity detecting circuit for controlling a write address generating circuit composed of TBC memory. CONSTITUTION:Data reproduced on a magneti tape is written in the prescribed TBC memory area by a block address at every track, and read out in accordance with the block address specified by a TBC memory read address generating circuit 26 after the delay of the prescribed time. An error detecting circuit 27 checks the error of the reproduction data read out of the TBC memory 25, and an address discontinuity detecting circuit 29 decides the continuity of an address code with the aid of both an address code extracted from the block of the reproduction data read out of the TBC memory and an error flag in the error detecting circuit 27. Then the block address among TBC memory write addresses generated by a write address generating circuit 24 for writing the reproduction data to the TBC memory is controlled. Thus a correct reproduction data string can be obtained with a simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital signal recording and reproducing apparatus that converts an analog signal into a digital signal and records and reproduces the converted signal on a recording medium.

2. Description of the Related Art In recent years, in the audio field, the development of digital audio recorders (hereinafter referred to as DAT) that convert analog signals into digital signals and record them on magnetic tape has been progressing.

The signal processing technology used in the conventional DAT mentioned above will be explained below with reference to the drawings.

FIG. 5 shows an example of the currently proposed signal format recorded on magnetic tape.

In FIG. 6, 1 is an 11-bit synchronization signal, 2 is an address code, which in this example consists of 2 bits, and is sequentially o-o-o1-410-11-400-...
...take steps. 3 is a 3-bit/1-bit flag indicating recording conditions, etc., and 4 is the first audio data, which is 16 in this example.
Digital audio data made up of bits is made up of 96 bits for 6 words. 6 is a parity code for correcting errors in audio data, 6 is second audio data having the same configuration as the first audio data 4, and 7 is an error detection code for detecting the presence or absence of an error within a block. In this example, a cyclic code (hereinafter referred to as CRO) is used, and address codes 2 to 2 except synchronization signal 1 are used.
Errors in 261 pits up to 6 of the second audio data are detected. A total of 288 indicated by the above codes 1 to 7
Blocks are made up of bits.

FIG. 6 is a block diagram showing a reproduction circuit for processing a digital signal sequence (hereinafter referred to as "single Kr reproduction data") reproduced from a magnetic tape with the configuration shown in FIG. 5. 6th
In the figure, 8 is an input terminal into which reproduced data is input, and 9 is a demodulation circuit for returning the modulated reproduced data to the original NRZ signal.

10 is a synchronization detection circuit for detecting a synchronization signal from the reproduced signal (in this example, a pattern not found in the modulator is used as a synchronization signal, so the synchronization signal is extracted from the reproduction data before demodulation); 11 is a block using CRC; CRC check circuit for detecting errors in reproduced data excluding synchronization signals, 12ijCRC1;E, W4F>lr*tbi
-c. Yoa, offwaa, 7. . , - a delay circuit for delaying the reproduced data.

13 is an address code extraction circuit for extracting an address code from within a reproduced block; 14 is a τBG memory for eliminating the effects of wow-o-flutter, jitter, etc. on the reproduced data generated in the tape running system; 16 is a synchronization detection circuit 10
The synchronization signal detected by the address code extraction circuit 13
a write address generation circuit for generating a write address for playback data and error flags to the TBC memory 14 based on the address code output from the ORO check circuit 11 and the error flag output from the ORO check circuit 11;
16 is the TBC memory 14 based on the clock from the crystal.
17 is an error correction circuit for performing predetermined error correction based on the reproduced data and error flag read from the TBC memory 14; 1B is a capstan servo circuit for driving the capstan 19 that controls the running speed of the magnetic tape 2o based on the difference between the write address and read address to the τBe memory 14.O About the playback circuit configured as above The operation will be explained below.

First, reproduced data reproduced from the magnetic tape 20 is input to the input terminal 8, demodulated into an NRZ signal by the demodulation circuit 9, and a synchronization signal is detected by the synchronization detection circuit 10. Furthermore, the demodulated playback data is sent to the ORO check circuit 1.
In step 1, check for errors. In this case, as is clear from the block configuration in Figure 6, in order to determine whether there is an error in the program and to confirm the reliability of the address code, it is necessary to remove the synchronization signal from the program. all 27
7bi0. It is necessary to read the CjRO check circuit 13t/c. In order to perform this time adjustment, the delay circuit 12 delays the reproduced data for one program.

Further, the address code extraction circuit 13 separates and extracts only the address code from the demodulated reproduced data for one program. However, as mentioned above, the reliability of the address code extracted here can only be determined after a CRO check.

The write address generation unit 16 uses the synchronization signal separated and extracted by the synchronization detection circuit 1o as a reference to generate the program 1. It also generates a write address to the TBC memory 14 corresponding to the playback data in the memory.

A block address to be written to the TBO memory 14 is generated using the address code extracted by the address code extraction circuit 13 and the check output of the CRC check circuit 11.

In other words, for an address code determined to be correct by the CjRO check, that value is output as is as a write block address to the TBC memory 14, and if the address code is determined to be unreliable by the CRC check, the address code is Focusing on continuity, the address code value of the correct previous block is sequentially incremented and used as the write block address to the τTBC memory 14. Reproduction data passed through delay circuit 12 and CRC check circuit 11
The error flag which is the error detection output of is written into the TBC memory 14 according to the write address designated by the write address generation circuit 16. In this example, the TBC memory 14 has an address code "o" expressed by 2 bits.
It has a memory area of 4 blocks corresponding to 3j, and the written playback data and error flags are normally read out with crystal accuracy generated by the read address generation circuit 16 after about 2 blocks of time has elapsed. By reading out according to the address, the effects of wow, black, jiggling, etc. are removed.The reproduced data read out from the TBC memory 14 is subjected to a predetermined correction operation by the error correction circuit 17.On the other hand, , among the write address and read address supplied to the 1dTBc memory 14 by the capstan servo circuit, the magnetic tape 2G is controlled by the capstan 19 so that the phase relationship between the two is always constant, mainly based on the respective program address information.
control the running speed of the vehicle.

Writing and reading data in the TBC memory 14 will be described in detail below with reference to FIG. −
In Figure 7, the block address in the write address is the block address, and B is the C of the block containing each address code.
In the RC check result, if ○ is determined to be correct, × indicates that it is determined to be suspicious. Also, C is TB
It represents a block address among the read addresses of the C memory 14. In section 1 in FIG. 7, an error is detected in "2" of the program addresses written to the τBGj memory 14, and therefore the address code extracted from this program is unreliable. The write address generation circuit 16 generates the address code "2" following the correct address code "1" of the previous block as the address code of this program, and writes the data to the block area "2" of the TBC memory 14. I'm here. In FIG. 7, the pro-1 block address obtained by incrementing based on the correct address code value as described above instead of the original address code of the write block address is ``(2
)” and so on with 0. On the other hand, the read block address C is configured to be read after a time difference of about two blocks from the write block address. In reality, the Write Pro 1 Quadram is generated separately from the data played back from the magnetic tape, so it causes wow and flutter.

Including jitter components, the time difference between the two program addresses expands and contracts depending on their distribution, but as described above, the phase relationship is controlled by the capstan servo circuit 18 to almost guarantee it. It is being said.

Next, the error correction method will be briefly explained.

FIG. 8 shows an example of the arrangement of parity codes recorded on a tape. In digital recording, in order to efficiently correct playback data errors due to dropouts etc. that occur on magnetic tape, a data sequence for error correction consisting of multiple data and error correction codes, a so-called parity sequence, is separated on the tape. A method called interleaving is used. In FIG. 8, one parity word 12iI- is generated for six predetermined data words 1 to 6 to form one parity sequence, and each is placed in a block spaced apart by 8 blocks. .

Focusing on data word 1 (indicated by an x in Figure 8), which has a block with address code ``0'', there is a predetermined data word 2 included in the same address code ``o'' which is 8 blocks away, and which is further 8 blocks away. Predetermined data word 3 included in address code "o", a total of seven words, constitute one parity sequence 1. Similarly, the 8th
Parity series 2 consisting of the words marked with ○ shown in the figure,
Parity series 3 consisting of words marked with Δ
In this way, all the words form a parity series in a chain in the longitudinal direction of the tape. If the parity word is a simple parity code as an error correction code, ORO
In combination with error flags by checking,
It is possible to correct any one-word error that makes up the parity sequence.

Next, the relationship between address code and error correction ability will be explained. Let us take as an example a case where an error due to dropout or the like that occurs on a magnetic tape occurs continuously over 10 blocks. If the error occurs continuously for a long time,
Since accurate capstan servo control cannot be performed, the tape running speed during that period may be slower or faster than normal. In FIG. 9, when the tape running speed in the IU error section is slow, ■ is assumed to be fast, and when writing the playback data to the TBC memory, the address code extracted from the playback data is not used.
This shows a case in which block addresses to be written to the TBC memory are generated sequentially in units of 0.7 times. Figure 9 1
．． 1 In either case, the parity sequence in the block sequence read from the TBC memory is incorrect after the error section, and therefore not only is it impossible to perform a correct correction operation, but in some cases, incorrect correction may be performed, resulting in abnormal noise. It will end up being output. On the other hand, FIG. 10 shows a case where data is written to the TBC memory using an address code extracted from a block of reproduced data in response to the occurrence of a similar error. Figure 10 1.1 - Even in the case of misalignment - After the error section ends, it is correct again - When the correct playback data is obtained, the playback data from the TBC memory is written to the correct TBC memory area again. A correct time series is maintained, so error correction for error sections is also performed correctly. In order to obtain a prescribed correction ability, it is important to always maintain the original data time series, so in this example, the address code in the reproduced signal is used to write the reproduced data to the TBC memory. There is. (
(For example, Japanese Patent Application Laid-open No. 57-50307) Problems to be Solved by the Invention However, with the above configuration, particularly in an apparatus that performs digital recording by dividing into a large number of tracks, the reproduced data is divided into each track. Wow and flutter every time.
1 because it is independently affected by factors such as
It is impossible to multiplex the system's reproducing circuits for each track and share them, so a reproducing circuit for each track alone is required. For example, a recently proposed D-whip system using a compact cassette is configured to record two channels of digital audio signals using 20 channels, and also uses a CRC code as a block error detection code. Since the Reed-Solomon code is used, which increases the circuit scale, a disadvantage is that a complicated circuit is required to extract the address code from each track independently and check for errors before writing to the TBC memory. It had

In view of the above-mentioned problems, the present invention provides a digital signal recording and reproducing device that can perform TBC processing without disturbing the order of reproduced data with a simple circuit configuration even when recording and reproducing digital signals using a plurality of trucks. It provides:

Means for Solving the Problems To achieve this object, the digital signal recording/reproducing apparatus of the present invention includes a TBC memory, a write address generation circuit for supplying a write address for the TBC memory, and a write address generation circuit for supplying a write address for the TBC memory.
a read address generation circuit that supplies a read address of the C memory; an error detection circuit that detects the presence or absence of an error in at least an address code of the block read from the TBC memory; and an output of the error detection circuit and the Using the address code extracted from the block read from the TBC memory, the discontinuity is detected and the TBC
The address discontinuity detection circuit controls the write address generation circuit of the C memory.

Effect of the present invention With the above-described configuration, the reproduced data 1j that has been reproduced from the magnetic tape is stored in a predetermined TBC by a block address that is not directly related to the address code in the reproduced data specified by the TBC memory write address generation circuit.
written to the memory area and after a predetermined time delay, the TB
The C memory read address is read according to the program address specified by the read address generation circuit. The reproduced data read from the TBC memory is subjected to an error check in an error detection circuit to confirm the reliability of the address code. Change [
The continuity of the address code is determined by the address code extracted from the block of playback data read from the 1TBc memory by the address discontinuity detection circuit and the error flag which is the error check result by the error detection circuit. By controlling the block address of the τBG memory write address generated by the write address generation circuit for the playback data to the TBC memory, correct playback data string can be achieved with a simple circuit configuration even in a digital signal recording/playback device using multiple tracks. can be obtained.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a reproducing circuit in one embodiment of the present invention, and FIG. 2 is a waveform diagram thereof. In Figure 1, 21&
~21n is an input terminal into which playback data of trunk mill truck n is input, 22&~22n is a demodulation circuit, and 231L
-23n are synchronization detection circuits, which have the same configuration as the conventional example.

24 can be separated and extracted by the synchronization detection circuit of each track, and □
□j＄K＠）? -71m. 51 ar 7゜
- A write address generation circuit that generates a write address to the TBC memory, 26 is 4 for each track and track.
TBC memory with memory area for pro-tsuku, 26
ijT B A read address generation circuit for reading playback data from the C memory 26 in track order; 27 is a T
An erroneous V detection circuit detects whether or not there is an error in the reproduced data read from the BC memory in block units. 2B detects a predetermined error in the reproduced data read from the TBC memory according to the error flag from the error detection circuit. An error correction circuit 29 performs a correction operation, reads the error flag from the error detection circuit and the TBC memory, separates and extracts the address code from the packeted playback data, and determines its continuity;
This is an address discontinuity detection circuit that controls the write block address generated by the write address generation circuit 24 based on the determination result. Although not shown in FIG. 1, the structure of the capstan servo is the same as that of the conventional example.

The operation of the digital signal recording and reproducing apparatus configured as described above will be explained below.

The block configuration of the reproduction signal of each track is the same as that shown in FIG. 5 used in the explanation of the conventional example, and on the aNn track used for recording and reproduction, the processors that failed to record at the same time have the same address code. shall be.

The data recorded and reproduced in one division on the ILNn track is input to input terminals 212L to 21n.

Since the playback data at the time of input is affected by wow, flag and skew for each track, demodulation and synchronization detection are carried out exclusively for each track by the demodulation circuit 22 &...
22n and the synchronization detection circuits 23a to 23n. The write address generation circuit 24 generates an 'I' BC memory write address for the data in the program of each track based on the synchronization signal of each track, and also specifies a memory area for four blocks. A write block address common to each track is generated (the TBG write block address marked with a circle in FIG. 2) is generated. In this case, the write block address has a direct correspondence with the address code in the block to be written. The playback data is written to the designated memory area in a time-division manner for each track, and after a time delay of approximately 2 blocks, the read address (O as the TBG read address in FIG. 2) is supplied from the read address circuit 26. ) is read out into tracks according to the following. The situation is shown in the waveform diagram of FIG. In other words, the playback data at the stage of writing to the TBC memory 26 is input in parallel to each truck, but
By performing time axis compression, reproduced data can be read out from the TBC memory 25 in track serial format. The error detection circuit 271/i: determines whether or not there is an error in the t''L reproduced data that is read out in track serial, and outputs an error pufferfish, and the error correction circuit 28 performs a predetermined error correction operation on the reproduced data according to the error flag. On the other hand, the address discontinuity detection circuit 29 determines the continuity of the error blowfish and the address code extracted from the block read from the TBC memory 26, and determines the write address according to the determination result. The write block address value generated by the generation circuit 24 is controlled.

An example of the configuration of the address discontinuity detection circuit 29 is shown in FIG.

In FIG. 3, reference numeral 30 denotes an address code predictor, which presets an error-free address code extracted from the block read from the block read out from the cTBc memory 26 only once at the start of data reproduction, and thereafter the reproduction state is changed. During the continuous period, a predicted address code is generated that is sequentially incremented by one step per plotter. 31 is an address code comparator which receives the predicted address code from the address code predictor 3o and the address code extracted from the block read from the TBC memory 26, and detects a difference between the address values. 32 is an AND gate that gates the comparison output of the address code comparator 31 using an error flag. In other words, the comparison output of the address code comparator 31 is TB (j).The TBG write address is generated only when there is no error in the block read from the memory 26 and the extracted address code is correct.
- Used as a control signal to the circuit.

The operation of the above embodiment will be described below using FIG. 4, taking as an example a case where errors occur continuously. Figure 4 1
It is assumed that errors occur continuously in the error section shown in the VC, and during that time the capstan servo is disturbed and the tape running speed becomes slower than in a steady state. Outside the error zone, TB is generated according to the write block address generated by the write address generation circuit 24 as shown in FIG.
Reproduction data is written to the corresponding block area of the C memory 26 for each track. Even in the error section, the write program address is generated by sequentially incrementing the address. Even after normal playback data is restored, the continuity of the write block addresses is maintained for several blocks. On the other hand, the reproduced data read from the TBC memory 26 is sequentially track-serially checked for errors in the program data of each track by the error detection circuit 27, and the address code extracted from the block by the address code comparator 31. address code predictor 3
A comparison is made with the predicted address code which is the output of o. The address code predictor 30 is preset with the correct address code value at the start of data reproduction, and is incremented sequentially thereafter, so while the normal program sequence is being read from the TBC memory 25, the predicted address code and the actual TB ( Since the address code value extracted from the block read from the memory 26 matches unless there is an error in the program, no address discontinuity is detected.Next, the error period ends at 1VC in FIG. 7
Considering the case where a disturbance occurs in the column, when the correct playback data is read from the TBC memory 25, the address code "o" extracted from the error-free block is different from the predicted address code "1". is detected by the address code comparator 31. Therefore, the write block address generated by the write address generation circuit 24 is changed from "■" to "■" by the address discontinuity detection output, and is incremented sequentially thereafter. Therefore, the block sequence of reproduced data read from the TBC memory 26 can be restored to a normal block sequence in two cycles after the end of the error period, and errors can be corrected in the correct sequence.

In FIG. 4, it is assumed that the tape running speed becomes faster than the steady state in the error section. In this case, the address code value of the error-free program read from the TBG memory 25 after the end of one error period is "2", while the predicted address code value is "1".
The write block address is changed from "■" to "■" by the address discontinuity detection output, so that the block sequence of the playback data read from the TBC memory 26 becomes a normal block sequence in 4 blocks after the end of the error section. He is back.

As described above, according to this embodiment, the address code is separated and extracted from the reproduced data read from the TBO memory 26, the presence or absence of an error is determined by the error detection circuit 27, and the discontinuity of the address code is detected by the address discontinuity detection circuit 27. TB detected by and generated by the write address generation circuit 24
Even in a digital signal recording and reproducing device that records and reproduces data by dividing it into a plurality of tracks by controlling the write program/1 address to the C memory 26, an address code separation/extraction and error detection circuit is provided for each track. The continuity of the reproduced data string can be ensured with a simple configuration without any problems, and therefore correct error correction is always guaranteed. Furthermore, the reproduced data delay circuit (12 in Fig. 6), which is indispensable in the conventional method of detecting the presence or absence of an error before writing the reproduced data to the TBC memory, until the detection of an error υ, which is rare, is no longer necessary, and the demodulated data is Since data can be directly written to the TBC memory without time delay, it is possible to simplify the circuit not only when using multiple tracks but also in a digital signal recording and reproducing apparatus that records and reproduces data on a single track.

In this embodiment, since the reproduced data is read out from the TBC memory 26 in track order, the extracted address -
Do and -Rahula, 7g also Tora, -Results of only a few minutes will be obtained. In this case, since each track of programs and programs recorded at the same time has the same address code, the address discontinuity detection result will be the same for all tracks unless an error is overlooked. Therefore, the error-free track/work results may be used as representative values for all tracks, but in order to further improve reliability, the results for all tracks may be subjected to majority voting and used.

Furthermore, although a 2-bit address code is used in this embodiment, the reliability of discontinuity detection improves when the number of bits is larger.

In addition, in this embodiment, the TBG mesori area is set to 4 blocks, so the range of write program addresses that can be controlled is explained in terms of 1 program address, but this can be expanded accordingly if the t'1TBc memory area is expanded. It is possible to do so. Also, once the control by address discontinuity detection is
After performing this on the G write block address, the capstan servo gradually restores the phase relationship between the write block address and the read block address to the original normal phase, so that playback before and after the continuous error period according to this embodiment is possible. You can normalize the data blog sequence as many times as you like.

Further, although this embodiment has been described by taking as an example a digital signal recording/reproducing apparatus using magnetic tape, it goes without saying that the recording medium is not limited to magnetic tape and can be applied to a wide range of digital signal recording.

Furthermore, the error detection code is not limited to a single KCRC code.

Effects of the Invention As described above, the present invention includes a TBC memory, a write address generation circuit that generates a write address for the TBC memory, a read address generation circuit that generates a read address for the TBC memory, and a write address generation circuit that generates a read address for the TBC memory. an error detection circuit that detects the presence or absence of an error in at least an address code among the programmed programs; and an error detection circuit that detects the presence or absence of an error in the address code; By providing an address discontinuity detection circuit that detects the discontinuity of the TBCi memory and controls the write address generation circuit of the TBCi memory, f'1TB can be used especially in a digital recording and reproducing apparatus that performs recording and reproduction using a plurality of tracks.
Address code extraction and error detection circuit for each track independently before writing playback data to C memory. Furthermore, there is no need to provide a delay circuit for playback data at the time of error detection, and address code extraction and error detection for all tracks can be performed with one circuit. By doing this and maintaining the order of the reproduced data string, the original error correction ability can be secured. Therefore, great effects can be achieved in ensuring reliability, downsizing, and cost reduction of the equipment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a reproducing circuit of a digital signal recording/reproducing apparatus in an embodiment of the present invention, FIG. 2 is a waveform diagram in the block diagram of FIG. 1, and FIG. 3 is a block diagram of a reproducing circuit in an embodiment of the present invention. A block diagram of the address discontinuity detection circuit, FIG. 4 is a waveform diagram at the time of continuous errors in an embodiment of the present invention, FIG. 6 is a signal configuration diagram in the conventional example, and FIG. 6 is a digital signal recording and reproducing in the conventional example. A block diagram of the reproduction circuit of the device, FIG. 7 is a waveform diagram showing the TBC memory write block address and read block address in the conventional example, FIG. 8 is a layout diagram of the parity code in the conventional example, and FIG. 9 is a waveform diagram showing the TBC memory write block address and read block address in the conventional example. FIG. 10 is a waveform diagram of a temporary continuous error when an address code is not used to write data to the TBC memory. FIG. 10 is a waveform diagram of a temporary continuous error when an address code is used to write data to the TBC memory in a conventional example. . 24...Write address generation circuit, 26...
... TBC memory, 26 ... Read address generation circuit, 27 ... Error detection circuit, 28.
...Address discontinuity detection circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure bama knee-g-mo 15” = razura: ku C and body-?) qko regret-・lW!i
beroto

Claims (2)

[Claims] (1) A digital block consisting of digital data reproduced from a recording medium and divided into at least a fixed number, an address code that circulates continuously, and an error detection code that detects at least errors in the address code. A time base correction memory (hereinafter referred to as TBC memory) that writes and reads a signal sequence, a write address generation circuit that generates a write address for the TBC memory, and a read address generation circuit that generates a read address for the TBC memory. an error detection circuit for detecting the presence or absence of an error in at least the address code among the blocks read from the TBC memory; A digital signal recording and reproducing apparatus comprising: an address discontinuity detection circuit that detects discontinuity of the address code using an address code and controls a write address generation circuit of the TBC memory. (2) The address discontinuity detection circuit includes an address code predictor that generates a predicted address code that cycles continuously from the address code value of a predetermined block, and an address code value extracted from the block read from the TBC memory. and the predicted address code value, and a logic circuit to which the comparison output of the address code comparator and the error detection circuit output are input. The digital signal recording and reproducing device described in 2.