JPH04143969A - Digital recording/reproducing device - Google Patents

Abstract

PURPOSE:To execute the recording/reproduction with high reliability by recording sub-information in the same area as main information, executing encoding of an error correction together with the main information and recording it, and selecting the sub-information of one track, when a result of correction and a pattern of reproducing sub-information coincide with each other at the time of reproduction. CONSTITUTION:On planes No2, No4, a free area of 16 symbols are provided, respectively, an ID is recorder therein, and by executing double encoding of C1 and C2, reliability is enhanced. In a recording system, an audio signal from a terminal 101, and an ID generated by an ID generating circuit 105 are stored in a memory 102, and encoding C1, C2 is executed by an encoding circuit 106, it is read out in a prescribed sequence from a terminal 107 and after a coincidence is detected, it is recorded in a tape. In a reproducing system, a reproducing audio signal and the ID are stored in a memory 112, based on an output of an address generating circuit 113, pass through an error correcting circuit 116 and when a correction is impossible, a flag is put thereto, and after the correction processing, audio information passes through a coincidence detection and is outputted from a terminal 110. The ID and the flag are inputted to an ID decoder 115, and that of high reliability is selected and outputted to a terminal 114. The system is controlled by the reproducing ID.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital recording/reproducing device, and particularly to recording and reproducing additional information.

[Prior Art] DAT (Digital IAudio) is a digital recording and reproducing device that records and reproduces audio signals.
1'ape recorder) is known. For more information about this DAT system, please refer to rr')AT
This article was published in the March 1987 issue of ``Technology and Its Practice'', so I will omit it here.

FIG. 5 is a pattern diagram showing the recording tracks of a conventional DAT. In the figure, (6011 is a magnetic tape, <6
021 is a recording track formed obliquely to the longitudinal direction of the magnetic tape (601), (6031 is an audio signal area (hereinafter referred to as PCM) in the recording track (602)
area).

The PCM area (603) of the l track is composed of 128 blocks, and FIG. 6 is a diagram showing the signal configuration of the l block. (11112) is the ID code that is additional information closely related to the audio signal, such as the sampling frequency and presence or absence of emphasis. (813) is the block address (811) and ID code (812). Parity to detect errors.

(610 indicates an area where audio data and parity for error correction are recorded, and one block is composed of 36 symbols. Here, 1 symbol refers to 8-bit data.

Note that the same ID code is recorded every eight blocks.

Next, let's talk about error correction.

Figure 7 shows the code structure of the l track.
- It is composed of four code planes No. 4, and one plane has two planes (CI) and (C2) as shown in Figure 8.
Heavily encoded. A code that is completed in one track in this way is called a one-track-two complete code.Audio symbols are arranged in two data areas each consisting of 28 vertical symbols and 13 horizontal blocks.

(C1) Corrects errors in the vertical direction, 28
4 check symbols from audio symbols (P)
is generated and added. (C2) performs horizontal error correction, and generates and adds 6 check symbols (Q) from 26 audio symbols.

In this way, four horizontally and vertically encoded planes are recorded in a 128 block data+parity (E114) area.

Note that the code block number in FIG. 8 is block N of 128 blocks recorded on the tape.

It is a number assigned to the 32m CI code on the l code plane.

Further, the DAT records data generated during one rotation of the drum in units of two tracks in a distributed manner. therefore,
The same ID is recorded on this bare track.

[Problems to be Solved by the Invention] Conventional digital recording and reproducing devices are configured as described above, and each block has a dedicated area for sub-data such as IO, so it has a high degree of redundancy. , is not suitable for high-density recording systems.Furthermore, in order to improve reliability, multiple Φs are written, making it difficult to utilize the tape effectively.

This invention was made in order to solve the problems described in L. It is possible to record and reproduce sub data without providing a dedicated area for sub data in each block, and it is highly reliable. It is an object of the present invention to provide a digital recording and reproducing device that can reproduce sub data.

[Means for Solving the Problems] A digital recording and reproducing device according to the present invention records sub data in the same area as main data, encodes it together with the main data for error correction, and records the sub data in the same area as the main data. The present invention is characterized in that, when the pattern of the correction result and the reproduced sub-data match, the sub-data of one track is selected.

[Operation] According to the present invention, since the sub data is encoded together with the main data, there is no need for a special recording area for the sub data, and error correction encoding is performed.
Highly reliable recording and reproduction of sub data can be performed.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described based on the drawings.

In Figures 7 and 8, the data area is 2912
There is a recording area for (28x l 3x2x4) symbols. - On the other hand, the number of audio symbols recorded on one track is 2880 symbols (7
20 words x 2 channels x 2), and there is an empty area of 32 symbols, which is assigned to an ID. An example in which there are empty areas at the same position on planes No. 2 and No. 4 in FIG. 7 will be described below.

FIG. 1 is a diagram showing a recording area of a TI according to an embodiment of the present invention, and the shaded area in the figure corresponds to the empty area. That is, symbols 26 and 27 of blocks Nos. 9 to 12 and 28 to 31 are empty areas.

There is an empty area of 16 symbols on one plane, and No. 2 and N
The total of the two planes of o4 is 32 symbols. By using this, there is no need to create a special area for IDs.
I am trying to record the ID. (CI), (C2)
However, multiple writing is effective in further increasing reliability. Even in this case 2
Or about 4 overwriting is sufficient.

To decode a double code, generally, after performing (CI) decoding, (C2) decoding is performed using the (CI) decoding result. Therefore, the same (C2) code sequence, that is, Fig. 1 If one code becomes uncorrectable by multiple writing at the same symbol number position, the correct ID will not be reproduced and the multiple writing will have no effect.

Therefore, in the case of multiple writing, reliability is improved by arranging them so that they are included in different (C2) code sequences.

In this case, for example, by overwriting the 26th symbol and the 27th symbol of code block No. 9, different (
C2) This results in multiple recording on the code. However, (C1
) Since the codes are common, 7 including code block No. 9
If an error that cannot be corrected (cl) occurs in a code block of Error correction is not possible, so correct ID reproduction is impossible.

The same ID is multiple recorded on different code planes, for example plane N
By multiplexing recording on o2 and No.4, the above-mentioned inconvenience can be avoided.

Next, the configuration of an apparatus for realizing the above method will be explained.

FIG. 2 is a block diagram showing the configuration of the recording system of the digital recording and reproducing apparatus. In the figure, (lot) is the input terminal for the digitized audio signal, (102) is the memory circuit, and (103) is the above-mentioned input terminal. An address generation circuit (104) that controls the address of the memory circuit (102) is an I
A terminal (105) inputs information necessary for D generation, and an I
This is an ID generation circuit that generates D.

(10B) is an encoding circuit that performs encoding for error correction, and (107) is a terminal that outputs encoded audio symbols and IDs. Note that (108) is a clock generation circuit that generates various clocks for the system.

Next, the operation of the recording system having the above configuration will be explained.

The audio signal input from the terminal (101) is temporarily stored in the memory circuit (102). Furthermore, the ID generated by the ID generation circuit (105) is also used by the memory circuit (102).
) can be stored once.

The memory map as shown in FIG. 7 can be realized by controlling with a total of 12 bits of address, 5 bits in the vertical direction, 5 bits in the horizontal direction, and 2 bits in the plane number.

The audio data is in code planes Not and N.

3 data area and the first code plane No. 2 and No. 4.
The ID is stored in the data area excluding the shaded area in the figure, and the ID is stored in the shaded area of code planes No. 2 and 4 in FIG.

Then, (CI) and (C2) encoding are performed by the encoding circuit (
10G), then read out in a predetermined order from a terminal (1θ7), modulated by a modulation circuit (not shown), and then recorded on tape.

FIG. 3 is a block diagram showing the configuration of the reproducing system of the digital recording/reproducing apparatus.

(117) is an input terminal for audio data and ID reproduced by the head, (112) is a memory circuit, (113)
) is a memory address generation circuit for controlling the address of the memory circuit (112), and (110) is an output terminal for reproduced audio data.

(11B) is an error correction circuit for correcting errors in the reproduced audio data and ID, and (115) takes in the ID stored in the memory circuit (112), performs predetermined processing, and sends the ID to the terminal (110). (118) is a clock generation circuit for generating various clocks of the system.Next, the operation of the reproduction system having the above configuration will be explained.

The audio data and ID reproduced by the head are temporarily stored in the memory circuit (112) as shown in FIGS. 7 and 1 based on the memory address output from the address generation circuit (113). Next, the error correction circuit (11B) performs error correction, and if correction is impossible, a flag is added. In this way, after the correction process is performed, the audio data is transferred to the terminal (110).
It is output from Also, the ID in the memory circuit (112)
and flags are taken into an ID decoding circuit (115), and one with high reliability is selected and outputted to a terminal (114).

This reproduced ID is used to control the system or display the ID.

Next, one embodiment of the ID decoding circuit (115) will be described.

The same ID is the code block N of planes No. 2 and No. 4.
The 26th symbol of o9 and the 26th symbol of code block No. 28
An example in which symbols are recorded at four locations will be described below.

Hereinafter, the 26th symbol of code block No. 9 of plane No. 2 is DO, code block No. 28c7 of plane No. 2)
26th symbol is Di, code block No. of plane No. 4
9, the 26th symbol is D2. The 26th symbol of code block N028 of plane No. 4 is assumed to be D4. In this example,
DO and Dl are included in the same C2 code, and Dl and D2 are also included in the same code. is an input terminal for the reproduction ID data outputted from the memory circuit (112) and a flag indicating the error correction result, and (403) is a flag (403) indicating the correction result of the C2 code including DO and Di.
F register stores (hereinafter referred to as F1 flag);
404) is an F2 register that stores a flag (hereinafter referred to as F2 flag) indicating the correction result of the C2 code including D2 and D3.

(4051 to +4081 are DIO, DIl, respectively
This is a register that stores D20°D2+. T40
9) is DIO, DIl, D20. +41 a coincidence detection circuit which takes D21 as an input, compares the patterns of two input signals, detects whether or not they match, and outputs the result;
01 inputs the output of the minus number construction circuit (409) and the Fl and F2 flags and outputs DID, DIl, D20.
．． A selection signal generation circuit that generates a signal for selecting which of D21 to output as an ID recorded on one track, (4111 is a selector that selects one of the four IDs A to D, (402) is the ID played from the bare track (hereinafter referred to as A track)
(4141 is an ID processing circuit (402
) has the same circuit configuration as the circuit that processes the TD reproduced from the other track of the pair track (hereinafter referred to as the B track), (4121 inputs the reliability determination signal of the ID of each track, a determination circuit (41) for determining which ID to select between the ID and the B track ID;
31 is a selector, (4151 is a register).

Next, the operation of the above IF) decoding circuit will be explained.

The selection signal generation circuit +4101 checks the Fl and F2 flags and selects the 2 flags included in the correctly corrected code sequence.
When the two data patterns match, a selection signal (410a) is generated to output the matched pattern as the ID of track A.

That is, if the F1 flag is correct, the pattern matching of DO and Dl is verified, and if the F2 flag is correct, the pattern matching of D2 and D3 is verified, and if they match, a selection signal is sent to select that pattern as the output of the selector (4+1). (410a>), and also outputs a selection result signal (41
Set 0bl to a possible state (.0). If all corrections are not possible and flags are set for both Fl and F2, or if corrections are made but the patterns do not match, the above selection result signal +410b) is disabled (・l)
shall be.

Generally, in error correction, when a large number of errors are input that exceeds the capacity of the error correction code, it rarely occurs that the error is corrected (herein referred to as error correction) or there is no error (herein referred to as missed error). . In such a case, audio data is played back based on incorrect ID data, which causes noise, but such inconvenience can be avoided by verifying pattern matching.

The determination circuit (412) inputs the selection results of both tracks A and B, and selects the ID of the track indicating 0 to the selector (413).
Outputs a selection signal that selects with . In other words, input A
Or choose B. If the selection result of any track is l, the selector (41) outputs the correct ID stored in the register (415) and previously selected.
The determination circuit (412) selects the selection signal so as to select the C input of 3).

The above example is an example of using only the C2 decoding result, but if it cannot be corrected by C2 decoding, the symbol for which the C1 decoding result is correct will be output as correct data, and only the symbol that could not be corrected by both CI and C2 decoding will be corrected. There is a decoding algorithm for double codes that makes it impossible.

For example, code blocks No.9 to N01 of plane N62
If up to 9 are incorrect, C1 flags are added to these blocks in C1 decoding. In C2 decoding, C1 flag is C
Since the capability of 2 codes exceeds 6, all errors within the plane cannot be corrected, but code blocks Nos. 28 to 31
Since it is determined that the C1 decoding result is error-free, the ID of code block N028 is reproduced as correct.

In the case of such a decoding algorithm, the flags differ depending on the symbol, so instead of the F register (403) and F2 register (400 in Fig. 4), the symbol D1G
, D 11 , D20. This can be realized by providing flag registers corresponding to each of D21.

In addition, in the above algorithm, if there is an ID that has been corrected by C2 decoding or is determined to be error-free, it is output as is without performing -number construction, and if there is no ID, C2 decoding is impossible. However, even if the matching pattern is output as an ID only when two patterns without CI flags match, and the previously output ID is output again in other cases, there is a problem with reliability. So, there is no problem in practical use.

Although the example in which the same ID is recorded on two tracks has been described above, recording the ID on each track as a unit can be realized by using the output of the selector (411).

Note that in the above embodiment, the main data is an audio signal,
Although the ID is used as the sub data, other signals such as video may be used as the main data, and the above-mentioned effect can be obtained regardless of whether the ID is related to the main data or not.

Further, in FIG. 4, the match detection is performed without depending on the flag, but even if the match detection is performed only on symbols to which no flag is attached, the same effect as in the above embodiment can be obtained.

[Effects of the Invention] As described above, according to the present invention, error correction is performed when sub data multiplexed on one track is reproduced, and as a result, symbols that indicate that there is no error or that the error has been correctly corrected are If the pattern matches, the pattern-matched data is played as the sub data output of that track, and in other cases, the previous correct data is output, so highly reliable sub data can be played. be able to. Furthermore, an area dedicated to sub-data is not required, and tapes can be used effectively.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an ID recording area according to an embodiment of the invention, FIG. 2 is a block diagram showing the configuration of a recording system of a digital recording/reproducing apparatus according to an embodiment of the invention, and FIG. FIG. 4 is a block diagram showing the configuration of a reproducing system of a digital recording/reproducing apparatus according to an embodiment of the invention. FIG. 4 is a block diagram showing an example of the configuration of an ID decoding circuit according to the invention.
The figure is a pattern diagram showing the recording tracks of a conventional digital recording/reproducing device, FIG. 6 is a diagram showing the (m number configuration) of one block, FIG. 7 is a diagram showing the code configuration of the l track, and FIG. 8 is a diagram of one code plane. It is a diagram showing the code structure. (+121...memory circuit, (1131...address generation circuit, (+151-1 D lever-1 circuit,
+1161--Error correction circuit, (403) to (408
)...Register, (4091...Pattern-number construction circuit, (4101-...Selection signal generation circuit, +411)
, (4131--Selector, (4121--Determination circuit). Note that the same reference numerals in the drawings indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a digital recording and reproducing device that records and reproduces data using a rotating head so that sub data to be multiplexed on a track is encoded together with the main data for error correction and tracks are formed diagonally with respect to the longitudinal direction of the tape. , comprises an error correction means for correcting errors in main data and sub data, a register for storing correction results and reproduced sub data, and a coincidence detection means for detecting a match between patterns of two sub data. A digital recording/reproducing apparatus characterized in that the sub data of one track is selected based on the correction result and the pattern matching detection result of the sub data.