JPH06203490A - Error correction circuit - Google Patents

Abstract

PURPOSE:To improve the error detection accuracy and the correction ability by using memory offset information sent only when the memory offset information is satisfied with a prescribed condition and reading out the memory according to an outer code code group. CONSTITUTION:The memory offset information SOFF is obtained from address information and identification data IDBLK based on the identification data IDBLK incorporated in block data where no error exists or error correctable. Then, the memory 28 is read out according to the outer code code group by using the memory offset information SOFF sent only when the memory offset information SOFF is satisfied with a prescribed condition. Thus, even when the error occurs in the identification data IDBLK, the block data are transmitted to an outer code error detection/correction means 29 and the error detection accuracy and the error correction ability are improved.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIGS. 2 to 9) Problem to be Solved by the Invention (FIGS. 2 to 10) Means for Solving the Problem (FIG. 1) Operation (FIG. 1) Example (FIG. 1) ~ Fig. 9) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction circuit, and more particularly, it can be applied to a circuit for detecting and correcting an error in transmission data transmitted by adding an error correction code based on a product code format.

[0003]

2. Description of the Related Art Conventionally, as a recording / reproducing apparatus for recording information data at high density, ANSI ID-1 format (Th
ird draft PROPOSED AMERICAN NATIONAL STANDARD 19mm
TYPEID-1 INSTRUMENTATION DIGITAL CASSETTE FORMAT
There is a data recorder that complies with X3B6 / 88-12 Project 592-D 1988-03-22).

In such a data recorder, information data is subjected to error correction coding in a product code format using a Reed-Solomon code, recorded on a magnetic tape, and reproduced. Processing is performed to detect a transmission error and correct it.

The outline of this data recorder will be described below. FIG. 2 shows a recording pattern on a magnetic tape by a data recorder conforming to the ID-1 format. ANN
Is an annotation track that records annotations. TR1, TR2, TR3, ... Are data tracks on which information data is recorded, and one sector is formed for each track. Note that each data track is recorded in azimuth alternately. CTL is a control track in which a control signal is recorded, and TC is a time code track in which a time code is recorded.

The data tracks TR1, TR2, TR
The configurations of 3, ... Are defined in common for each track as shown in FIG. That is, one data track TR is one sector S
It corresponds to EC and is composed of a preamble portion PR, a data recording portion DT and a postamble portion PS. The preamble part PR corresponds to the lower head part of the data tracks TR1, TR2, TR3, ...

The preamble part PR includes a rising sequence RUS having a length of 20 bytes, a synchronization code SYNC _{PR having a} length of 4 bytes, and sector identification data ID _SEC1 .
It is formed from auxiliary data DT _AUX having a length of 6 bytes.

Further, the subsequent data recording section DT has 256 synchronous blocks BLK (BLK ₀ , BLK ₁ , BLK ₂ , ...).
, BLK ₂₅₅ ), and the input information data is recorded in this part. Each sync block BLK is a 4-byte block sync code SYNC _BLK , 1-byte block identification data ID _BLK , and 153-byte inner data (input information data is internally encoded) D
It is formed by a parity code RI composed of I and Reed-Solomon code having a length of 8 bytes. Further, the subsequent postamble part PS has a synchronization code S of 4 bytes each.
It is formed by YNC _PS and sector identification data ID _SEC2 .

FIG. 4 shows the recording system of an ID-1 format data recorder. In the recording system 1, the input information data is subjected to error correction coding for product code formation and recorded. The outline of the operation of each circuit is as follows. First, the 1-byte 8-bit input information data DT _USE is input to the outer code generation circuit 2.

As shown in FIG. 5, the code generation circuit 2 uses a predetermined generator polynomial for each of the data blocks in units of 118 bytes of the input information data DT _USE to convert from 10 bytes of the Reed-Solomon code. The generated parity codes RO _{0 to} RO ₃₀₅ are generated as outer codes, which are added after each data block and output as outer data blocks DO. The outer data block DO is sent to the memory 4 via the first multiplexer 3.

FIG. 6 shows the structure of the memory 4 and the data array in the memory. As shown, the memory 4 has one row
It is composed of memories MEM1 and MEM2 each consisting of 54 bytes and 128 bytes in a column. Outer data blocks DO _{0 to} D for 153 blocks which are sequentially input to MEM1.
O ₁₅₂ and MEM2 have outer data block DO
Outer data blocks DO _{153 to} DO ₃₀₅ for 153 blocks, which are sequentially input after _{0 to} DO ₁₅₂ , are written for one outer data block per column. The information data of one outer data block is 118 bytes, and each of the memories MEM1 and MEM2 has 1
Since 53 blocks are written, 118 × is stored in memory 4.
This means that 153 × 2 bytes, that is, 36,108 bytes of information data has been written.

The order of data writing in each column of the memories MEM1 and MEM2 is the order of the direction A in the figure, and the memory M
The lower 10 bytes of EM1 and MEM2 correspond to the outer code. In the memory 4, the data block identification data ID _B , which is data generated by the identification data generation circuit 5 for identifying each row of the memories MEM1 and MEM2,
The even number data ID _BE of the data block identification data ID _B sent to the memory MEN1 and the odd number data ID _BO of the data block identification data ID _B are sent to the memory MEM2 by one column, respectively. They are written in the order of direction A.

The data written in the memories MEM1 and MEM2 has one block of data for one line,
Reading is performed in the order of direction B. Data is read in row units. Data block identification data ID _B (00, 01, 02, 03, ...)
The memory cells MEM1 and MEM2 are alternately performed in the order according to.

The data read from the memories MEM1 and MEM2 are input to the inner code generation circuit 6. The inner code generation circuit 6 uses, for each input data block, a predetermined generator polynomial to generate parity codes RI _{0 to} RI ₂₅₅ consisting of 8 bytes of the Reed-Solomon code as inner codes, and generate each data block. Add after
Inner data blocks DI _{0 to} DI as shown in FIG.
It is output as ₂₅₅ to the second multiplexer circuit 7.

The second multiplexer circuit is an inner data block DI ₀ which is an output of the preamble data PR, the postamble data PS formed by the preamble part and the postamble part generation circuit 8 and the inner code generation circuit 6.
~ DI ₂₅₅ are sequentially selected and output. The order of output data is preamble data PR, inner data blocks DI _{0 to} DI ₂₅₅ , and postamble data PS.

The output of the second multiplexer circuit 7 is input to the data distribution circuit 9. The data distribution circuit 9 distributes (randomizes) the data by taking the exclusive OR of each 1 byte of the input data with predetermined data. The dispersed data is input to the 8-9 modulation circuit 10. This 8-9 modulation circuit 10 removes the DC component of the signal waveform recorded on the magnetic tape (DC
To make it free, the data structure is converted from 8 bits to 9 bits. The outline of this conversion is as follows.

For each value of 1-byte 8-bit input data having 256 kinds of values, 2 kinds of 9-bit data are ID-1.
It is predetermined by the format. These two 9-bit data are the CDS (Codeword Digital Sustain).
The data is such that the polarity of m) is different between positive and negative. The 8-9 modulator monitors the DSV (Digital Sum Variation) of the 9-bit data output according to the input data, and two 9-bits with different CDS values are observed so that this value converges to zero. Select one of the data. Thus 1
Input data of 8-bit structure is converted into DC-free 9-bit structure data. The 8-9 modulation circuit 1
0 indicates the format of NRZL (Nonreturn to Zero Level) input data and NRZI (Nonreturn to Zero Inversity).
The circuit to convert to e) is also included.

The output of the 8-9 modulation circuit 10, that is, the data of NRZI having a 9-bit configuration is input to the third multiplexer circuit 11. This multiplexer circuit 11
Generates a sync block BLK _{0 to} BLK ₂₅₅ by adding a fixed sync code SYNC _B having a 4-byte length formed by the sync code generation circuit 12 to each of the inner data blocks DI _{0 to} DI ₂₅₅ . The code pattern of this synchronization code SYNC _B is defined by the ID-1 format, and it is also defined that the pattern recorded on the magnetic tape must also maintain the form of this code pattern.

FIG. 8 shows a map display of the data obtained by the above processing. The output of the third multiplexer circuit 11 is a data array obtained by scanning the maps MAP1 and MAP2 in the horizontal direction, as shown in FIG.

The output of the third multiplexer circuit 11 is
It is input to the parallel-serial conversion circuit 13. The parallel-serial conversion circuit 13 receives a preamble portion PR and a synchronous block BLK ₀ to which have a bit-parallel configuration.
Each data of the BLK ₂₅₅ and the postamble part PS is converted into the data S _REC of bit serial structure.

The serial data S _REC is amplified by the recording / amplifying circuit 14 and then supplied as a recording signal to the magnetic head 16 which makes a helical scan on the magnetic tape 15, whereby the magnetic tape 15 is recorded on the magnetic tape 15 as shown in FIG. Recording tracks TR (... TR1, TR2, TR3, TR4, ...) As shown in FIG. In this way, the recording system 1 of the data recorder
Is designed so that an error correction code can be added to desired information data DT _USE based on the Reed-Solomon product code format and recorded.

Further, as described above, the recording system 1 of the data recorder
Information data DT recorded on the magnetic tape 15 by
_USE is reproduced by the reproduction system 20 of the data recorder shown in FIG. The signal processing of the reproducing system 20 is completely opposite to that of the recording system 1. That is, in the reproducing system 20 of this data recorder, the recording tracks TR (... TR1, TR2, ...
TR3, TR4, ...) Are read out as the re-correction signal S _{PB and} are input to the reproduction amplifier circuit 21.

The reproduction / amplification circuit 21 is constituted by including an equalizer and a binarization circuit, etc., and binarizes the inputted reproduction signal S _PB to the serial / parallel conversion circuit 22 as reproduction digital data DT _PB . Output. The serial / parallel conversion circuit 22 converts the reproduced digital data DT _PB in serial format into 9-bit parallel data DT _PR .

The sync code detection circuit 23 determines the sync code SYN of 4 bytes from the flow of the parallel data DT _PR.
Detecting a C _B, identifying the sync block on the basis of this. Also, here, the parallel data D in the NRZI format
A circuit for converting T _PR to NRZL format is also included.

The output of the sync code detection circuit 23 is 8-9.
It is input to the demodulation circuit 24. The 8-9 demodulation circuit 24 is a circuit for restoring the data converted from 8 bits to 9 bits in the recording system to be DC-free to 8 bits again. This circuit is composed of a ROM (Reed Only Memory) and converts data from 9 bits to 8 bits by a search table process.

In the data integration circuit 25, the data restored to 8 bits is subjected to an integration (derandomization) process which is the reverse of the process received by the recording system, that is, the decentralization process. This integration is achieved by performing an exclusive OR operation of the same predetermined data used for decentralization and the input data of the data integration circuit 25.

The inner code error detection / correction circuit 26 selects an inner data block DI among the determined synchronization blocks.
_{For 0 to} DI ₂₅₅ , error detection and correction are performed by using the 8-byte length inner code RI _{0 to} RI ₂₅₅ added to each block.

The inner data blocks DI _{0 to} DI ₂₅₅ that have undergone inner code error correction are identified by the identification data detection circuit 27.
Based on the block identification data ID _B of 1-byte length added to each block detected in step 1, one data block is stored in one line in the memory 28 having the same configuration as the memory 4 of the recording system shown in FIG. Written. The order of writing is
The order of reading from the memory 4 of the recording system is similar to that of the ME.
Alternately, M1 and MEM2 are arranged line by line along the block identification data.

Each memory MEM1 and MEM2 of the memory 28
The data written in is read out in the same order as the writing order of the memory 4 of the recording system in the next column direction, and as a result, the outer data blocks DO _{0 to} DO of 128 bytes length are read.
₃₀₆ is obtained again. Outer code error detection and correction circuit 29
Performs error detection and correction on outer data blocks DO _{0 to} DO ₃₀₆ output from the memory 28, using 10-byte-length outer codes RO _{0 to} RO ₃₀₆ added to the respective blocks. In this way, the information data DT _USE recorded on the magnetic tape 15 is reproduced.

[0030]

However, in the reproducing system 20 of the magnetic recording / reproducing apparatus having such a structure, in the inner code error detection / correction circuit 26, the synchronous block B for the memory 28 regarding the synchronous block BLK which cannot be error-corrected.
It is controlled to stop writing LK. For this reason, if an error occurs in a part other than the synchronous block data DT _BLK and it is impossible to correct the error due to this, the synchronous block data DT _BLK is not actually erroneous.
Is not written in the memory, the correct sync block data DT _BLK is not sent to the outer code error detection / correction circuit 29. As a result, the outer code error detection / correction circuit 29 cannot correct the error. Atsuta

Further, in the inner code error detection / correction circuit 26, when a certain synchronous block BLK is erroneously corrected and the identification data ID _BLK of the synchronous block BLK is erroneous, the memory in which the synchronous block BLK is erroneous. When the correct synchronization block BLK is written in the address and, as a result, the erasure correction is performed in the outer code error detection / correction circuit 29, there is a problem that the error is further corrected.

Furthermore, the identification data IDBLK has the value "00".
In all other synchronous blocks _BLK K, even if all "0" data is input due to dropout on the magnetic tape 15 or the like, the identification data ID _BLK becomes the address of the memory 28 corresponding to the value "00". , The synchronous block BLK of all "0" is written as correct data, and therefore, if erasure correction is performed by the outer code error detection / correction circuit 29 in the same manner as described above, there is a problem of further erroneous correction.

In order to solve such a problem, an error correction circuit 30 including a memory control circuit 31 as shown in FIG.
Is used. Of these, the counter 32 is reset to "00" by the block reset BRST and incremented for each inner code. When the block ID detected by the block ID detection circuit 33 is other than "00" and a code determined to be correct in the inner sequence comes in after the block is reset, the difference between the counter 32 and the block ID is detected. Counter 3 calculated by subtraction circuit 34
Data is written in the memory 28 using the output of 2 as a memory address.

After determining the memory address, the counter 32 loads the block ID at that time. After that, that is, after the offset is obtained, the difference between the block ID and the output of the counter which is incremented by 1 is detected for each block, and the difference is judged by the judgment circuit 36. If it is correct, the block ID is loaded into the counter 32. Then, the sum of the loaded value (that is, the block ID) and the offset is obtained by the adder circuit 38, and the data is written as the address of the memory 28.

Thereafter, this operation is continued, and the final address detection circuit 35 determines whether the output of the counter 32 and the block ID are the final code. When the final code is determined, the writing of data to the memory 28 is stopped.

When data is read from the memory 28, the data is read with the offset as the first address and sent to the outer code error detection / correction circuit 29. However, if the offset is erroneously obtained at this time, the memory address is destroyed and correct data cannot be sent to the outer code error detection / correction circuit 29.

In practice, in this error correction circuit, the difference between the output of the counter and the block ID of the code which is reproduced first and whose block ID is not "00" but judged to be correct is obtained as an offset and demodulated. The address of the write memory is obtained when
Of the block ID and the continuity of the block ID are judged by the judging circuit 36, the write address of the code is controlled, and the read address of the outer series is determined from the obtained offset when reading.

However, at this time, once the offset has been obtained, the offset is loaded into the counter 32,
Since the read address is determined by the offset and by observing the continuity from there, if the offset is wrong, all the continuity judgments on the write side are incorrect and an error flag is set. The data is in error.

On the read side, since the read address is different, the data arrangement is destroyed. This is because once the offset is erroneously obtained, even if the offset is logically suspected, the offset is used for demodulation. Further, if the offset is wrong, there is a problem that all the data forming the product code becomes an error.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose an error correction circuit which can improve the error correction efficiency and accuracy by correctly grasping the offset.

[0041]

In order to solve such a problem, in the present invention, an error correction is performed in which error correction code is added to information data based on a product code format to receive transmission data to be transmitted and error correction is performed. In the circuit 40, an inner code error detection / correction means 26 for detecting and correcting an inner code error of transmission data, and the inner code error detection / correction means 26.
The counter 32 that operates the inner code correction data transmitted from the block data unit BLK from the block data unit BLK
The memory offset information S _OFF is written from the address information S _OFF and the identification data ID _BLK on the basis of the identification data included in the block data in which no error exists or the error can be corrected. determined, only when the memory off excisional information S _oFF satisfies a predetermined condition, the memory control unit 41 for sending a memory off excisional information, using a memory-off excisional information S _oFF sent from the memory control unit 41 Outer code error detection / correction means 29 for reading out the memory 28 in accordance with the outer code sequence, detecting and correcting the outer code error, and sending it out is provided.

Further, in the present invention, in the error correction circuit 40 for adding the error correction code to the information data on the basis of the product code format and receiving and correcting the transmission data transmitted, the inner code error of the transmission data is corrected. The internal code error detection / correction means 26 for detecting and correcting and the internal code correction data sent from the internal code error detection / correction means 26 in the block data unit BLK are converted into address information obtained from the counter 32 operating in the block data unit. According to the identification data ID _BLK which is written in the memory 28 and has no error or error-correctable block data, the memory offset information S _OFF is obtained based on the address information and the identification data ID _BLK , and the memory is turned off. If the continuity of the set information S _OFF is judged and it is judged to be correct, the memory off set Sends the information S _OFF, depending suspicious if the memory control unit 41 again obtains the memory off excisional information S _OFF, the memory 28 using the memory-off excisional information S _OFF sent from the memory control unit 41 to the outer code sequence And an outer code error detection / correction unit 29 for detecting and correcting the outer code error and transmitting the corrected data.

[0043]

The inner code correction data BL sent from the inner code error detection / correction means 26 in units of predetermined block data BLK.
K is written in the memory 28 according to the address information obtained from the counter 32, and the identification data ID included in the block data in which no error exists or error correction is possible
Based on _BLK, address information and the identification data ID _BLK
More seeking memory off excisional information S _OFF, the memory-off excisional information S _OFF by using the memory-off excisional information S _OFF sent only when a predetermined condition is satisfied, reading in accordance with the memory 28 to the outer code code sequence By doing so, even if an error occurs in the identification data ID _BLK , the block data can be transmitted to the outer code error detection / correction means 29, and the error detection accuracy and the error correction capability can be improved.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In the present invention, in FIG. 1 in which parts corresponding to those in FIG. 10 are designated by the same reference numerals, reference numeral 40 indicates an error correction circuit according to the present invention as a whole. A switch circuit 42 and first and second determination circuits 43 and 44 are provided.

That is, according to the present invention, if the offset obtained once is judged to be suspicious during the subsequent demodulation, the offset is obtained again. Therefore, even if the offset is erroneously obtained, the offset check is performed, and only the offset that has passed the check is used as the regular offset.

In practice, the first decision circuit 43 decides whether or not the offset is within a predetermined range as in the case of the conventional decision circuit. When the offset value deviates from the predetermined range, the switch 42 is detected. OFF control is performed so that the offset is not supplied to the offset detection circuit 45 until the correct offset value is obtained.

The second judgment circuit 44 monitors the difference between the output of the counter 32 and the block ID, and if the offset is erroneously obtained, the offset is loaded into the counter 32, and the operation thereafter is as follows. If the block IDs are successively input, the counter 32 and the block ID have a difference and hold a value.

Therefore, if this shift continues for some blocks, the offset detection circuit 45 is cleared to
Ask for the offset again. However, when the offset determined again here is judged to be incorrect by the second judgment circuit 44, the offset is calculated again, and this operation is repeated, and the finally remaining one is taken as the offset and the first memory on the reading side. Determine as address.

According to the above configuration, when the offset obtained once is judged to be suspicious in the subsequent demodulation,
If the offset is requested again by mistake, even if the offset is mistakenly requested, the offset is checked, and only the offset that has passed the check is used as a regular offset so that the offset can be correctly grasped and error correction can be performed. An error correction circuit capable of further improving efficiency and accuracy can be realized.

In the above embodiment, the present invention is
Although the present invention is applied to the reproduction system of the D-1 format data recorder, the present invention is not limited to this, and various information can be used as long as it decodes data to which parity codes are added in the product code format for error correction. It can be widely applied to processing equipment.

[0052]

As described above, according to the present invention, the inner code correction data sent from the inner code error detection / correction means in a predetermined block data unit is written in the memory according to the address information obtained from the counter, The memory offset information is obtained from the address information and the identification data based on the identification data contained in the block data in which no error exists or the error correction is possible, and it is transmitted only when the memory offset information satisfies the predetermined condition. By reading the memory according to the outer code code sequence using the memory offset information, the block data can be transmitted to the outer code error detection / correction means even if an error occurs in the identification data, and the error detection is performed. The accuracy and error correction ability can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an error correction circuit according to the present invention.

FIG. 2 is a schematic diagram for explaining a recording pattern of ID-1 format.

FIG. 3 is a schematic diagram showing the contents of a data track in an ID-1 format.

FIG. 4 is a block diagram showing a recording system of an ID-1 format data recorder.

FIG. 5 is a schematic diagram showing an outer data block in the recording system of the data recorder.

FIG. 6 is a schematic diagram showing a data array in a memory in the recording system of the data recorder.

FIG. 7 is a schematic diagram showing an inner data block in the recording system of the data recorder.

FIG. 8 is a schematic diagram showing a map display of data.

FIG. 9 is a block diagram showing a reproduction system of a data recorder of ID-1 format.

FIG. 10 is a block diagram showing a conventional error correction circuit.

[Explanation of symbols]

1 ... Recording system, 2 ... Outer code generation circuit, 3, 7, 11 ...
... MUX, 4 ... Memory, 5 ... Identification data generation circuit,
6 ... Inner code generation circuit, 8 ... Preamble part Postamble part generation circuit, 9 ... Data distribution circuit, 10 ... 8
-9 Modulation circuit, 12 ... Synchronous code generation circuit, 13 ...
Parallel / serial conversion circuit, 14 ... Recording amplification circuit,
15 ... Magnetic tape, 16 ... Magnetic head, 20 ... Playback system, 21 ... Playback amplification circuit, 22 ... Serial-parallel conversion circuit, 23 ... Sync code detection circuit, 24 ... 8
-9 demodulation circuit, 25 ... data integration circuit, 26 ... inner code error detection / correction circuit, 27 ... identification data detection circuit,
28 ... Memory, 29 ... Outer code error detection / correction circuit.

Claims (2)

[Claims] 1. An error correction circuit for receiving and correcting error in transmission data transmitted by adding an error correction code based on a product code format to information data, and detecting and correcting an inner code error in the transmission data. Inner code error detection / correction means for writing, and inner code correction data sent from the inner code error detection / correction means in block data units are written in a memory in accordance with address information obtained from a counter operating in block data units. Only when the memory offset information satisfies a predetermined condition, the memory offset information is obtained from the address information and the identification data based on the identification data contained in the block data in which no error exists or the error can be corrected. A memory control means for transmitting as the memory offset information, and the memory control means. An error characterized by comprising an outer code error detection / correction means for reading the memory according to an outer code sequence using the memory offset information to be transmitted, detecting and correcting an outer code error and transmitting the error. Correction circuit. 2. An error correction circuit for receiving and correcting error in transmission data transmitted by adding an error correction code based on a product code format to information data, and detecting and correcting an inner code error of said transmission data. The internal code error detection / correction means and the internal code correction data sent from the internal code error detection / correction means in block data units are written in the memory in accordance with the address information obtained from the counter operating in the block data units, and an error occurs. Is not present or error correction is possible, the memory offset information is obtained based on the address information and the identification data, and the continuity of the memory offset information is determined to be correct. If it is determined that the memory offset information is sent, if it is doubtful, the memory off Using the memory control means for re-obtaining the offset information and the memory offset information sent from the memory control means, the memory is read in accordance with the outer code sequence, and an outer code error is detected and corrected An error correction circuit comprising a code error detection and correction means.