JPH06124548A - Data reproduction device - Google Patents

Abstract

PURPOSE:To obtain a data reproduction device capable of correcting burst error by forming error flags with a demodulation means and correcting the errors of a data employing the error flags with an error correcting means. CONSTITUTION:Reproduced signals by a pickup 10 from a disk 9 are waveform equalized by a waveform equalizer 11 and transmitted to a demodulator 80. The demodulator 80 demodulates the inputted signals, generates an error flag when an error exists in the demodulated data and outputs to an error correcting circuit 14. The circuit 14 corrects the error of the data demodulated by the demodulator 80 by using an inputted error flag. Having this constitution, an error flag is surely raised even though errors occur in continuous symbols by burst errors, an erasure correction capability is fully used and a data reproduction device, which corrects burst errors, is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus suitable for reproducing digital data of image and / or sound obtained from a storage medium such as a disk or a transmission line.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional configuration example of an apparatus for recording / reproducing digitized image and audio signals on a storage medium such as an optical disk.

In FIG. 6, an analog image signal (video signal) supplied to an input terminal 31 is digitized by an A / D (analog / digital) converter 1 and encoded by an encoder 3. , Multiplexer
Input to 5. Similarly, the analog audio signal (audio signal) supplied to the input terminal 32 is also supplied to the A / D converter 2
After being digitized by the encoder, encoded by the encoder 4, and input to the multiplexer 5. The multiplexer 5 multiplexes the coded image signal and audio signal and sends them to the next error correction parity adding circuit 6.

The details of the error correction parity adding circuit 6 are shown in FIG. 8 to 12 show how data is written / read to / from the memory space of the memory 51 of FIG. 7.

Here, as the error correction parity, for example, a 16-byte Reed-Solomon code is added to interleaved 64-byte data. A total of 80 bytes of 64-byte data and 16-byte parity,
It is called 1 code. A unit of data for which error correction is performed is called one symbol. In this example, one symbol is one byte.

The signal from the multiplexer 5 of FIG. 6 is shown in FIG.
Is sent to the buffer 50 via the input terminal 33 of the error correction parity adding circuit 6 and the output of the buffer 50 is stored in the memory 51 via the data bus 54 (this write operation is W1). At this time, in the memory 51,
Data is written in the order of the write operation W1 shown in FIG. In addition, the white circle in the drawing of FIG. 8 shows one symbol.

Next, the data read from the memory 51 is sent to the error correction parity calculation circuit 53 via the data bus 54. At this time, 6 bytes of data are read from the memory 51 in an oblique direction (interleave direction) (this read operation is referred to as R1). That is, data is read from the memory 51 in the order of the read operation R1 shown in FIG.

The error correction parity calculation circuit 53 calculates a 16-byte parity for the supplied 64-byte data and adds it to the end of the data.
To the memory 51 again. The memory 51 writes the data with parity in the same direction as the read operation R1 as shown in FIG. 10 (this write operation is referred to as W2). In addition, the black circle in the figure of FIG. 10 shows one parity symbol.

After that, data with parity (80 bytes) is read from the memory 51 in the same order as the write operation W1 shown in FIG. 11 (this read operation is referred to as R2). These are output from the output terminal 34 of the error correction parity adding circuit 6 via the data bus 54 and the buffer 55, and sent to the modulator 7 of FIG. The controller 52 of FIG. 7 controls the writing / reading of the memory 51 and the data processing operation of the error correction parity calculation circuit 53.

Next, in the modulator 7 of FIG. 6, as shown in FIG. 12, a sync signal is added to the beginning of each code (80 bytes), for example, so-called 8-14.
After being modulated by modulation (EFM: Eight to Fourteen Modulation), it is sent to the pickup 8. It is recorded on the disc 9 by this pickup 8. The above is the conventional image and audio encoding device (image and audio recording device) 1
00.

Next, an image and audio decoding device (image and audio reproduction device) 110 corresponding to the above encoding device 100.
Explain. A signal reproduced from the disc 9 by the pickup 10 is input to a waveform equalizer (EQ: equalizer) 11, where the waveform is equalized and then sent to a demodulator 13. On the other hand, the waveform equalizer 11 also extracts a clock component, which is sent to the PLL circuit 12, where it is phase-locked and then sent to the demodulator 13.

Details of the demodulator 13 are shown in FIG. An input signal (input data) via the input terminal 35 of the demodulator 13 is stored in the register 60, and the sync extractor 61 extracts the sync. The extracted sync is input to the timing generator 64, output from the terminal 36 as a sync signal, and sent to the error correction circuit 14 shown in FIG.

If there is an error in the data due to scratches on the disk 9 and the sync extractor 61 cannot extract the sync, the timing generator 64 is used.
Then, an interpolation sync is inserted based on the PLL clock supplied from the PLL circuit 12 via the terminal 39.
That is, as shown in FIG. 14, the interpolation sync is inserted into the original sync.

Further, the data output from the register 60 is subjected to EFM demodulation in a converter (converter) 62, and the error correction circuit 1 in the subsequent stage is passed through a terminal 37.
Sent to 4. Furthermore, the output of the register 60 is also input to the error detector 63.
Then, it is monitored whether there is a combination of impossible codes (for example, a fixed number of consecutive zeros or more) in EFM modulation, and if there is a combination of impossible codes, it is determined as an error for each symbol as an error symbol. Furthermore, EF
Even when a combination of impossible codes is detected during M demodulation, the error detector 63 makes an error determination based on the signal from the converter 62. When it is determined that there is an error, the error flag is sent to the error correction circuit 14 in the subsequent stage via the terminal 38.

The details of the error correction circuit 14 of FIG. 6 are shown in FIG. In addition, similar to the above-mentioned encoder, FIGS. 16 to 19 show how data is written / read to / from the memory space of the memory 71 in the error correction circuit 14 of FIG.
Shown in. However, the circle marks (white circles and black circles) in FIGS. 16 to 19 indicate 9 bits, which is a combination of 1 byte of data and 1 bit of error flag, and the white circles in the figures represent the data part and the black circles represent the parity part. .

Demodulated data (input data) demodulated by the demodulator 13 and supplied to the input terminal 39 of the error correction circuit 14 is written in the memory 71 via the buffer 70 and the data bus 74. Further, the error flag from the demodulator 13 supplied to the terminal 40 is similarly written in the memory 71 via the buffer 70 (this writing operation is referred to as W11). That is, the memory 7
Data and an error flag are written in 1 in the order shown in the write operation W11 in FIG.

The data read from the memory 71 is sent to the error correction circuit 73 via the data bus 74. At this time, as shown in FIG. 17, 80 bytes including parity in the diagonal direction (interleave direction) are read from the memory 71 (this read operation is performed by R1.
1).

The error correction circuit 73 performs error correction on the input data. Here, in general, when p parity is added, q error symbols without error flags and r error symbols with error flags can be corrected, and q and r satisfy the following expression (A). There must be.

P ≧ q * 2 + r ... (A)

In this example, 16 bytes of parity are added, and up to 8 symbols of error can be corrected per code by normal correction without an error flag, and up to 16 symbols by erasure correction using an error flag. Error correction is possible.

The data corrected in error by the error correction circuit 73 is sent again to the memory 71 via the data bus 74 and is written in the same direction as the read operation R11 as shown in FIG. The write operation is W21).

Thereafter, only 64 bytes of the data portion are read from the memory 71 in the same order as the write operation W11 shown in FIG. 19 (this read operation is referred to as R21). These are passed through the data bus 74, the buffer 75, and the terminal 42, and then the demultiplexer (demultiplexer) 15 of FIG.
Sent to. The controller 72 controls these series of data processing operations based on the sync signal from the terminal 41.

The output of the error correction circuit 14 as described above is
The demultiplexer 15 of FIG. 6 separates the image signal and the audio signal. The image signal is decoded by the decoder 16,
Thereafter, it is converted into an analog signal by the D / A (digital / analog) converter 18 and sent to the monitor device 20. The audio signal is decoded by the decoder 17, converted into an analog signal by the D / A converter 19, and sent to the audio reproducing device 21.

[0024]

In the above-described decoding device (decoding device 110), since erasure correction is performed by the error flag generated by the demodulator (demodulator 13), total error is generated. The error correction capability largely depends on how many of the symbols an error flag is added to.

In the decoder, however, an error flag is set only when a combination of prohibited codes which cannot be provided in the modulation method occurs, so that an error occurs and it happens that the code combinations are not prohibited. If
No error can be detected and no error flag is raised. For this reason, for example, when an error occurs in consecutive symbols due to a burst error, the error flag becomes considerably smaller than the actual number of error symbols, the erasure correction cannot be performed sufficiently, and the error correction circuit does not correct the error. Often it becomes possible.

In view of the above, the present invention has an object to provide a data reproducing apparatus capable of error correction even when an error occurs in consecutive symbols due to a burst error.

[0027]

The data reproducing apparatus of the present invention has been proposed in order to achieve the above-mentioned object, and an image and / or an image transmitted via a transmission line or a recording medium are provided.
Or an error that demodulates voice data and generates an error flag when the demodulated data has an error, and an error that corrects the error of the data demodulated by the demodulating means by using the error flag obtained from the demodulating means. It comprises a correction means and a decoding means for decoding the data subjected to the error correction by the error correction means to obtain an image and / or audio signal.

Here, the demodulation means includes a first detection means for detecting a combination of codes which is not possible at the time of modulation,
Second detection of combinations of codes that are not possible during demodulation
Of the detection output, and an error flag generating means for generating an error flag from the output of the counting means.

The error flag generating means generates an error flag based on the interpolation sync signal from the timing generator. Further, the error flag generating means is
When it is detected that it is an interpolation sync, an error flag is generated for the symbols of one code. Further, the error flag generating means generates an error flag for all the symbols of one code when the number of errors in one code is a predetermined number or more. Furthermore, when the error flag generating means does not detect that it is an interpolation sync and the number of errors in one code is less than or equal to a predetermined number, the output of the first detecting means is generated as an error flag. .

That is, the data reproducing apparatus of the present invention is a reproducing means such as a pickup for reproducing data recorded on a disk such as an optical disk, and a demodulation for demodulating the data reproduced from the optical disk and outputting an error flag. Means, error correction means for performing error correction on the data obtained by the demodulation means by using an error flag also obtained by the demodulation means, demultiplexing means for decoding and reproducing the data obtained by the error correction means, etc. And a decoding / reproducing unit.

[0031]

According to the data reproducing apparatus of the present invention, the demodulating means forms the error flag in consideration of the burst error, and the error correcting means performs the error correction of the data demodulated by the demodulating means by the error flag obtained from the demodulating means. Since it is performed by using, it becomes possible to correct an uncorrectable burst error.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data reproducing device (image and audio decoding device) of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the configuration of the data reproducing apparatus according to the embodiment of the present invention. Note that, in FIG. 1, each component except the demodulator 80 is the same as that of the decoding device (reproducing device) 110 shown in FIG. 6 described above, and these are designated by the same reference numerals. ing.

That is, the data reproducing apparatus of this embodiment is
As shown in FIG. 1, a demodulator 80 that demodulates image and / or audio data transmitted through a transmission path or a recording medium and generates an error flag when the demodulated data has an error, and the demodulator 80. The error correction circuit 14 that performs error correction of the demodulated data using the error flag obtained from the demodulator 80, and the image and / or audio data obtained by decoding the data that has been error-corrected by the error correction circuit 14 And a demultiplexer 15 and decoders 16 and 17 for obtaining

In FIG. 1, the signal reproduced by the pickup 10 from the disk 9 is input to the waveform equalizer 11, is equalized in waveform, and then is sent to the demodulator 13.
On the other hand, the clock component extracted by the waveform equalizer 11 is P
After being sent to the LL circuit 12 and locked in phase, the demodulator 8
Sent to 0.

The details of the demodulator 80 of this embodiment are shown in FIG. That is, the demodulator 80 is, as shown in FIG. 2, an error detector 93 as a first detecting means for detecting a combination of codes that is not possible at the time of modulation, and a first detector for detecting a combination of codes that is not possible at the time of demodulation. An error counter 95, which includes a converter 92 (and an error detector 93) as a second detection unit, and further as a counting unit that counts these detection outputs, and the error counter 9
5 and an error flag generator 96 for generating an error flag from the output of FIG.

The error flag generator 96 generates an error flag based on the interpolation sync signal from the timing generator 94. Further, when the error flag generator 96 detects that it is an interpolation sync, it generates an error flag for all the symbols of one code. Further, the error flag generator 96 generates an error flag for all the symbols of one code when the number of errors in one code is equal to or larger than a predetermined number. Furthermore, when the error flag generator 96 does not detect that it is an interpolation sync and the number of errors in one code is less than or equal to a predetermined number,
The output of the first detecting means is generated as an error flag.

A detailed description will be given below. In FIG. 2, the input signal supplied to the terminal 43 is the register 90.
, And the next sync extractor 91 extracts the sync. The extracted sync is input to the timing generator 94, output as a sync signal from the terminal 44, and sent to the error correction circuit 14 in the subsequent stage in FIG. Also in the present embodiment, as described above, when the sync cannot be extracted by the sync extractor 91, the timing generator 9
At 4, the interpolation sync is inserted based on the PLL clock supplied from the PLL circuit 12 via the terminal 47.

The data output from the register 90 is subjected to EFM demodulation in the converter 92, and the terminal 4
It is sent to the error correction circuit 14 of FIG.

The output of the register 90 is also input to the error detector 93. Similar to the error detector 63, the error detector 93 monitors whether there is a combination of impossible codes in EFM modulation, and if there is a combination of impossible codes, it is determined that each symbol is an error as an error symbol. . Further, even when a combination of impossible codes is detected during EFM demodulation, the error detector 93 determines that there is an error from the signal from the converter 92.

The output of the error detector 93 is input to the error counter 95. The error counter 95 counts the number of errors included in one code and sends the number to the next error flag generator 96.

In the error flag generator 96, the interpolated sync signal obtained from the timing generator 94,
Based on the number of errors obtained from the error counter 95, an error flag is generated under the following rules.

First, when interpolating the sync,
An error flag is set for all the symbols in one code, assuming that an error has occurred in the entire one code.

Second, when the number of errors in one code is equal to or greater than a set value, it is determined that an error has occurred in the entire one code, and an error flag is set for all the symbols in the one code.

Thirdly, when neither of the first and second rules is satisfied, the output of the error detector 93 is directly used as an error flag as usual.

Here, a timing chart of the operation of each part in the demodulator 80 is shown in FIG. In FIG. 3, the sync is low level active and the error flag is high level active. That is, in FIG. 3, the part indicated by (*) in the drawing corresponds to the above-mentioned first rule, and therefore an error flag is set for all one code as described above. Further, the part indicated by (**) in FIG. 3 corresponds to the above-mentioned second rule, and since the number of error flags is equal to or greater than the set value, the error flag is set for all the codes.

The output data, the sync, and the error flag from the demodulator 80 as described above are output from the corresponding terminals 44, 45 and 46, respectively, and input to the error correction circuit 14 of FIG. In this error correction circuit 14, data error correction is performed as in the above-described decoding device.

Next, FIGS. 4 and 5 are shown in FIGS.
Similar to FIG. 19, a read operation R13 (reading to the error correction circuit 73) in the memory space of the memory 71 of the error correction circuit 14 in this embodiment is shown.

Here, it is assumed that 10 consecutive codes (800 bytes) from the Nth line to the N + 9th line in FIG. 4 have an error due to a burst error. Also, the N + 1th row and N +
It is assumed that an error flag is set on the symbol on the second line. Further, an error symbol in which an error flag is not set is indicated by X in the figure, and an error symbol in which an error flag is set is indicated by a triangle mark in the figure. That is, FIG. 4 shows an example in which 10 symbols are consecutively erroneous in the reading direction of the reading operation R13, and an error flag is set for only 2 symbols among them. In such an example, only the correction of eight error symbols in which no error flag is set is the correction capability limit of the error correction circuit 14, and it cannot be corrected as it is.

Therefore, in this embodiment, an error flag is set on the symbols on the N + 3th row and the N + 8th row, as shown in FIG. 5, by a method corresponding to the above-mentioned rules. By doing so, in this embodiment, the number of error symbols without an error flag is two, and the number of error symbols with an error flag is eight, which satisfies the above-mentioned expression (A), so that error correction is possible.

The operation from the output of the error correction circuit 14 to the subsequent stage is exactly the same as that of the decoding device shown in FIG. 6 described above, and therefore its explanation is omitted.

As described above, in the apparatus of this embodiment, the error flag is surely set even in the case of a burst error by adding some measures to the setting of the error flag. As a result, it becomes possible to correct even a burst error, which is conventionally uncorrectable due to a small number of error flags, up to the limit of erasure correction capability.

The above-mentioned modulation method, data format, interleaving method, etc. are not limited to those in the above-described embodiments, and other modulation methods can be adopted instead of EFM modulation, for example.

The data reproducing apparatus of the present invention can be applied not only to a disk medium such as an optical disk but also to a decoding / reproducing apparatus for communication using a transmission line (electric transmission line).

[0055]

As described above, in the data reproducing apparatus of the present invention, the demodulating means forms the error flag in consideration of the burst error, and the error correcting means performs the error correction of the data demodulated by the demodulating means. The error flag obtained from is used. That is, when an error occurs in consecutive symbols due to a burst error, the error flag is set to be sure to be set, so that the erasure correction capability can be fully used, and the burst error that was previously uncorrectable can also be corrected. It will be possible.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration example of a data reproducing device according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a detailed configuration of a demodulator in one configuration example of the reproducing apparatus of the present embodiment.

FIG. 3 is a timing chart for explaining error flag generation in one configuration example of the reproducing apparatus of the present embodiment.

FIG. 4 is a diagram illustrating a series of 10 from the Nth row to the N + 9th row in the memory space for explaining the error correction in this embodiment.
It is a figure which shows the example in which the code has produced the error by the burst error.

FIG. 5 is a diagram showing an example of setting an error flag on the symbols on the N + 3th row and the N + 8th row in the memory space for explaining the error correction in the present embodiment.

FIG. 6 is a block circuit diagram showing a configuration of a specific example of a conventional encoding device and decoding device (recording device and reproducing device).

7 is a block circuit diagram showing details of an error correction parity adding circuit in the configuration example of FIG.

8 is a diagram for explaining a write operation W1 in the memory space of the memory of the error correction parity adding circuit in FIG. 7. FIG.

9 is a diagram for explaining a read operation R1 in the memory space of the memory of the error correction parity addition circuit in FIG. 7.

10 is a diagram for explaining a write operation W2 in the memory space of the memory of the error correction parity addition circuit in FIG. 7.

11 is a diagram for explaining a read operation R2 in the memory space of the memory of the error correction parity addition circuit in FIG. 7.

12 is a diagram for explaining how a sync signal is added to the beginning of each code in the memory space of the memory of the error correction parity adding circuit in FIG.

13 is a block circuit diagram showing details of a demodulator in the configuration example of FIG.

14 is a timing chart for explaining the interpolation of the sync signal in the configuration example of FIG.

15 is a block circuit diagram showing details of an error correction circuit in the configuration example of FIG.

16 is a diagram for explaining a write operation W11 in the memory space of the memory of the error correction circuit in FIG.

17 is a diagram for explaining a read operation R11 in the memory space of the memory of the error correction circuit in FIG.

FIG. 18 is a diagram for explaining a write operation W21 in the memory space of the memory of the error correction circuit in FIG.

19 is a diagram for explaining a read operation R21 in the memory space of the memory of the error correction circuit in FIG.

[Explanation of symbols]

 9 ... Optical disc 10 Pickup 11 Waveform equalizer 12 PLL circuit 13 Demodulator 14 Error correction circuit Demultiplexer 16/17 Decoder 18/19 D / A converter 20 Monitor device 21 Sound reproduction device 80 Demodulator 90 ... Register 91 ... Sink extractor 92 ... Converter 93 ... Error detector 94 ... Timing generator 95 ... Error counter 96 ... Error flag generator

Claims (6)

[Claims] 1. Demodulation means for demodulating image and / or audio data transmitted via a transmission path or a recording medium, and for generating an error flag when the demodulated data has an error, and demodulation means demodulated by the demodulation means. Error correction means for performing error correction on the data using the error flag obtained from the demodulation means, and decoding the data corrected by the error correction means,
A data reproducing device comprising a decoding means for obtaining an image and / or audio signal. 2. The demodulating means includes a first detecting means for detecting a combination of codes which is impossible at the time of modulation, and a second detecting means for detecting a combination of codes which is impossible at the time of demodulation, and further, these detection outputs 2. The data reproducing apparatus according to claim 1, further comprising: a counting means for counting the number of times, and an error flag generating means for generating an error flag from the output of the counting means. 3. The data reproducing apparatus according to claim 2, wherein the error flag generating means generates an error flag based on the interpolation sync signal from the timing generator. 4. The data reproducing apparatus according to claim 3, wherein the error flag generating means generates an error flag for all symbols of one code when it is detected as an interpolation sync. 5. The data according to claim 3, wherein the error flag generating means generates an error flag for all the symbols of one code when the number of errors in one code is a predetermined number or more. Playback device. 6. The error flag generating means does not detect that it is an interpolation sync, and when the number of errors in one code is a predetermined number or less, the output of the first detecting means is used as an error flag. The data reproducing apparatus according to claim 3, wherein the data reproducing apparatus is generated.