JP2656915B2 - Error correction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device applied to reproduce digital audio signals and digital data from a digital disk.

[Conventional technology]

2. Description of the Related Art A disc reproducing apparatus that optically reproduces a digital audio signal from a disc (referred to as a compact disc) is known. In this disc reproducing apparatus, a strong error correction code is employed. However, if the error cannot be completely corrected, interpolation is performed to replace the error data with an average value of correct data located before and after the error data.

This interpolation is performed by looking at a flag for each sample data output from the error correction circuit. Although the probability of decoding an error correction code is extremely low, an error correction operation may be erroneously performed. In this case, the corrected data is completely different from the original data, and becomes an abnormal sound in the reproduced sound. Therefore, erroneous corrections should be avoided as much as possible.

When reproducing digital data such as characters from a digital disk, it is necessary to strictly determine whether or not the data is erroneous, and there is a strong demand to prevent the erroneous correction described above.

The error correction of the conventional digital audio disk reproducing apparatus is a combination of Reed-Solomon code and interleave, and one and two symbols are corrected by a first Reed-Solomon code (referred to as C1 code).
When a two-symbol error is corrected or uncorrectable, a pointer is set, then deinterleaving is performed, and correction is performed using a second Reed-Solomon code (referred to as C2 code). The correction is performed with reference to the number of pointers and the position of the pointer.

[Problems to be solved by the invention]

Conventional error correction devices are not yet sufficient to prevent erroneous corrections.

In other words, when a double error is detected in the C2 decoder,
When the number of pointers is, for example, five or more, the pointer from the C1 decoder is used as the interpolation flag as it is, and the calculated error position is not considered at all.

When the present invention generates a flag from a pointer,
It is an object of the present invention to provide an error correction apparatus in which a flag is set not only at a pointer from a decoder at the preceding stage but also at a calculated error position, so that the possibility of erroneous error correction is extremely reduced.

[Means for solving the problem]

According to the present invention, a data sequence in which each symbol of a digital information signal, for example, a digital audio signal is double-encoded by a first error correction code (C1 code) and a second error correction code (C2 code) is, for example, a digital signal. This is an error correction device that is reproduced from a disk and input.

According to the present invention, a C1 decoder that decodes a C1 code with respect to a data sequence and generates a pointer P1 in response to the presence of an error, data and a pointer P1 from the C1 decoder are supplied, and an error position and an error value And a C2 decoder that performs decoding of the C2 code and generates a flag P2 indicating whether the received data is valid or invalid.When decoding with the C2 decoder, each code sequence of the C2 code is provided. In the case where the number of pointers P1 generated by the C1 decoder is equal to or greater than a predetermined number, a flag indicating invalid data is provided at both the position where the pointer P1 is standing and the symbol indicated by the error position obtained by decoding the C2 code. An error correction device characterized in that the error is generated.

[Action]

According to the present invention, when decoding is performed by the C2 decoder, not only the number of pointers P1 from the C1 decoder but also an error position calculated by the C2 decoder is flagged, so that error data is Can be reliably flagged.

〔Example〕

An embodiment in which the present invention is applied to a digital audio disc reproducing apparatus will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a digital disk on which a digital audio signal is spirally recorded in a predetermined format. The disk 1 is rotated by a spindle motor. In this case, the spindle motor 2 is controlled by the spindle servo circuit 3 so that the disk 1 rotates at a constant linear velocity.

Reference numeral 4 denotes an optical head, an optical lid 4 is a laser source for generating a laser beam for reading,
Optical system such as beam splitter and objective lens, disk 1
And a light receiving element for the reflected laser light from the light source. The optical head 4 is driven by a thread feed motor 5
The disk 1 can be moved in the radial direction. The optical head 4 can be displaced in two directions, that is, a direction perpendicular to the signal surface of the disk 1 and a direction parallel thereto, and is controlled so that focusing and tracking of the laser beam during reproduction are always good. . For this purpose, a focus servo circuit 7 and a tracking servo circuit 8 are provided.

The reproduction signal of the optical head 4 is supplied to the RF amplifier 9. The optical head 4 is provided with, for example, a focus error detecting unit composed of a combination of a four-divided detector with a cylindrical lens and a tracking error detecting unit using three laser spots. The output signal of the RF amplifier 9 is supplied to the clock extraction circuit 10. The output (data and clock) of the clock extraction circuit 10 is supplied to the frame synchronization detection circuit 11.

The digital signal stored on the disk 1 is EFM
Modulated. EFM modulation is a method of block-converting 8-bit data into a preferable 14-bit (ie, a 14-bit pattern in which the minimum inversion interval of the modulated signal is long and its low-frequency component is small). The digital demodulation circuit 12 is configured to perform EFM demodulation. The bit clock extracted by the clock extraction circuit 10 and the frame synchronization signal detected by the frame synchronization detection circuit 11 are supplied to the spindle servo circuit 3 and also to a digital demodulation circuit 12 (not shown).

Reference numeral 13 denotes a subcode demodulation circuit that demodulates a subcoding signal for control and display. Subcode demodulation circuit
Sub-coding signal from 13 is system controller
Supplied to 14. The system controller 14 is provided with a CPU for rotating the disk 1, feeding the thread,
The reading operation of the optical head 4 and the like are controlled by the system controller 14. A control command from an operation button 15 is supplied to the system controller 14. That is, the system controller 14 performs control for performing a search for a desired music using the sub-coding signal.

Main digital data output from the digital demodulation circuit 12 is supplied to the RAM 17 and the error correction circuit 18 via the RAM controller 16. This RAM controller 16, RAM17
The error correction circuit 18 removes the time axis fluctuation and performs error correction, and the main digital data is extracted from the output.

The reproduction data from the RAM controller 16 is used as the interpolation circuit 1
The error data which is supplied to 9 and cannot be corrected is corrected. The reproduction data is divided into left and right channels of the stereo signal by the interpolation circuit 19, and the data of each channel is converted into an analog signal by the D / A converters 20 and 21, and the output terminal is output through the low-pass filters 22 and 23, respectively.
Taken out on 24, 25.

RAM controller 16, RAM 17, and error correction circuit described above
The error correction performed by 18 will be described. Third
The figure shows a decoder written in order of error correction for ease of understanding. On the other hand, FIG. 2 shows a configuration of an encoder relating to data recorded on a master disk when a disk is manufactured.

In FIG. 2, reference numeral 31 denotes a scramble circuit. The scrambling circuit 31 _generates even-numbered sample data L _6n , R _6n , L _{6n + 2} ,
R _{6n + 2} , L _{6n + 4} , R _{6n + 4} , and odd-numbered sample data L _{6n + 1} , R
_It interleaves with _{6n + 1} , _{L6n + 3} , _{R6n + 3} , _{L6n + 5} , and _{R6n + 5} and converts the symbol position in one frame. The 16 bits of one sample data are divided into upper 8 bits and lower 8 bits, and the encoding process is performed with 8 bits as one symbol. 12 sample data (24 symbols) of music data is supplied to the scramble circuit 31, 24 symbols output from the scramble circuit 31 are supplied to the C2 decoder 32, and encoding of the (28,24) Reed-Solomon code is performed. Done.

The parity of 4 symbols and the data of 24 symbols generated in the output of the C2 encoder 32 are supplied to the interleave circuit 33. The interleave circuit 33 is provided to improve the burst error correction capability by separating the recording positions of 28 symbols included in one C2 code sequence. 28 symbols output from the interleave circuit 33 are supplied to the C1 encoder 34, where the (32, 28) Reed-Solomon code is encoded. 32 symbols including four parities formed by the C1 encoder 34 are supplied to the delay circuit 35. This delay circuit 35 is for delaying only odd symbols in one frame. A sub-coding signal of one symbol is added to 32 symbols output from the delay circuit 35 to form a recording signal of a predetermined format.

The reproduction signal from the disk is EFM-demodulated, supplied to the decoder shown in FIG. 3, and subjected to error correction processing. 32 symbols in one frame are supplied to the delay circuit 45, only the even symbols are delayed, the delay given by the delay circuit 35 of the encoder is canceled, and the delay is supplied to the C1 decoder 44.
(2, 28) The error of the Reed-Solomon code is corrected, and the corrected data and the formed pointer are supplied to the deinterleave circuit 43. Deinterleave circuit 43
Performs the process of restoring the interleave performed by the interleave circuit 33, and the output of the deinterleave circuit 43 is supplied to the C2 decoder 42.

The pointer of each symbol from the C1 decoder 44 is also subjected to the same deinterleaving processing as the data in the deinterleaving circuit 43. The deinterleaving is performed when the RAM controller 16 generates a predetermined address for the RAM 17. The pointer from the C1 decoder 44 is written in a part of the memory area of the RAM 17, and receives the same address control as that of the data. The C2 decoder 42 decodes the (28, 24) Reed-Solomon code using the pointer after the C1 decoding. The data and the pointer after the error correction are supplied from the C2 decoder 42 to the descramble circuit 41. The descramble circuit 41 performs the reverse operation of the scramble circuit 31,
In the output, reproduced data of 24 symbols is obtained in the same order as the original order.

A decoding method performed by the C1 decoder 44 and the C2 decoder 42 will be described. First, the C1 decoder 44 performs the following decoding. Syndrome calculated from playback data
S1 and a pointer to the C2 decoder 42 as P1.

(1) When the syndrome S1 has no error No correction is performed and (P1 = ‘0 ').

(2) When a single error is detected from the syndrome S1 The single error is corrected and is set to (P1 = '0').

(3) When a double error is detected from syndrome S1 Double error correction is performed and (P1 = ‘1 ').

(4) When three or more errors are detected from syndrome S1, no correction is made and (P1 = '1').

That is, the C1 decoder 44 performs even the double error correction. At that time, there is a possibility that an erroneous correction is made.
Check again with C2 decryption as '1').

Next, decoding in the C2 decoder 42 will be described. The syndrome calculated by the C2 decoder 42 is S2, the pointer formed by the C1 decoder 44 is P1, the N (P1) is the number of '1' pointers among the 28 symbols input to the C2 decoder 42, L (P1 =
S2) is the number of “1” pointers that match the error position calculated from the syndrome S2, and P2 is the interpolation flag passed to the interpolation circuit 19.

(1) When it is determined that there is no error from the syndrome S2, no correction is made and (P2 = ‘0 ').

(2) When a single error is detected from the syndrome S2 The single error is corrected and set to (P2 = ‘0 ').

(3) When a double error is detected from the syndrome S2 When iN (P1) ≦ 4 and L (P1 = S2) = 2, double error correction is performed and (P2 = '0').

ii. N (P1) ≦ 3 and L (P1 = S2) = 1 or N (P1) ≦
2 and L (P1 = S2) = 0, no correction is performed,
(P2 = '1').

At times other than iii.i. and ii., no correction is performed, and a pointer P2 of '1' is set at the calculated error position and the position of the pointer P1.

(4) When three or more errors are detected from the syndrome S2 When iN (P1) ≦ 2, no correction is performed and (P2 = '1')
And

ii. In cases other than the above, no correction is made and P1 is used as is in P2
And

The above-described decoding operation can be performed for each 8-bit symbol. When even one of the two symbols constituting one sample data of the digital audio signal contains an error, the sample data needs to be interpolated by the interpolation circuit 19.

The present invention includes, in the above-described decoding operation of the C2 decoder 42,
"(3) When a double error is detected from the syndrome S2 and other than iii.i. and ii., No correction is performed, and a pointer of" 1 "is set at the calculated error position and the position of the pointer P1. This is characterized by the generation of an interpolation flag. This operation will be further described with reference to FIG.

FIG. 4A shows one sequence (24 symbols) of the C2 code supplied to the C2 decoder 42. Now, the C1 decoder 44 shown in FIG.
Are supplied with the four pointers P1 of "1", and the error position equation is calculated by the C2 decoder 42 to calculate the error position (i, j) shown in FIG. 4C. An interpolation flag (P2 = '1') indicating that there is an error in the symbol indicated by the hatched position shown in FIG. 4D is added. Also, three '1's from the C1 decoder 44 shown in FIG.
As shown in FIG. 4F, if the error position (i, j) whose position does not match this pointer is calculated by the C2 decoder 42, as shown in FIG. An interpolation flag (P2 = '1') is added to the position of the oblique line shown in G.

Therefore, an interpolation flag can be generated at an error position where both the C1 decoding and the C2 decoding are detected, and the interpolation flag can be added to data with a possibility of error without fail.

It should be noted that the present invention is not limited to the case where digital data is reproduced from a disc,
The present invention is also applicable to a case where a digital video signal is reproduced from a magnetic tape. Further, as the error correction code, an error correction code such as an adjacent code other than the Reed-Solomon code may be used.

〔The invention's effect〕

According to the present invention, it is possible to generate a flag indicating that data is invalid at an error position detected using two error correction codes, and therefore, it is possible to prevent the error data from being mistaken as valid data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire configuration of an embodiment in which the present invention is applied to a digital audio disk reproducing apparatus, and FIG. 2 is a block diagram used for explaining the coding of an error correction code according to an embodiment of the present invention. FIG. 3 is a block diagram used for explaining the decoding of the error correction code according to one embodiment of the present invention, and FIG. 4 is used for explaining the formation of a flag in the decoding of the error correction code according to one embodiment of the present invention. FIG. 1: disk, 18: error correction circuit, 19: interpolation circuit, 44: C1
Decoder, 42: C2 decoder.

Claims (1)

(57) [Claims] 1. An error correction apparatus for receiving a data sequence in which each symbol of a digital information signal is double-encoded by a first error correction code and a second error correction code, wherein the data sequence is A first decoder that decodes the first error correction code and generates a pointer in response to the presence of an error; and data and the pointer from the first decoder are supplied, and an error position and an error value are provided. And a second decoder that decodes the second error correction code and generates a flag indicating whether the received data is valid or invalid. In this case, in each code sequence of the second error correction code, when the number of pointers generated by the first decoder is equal to or more than a predetermined number, Error correction device characterized by both of the symbols represented by the error position obtained by the decoding of the second error correction code so as to generate a flag indicating the invalidity of the data.