JPH0687348B2 - Digital data transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial application" The present invention uses a digital disk in which a 2-channel digital audio signal is recorded, and a digital disk in which digital data other than the 2-channel digital audio signal is recorded. The present invention relates to a digital data transmission method capable of reproducing data.

“Background Technology and Its Problems” A system that uses an optical digital audio disc (called a compact disc) is a disc system that can reproduce high-quality stereo music. If this disk system can reproduce digital data such as character data, display data, program data, etc. in addition to stereo music signals, without changing the configuration of the player, add a display device. Thus, it is possible to realize a device for reproducing visual information such as charts and statistics by graphic images, a picture book by still images, and a video game device, and it is possible to broaden the application range of the compact disk system. The current compact disk has a data storage capacity of about 500 bytes, which is an advantage over the conventional flexible disk.

Like digital signals, digital data cannot be subjected to error correction by means of interpolation processing such as average value interpolation, and it is desirable that the error rate of reproduced data is better than that of digital signals. The error rate of the current compact disk, 10 ^-11 , should be 10 ^-13 or more when used for storing digital data.
Since the reproduction signal processing circuit of the current compact disc player is configured as an LSI, it is desirable that the error rate as described above can be realized by using the hardware of this reproduction signal processing circuit.

Therefore, the object of the present invention is to enable the transmission of digital data having an error rate lower than that of the current compact disc, and to use the compact disc for storing digital data. To provide a method.

Another object of the present invention is to use the hardware of the existing compact disc reproducing apparatus to reproduce not only a new disc in which digital data such as programs and graphics are stored but also the existing compact disc. It is to provide a digital data transmission method.

[Summary of the Invention] According to the present invention, an input digital audio signal is subjected to error correction coding for each error correction block to generate a first check word, and after interleaving the digital audio signal and the first check word. , A second check word is generated by further performing error correction encoding, and the second check word is generated.
And a digital data transmission method for transmitting the second checkword, digital data other than the input digital audio signal is error-correction-encoded to generate a third checkword, and an error is generated by the digital data and the third checkword. After forming the correction block, the same error correction coding as that for the digital audio signal is performed, and the digital data, the first, the second and the third
The digital data transmission method is characterized by transmitting the check word of.

[Example] An example of the present invention will be described below.

The data structure when the signal recorded on the compact disc is audio data (that is, the current compact disc) will be described with reference to FIGS. 1 and 2.

FIG. 1 shows a data stream recorded on a compact disc. One frame is 588 bits of recorded data, and a 3-bit DC suppression bit RB is provided after the frame synchronization pulse ES of a specific bit pattern for each frame, and further 14 bits each of 0 bits. The data bit DB of ~ 32 and the DC component suppression bit RB of 3 bits are provided alternately. The 0th one of the data bits DB is called a sub-coding signal or user's bit, and is used for disk reproduction control and related information display.
The 1st to 12th, 17th to 28th data bit DBs are allocated to the audio data of the main channel, and the remaining 13th to 16th, 29th.
The 32nd data bit DB is assigned to the parity data of the error correction code of the main channel. In each data bit DB, 8 bits of data are converted into 14 bits by 8-14 conversion at the time of recording.

Fig. 2 shows each data bit DB except the DC suppression bit.
Shows 8 bits, and 98 frames are arranged in parallel in order. Subcoding signal P of 0 and 1 frames
˜W form a sync pattern which is a predetermined bit pattern. Regarding the Q channel, the CRC code for error detection is inserted in 16 frames on the terminal side of the 98 frames.

The P-channel is a flag that indicates a pose and music. The P-channel is a low level for music, a high level for pause, and a pulse of 2 Hz cycle in the lead-out section. Therefore,
By detecting and counting this P-channel, it becomes possible to select and play the specified music. The Q-channel can perform the same kind of control in a more complicated manner. For example, the information of the Q-channel is taken into a micro computer provided in the disc reproducing device, and the music is immediately reproduced while the music is being reproduced. It is possible to select a random song. Other than this, R-channel to W-channel display the songwriter, composer, commentary, poem, etc. of the song recorded on the disc.
Used for audio commentary.

Of the 98 bits of the Q channel, the first 2 bits are used as the sync pattern, the next 4 bits are used as the control bits, the next 4 bits are used as the address bits, and the subsequent 72 bits are used as the data bits. ， At the end, CRC code for error detection is added. Data Bit 7
The track number code TNR and the index code X are included in the two bits. Track number code TNR is 00
The index code X can also change from 00 to 99. In addition, the Q channel data includes a time display code that indicates the time of the song and pause, and a time display code that displays the absolute time that continuously changes from the beginning of the program area of the compact disc to the end of the outermost peripheral side. Be done. Each of these time display codes is composed of a 2-digit minute, second, and frame code. One second is divided into 75 frames. In order to access a compact disc in units shorter than music, such as digital data, the above-mentioned time display code regarding absolute time is used.

In this embodiment, when recording digital data as main channel data, the data structure of the P and Q channels of the sub-coding signal is the same as that of the compact disk.

FIG. 3 shows a recording format of digital data. Digital data has (588 × 4 bytes = 2352 bytes) as one sector, and FIG. 3 shows the data structure of this one sector. One sector consists of a 12-byte sector synchronization signal, 4-byte header, 2048-byte data (user data), and 4-byte error detection code such as CR.
It consists of a C code, an extension space of 8 bytes, a P-code parity of 172 bytes (referred to as P parity), and a Q-code parity of 104 bytes (referred to as Q parity). One sector is configured so that only the data that is finally needed can be cut out.

FIG. 4 shows the structure of one sector in more detail. In Fig. 4, the left channel and right channel show the correspondence with the sample data of the left and right channels of stereo music data, and each channel has 16 bits as one word,
L is the lowest bit and M is the highest bit. As mentioned above, in the case of stereo music data, within the section specified by the frame sync signal (6 x 6 x 2 = 24 bytes)
Data is recorded, if digital data is recorded with the same signal format (Fig. 1) as stereo music data, one block (2352 bytes) is recorded from the 0th frame to the 97th frame. Therefore, it is possible to record a digital day without breaking the 98 frames of the change cycle of the sub-coding signal.

The first 1 byte of digital data of 1 block is a bit of all 0s, the subsequent 10 bytes is a bit of all 1, and the subsequent 1 byte is a bit of all 0s. This 12-byte section is used as a sector synchronization signal indicating the beginning of one block of digital data. After the sector synchronization signal, a 1-minute minute, second, sector, and mode header is added.

This header is the address of one sector, and one sector is
Like a frame, it takes 1 second in 75 sectors. The mode data indicates the type of data of the one sector. In FIG. 4, D0001 to D2336 indicate byte numbers of one sector excluding the sector synchronization signal and header.

D0001 to D2048 are user data, D2049 to D2052 are error detection codes, D2053 to D2060 are spaces, D2061 to D2232 are P parity, D2233 to D2336 are Q.
Parity.

To explain the code structure of the error detection code and the error correction code, FIG. 5 shows the structure of one sector expressed in word units. In FIG. 5, Wi indicates the word number. W
0000 and W0001 are headers, W0002 to W1025 are user data, W1026 and W1027 are error detection codes, W1028 to W1031 are spaces, W1032 to W1117 are P parity, and W1118 to W1169 are Q parity. Is. The error detection code is encoded by header and user data (W0
000 to W1027), and the error correction code is encoded in W000 to W1169 117 excluding the sector synchronization signal.
Performed on 0 words (2340 bytes).

The CRC code used as the error detection code has, for example, the following generator polynomial p (x).

^{p (x) = (x 16} + x 15 + x 2 +1) (x 16 + x 2 + x + 1) the header and that the user data was expressed by a polynomial in the GF (2 ^8), the remainder when divided by the generating polynomial above Is a 4-byte CRC code. This error detection code is used for the purpose of checking the final reliability after error correction of the reproduction signal reproduced from the disk. In addition to this, it may be used for the purpose of preventing erroneous error correction when error correction is performed.

The error correction code divides each word of W0000 to W1169 of one sector into two parts, each of the upper byte including the most significant bit M and the lower byte including the least significant bit L, and a data plane consisting of the upper byte of 1170 bytes, It is performed for each data plane including the data plane composed of the lower byte of 1170 bytes. The encoding performed in each of the upper byte data plane and the lower byte data plane is the same.

FIG. 6 is used for explaining the encoding regarding the data plane composed of either the upper byte or the lower byte. The data plane consists of 1032 bytes consisting of header and user data, and this 1032 bytes is a two-dimensional array of (24 × 43). As shown in FIG. 6, each byte distinguished by the word number is arranged from the first line to the 24th line in order. On this (24 × 43) data plane, an error correction code that is a combination of complete cross interleave and Reed-Solomon code is encoded. This error-correcting code is interleaved so that each 1-byte symbol is included in two code sequences located in different directions on a 1032-byte data plane, and the Reed-Solomon code is encoded for each code sequence. Is to do.

As shown in FIG. 6, the Reed-Solomon code of (26,24), where 1 byte is 1 symbol for every 24 bytes located in each column of 0 to 42, is coded and located below each column. P parity is added as 2 bytes. Therefore, the code sequence including P parity (referred to as P sequence) consists of 26 symbols. For example, the following polynomial p (x) is used as the (26,24) Reed-Solomon code on GF (2 ⁸ ).

When the primitive element a on p (x) = x ⁸ + x ⁴ + x ³ + x ² +1 GF (2 ⁸ ) is (a = 00000010), the parity matrix HP is as shown below.

Parity symbol P0 = D (43 × 24 + N) and P1 = D (43
× 25 + N) (N = 0,1,2, ... 41,42) is the reproduced P
When the sequence is VP, it is assumed that the following equation is satisfied.

HP × VP = 0 where Is. As an example, when (N = 0), it is located in the first example [D0000, D0043, D0086, D0129, D0172, ... D0946,
D0989, D1032 (= P0), D1075 (= P1)] becomes one reproduced P sequence.

Also, for every 43 bytes located diagonally in the data plane, one byte is taken as one symbol (45,43) Reed-Solomon code is coded, and as two bytes located at the 27th and 28th rows. , Q Parity is added. Therefore, the Q sequence consists of 45 symbols. GF (2
⁸ ) For example, the following polynomial p (x) is used as the (45,43) Reed-Solomon code.

When the primitive element a on p (x) = x ⁸ + x ⁴ + x ³ + x ² +1 GF (2 ⁸ ) is (a = 00000010), the parity matrix HP is as shown below.

Parity symbol Q0 = D (43 × 26 + N) and Q1 = D (44
X26 + N) is assumed to satisfy the following equation when the reproduced Q sequence is VP.

HP × VP = 0 where Is. (N = 0,1,2,3 ... 24,25) and M = 0,1,2,3
...... 41, 42). If (44 x M + 43 x N)> 1117
When the relationship of (44 × M + 43 × N) occurs, (44 × M + 43 × N) becomes (44 × M
+ 43 × N-1118).

To make it easier to understand the Q-sequence interleave relationship, (N = 0,1,2, ... 24,25) is the vertical direction, and (M = 0,1,
2, …… 41,42) is the horizontal direction and includes P parity 1118
Rearranging the arrangement of the symbols gives the one shown in FIG. Each row arranged in the horizontal direction in FIG. 7 forms one Q series. For example, when (N = 0), [D0000, D0044, D0088, D0
132, D0176, ..., D0642, D0686, D0730, D1118 (= Q0), D11
44 (= Q1)] forms one Q code sequence. Further, in FIG. 7, each column arranged in the vertical direction forms a P series. Therefore, FIG. 7 shows a product of one type in which the (26,24) Reed-Solomon code is encoded in the vertical direction and the (45,43) Reed-Solomon code is encoded in the horizontal direction. It shows the configuration of the code.

Since these two Reed-Solomon codes both have 2 symbols of parity symbols, even if there is no error flag, it is possible to correct up to 1 symbol error, and the error flag determines the error location. It is possible to correct errors of up to 2 symbols while doing so. As this error flag, the decoding result of CIR C (Cross Interleaved Reed-Solomon code), which is standardly used for digital disks, can be used. Therefore, the decoding of the Reed-Solomon code in the vertical direction (referred to as P decoding) and the decoding of the Reed-Solomon code in the horizontal direction (referred to as Q decoding) in FIG. 7 are alternately performed, for example (P decoding → Q decoding → By performing (P decoding → Q decoding), it is possible to correct all error patterns except when 3 or more symbols are error symbols, regardless of both P and Q sequences. . However, since the cross interleaving process is performed, the error correction capability can be further improved by dispersing the burst error.

The above-mentioned error correction code is similarly applied to two data planes which are obtained by dividing a header of one sector and a total of 1118 words of user data into an upper byte and a lower byte. The data planes that have been subjected to this error correction coding are combined, and the sector synchronization signal is added,
It has a one-sector configuration shown in FIG. 4 or FIG. This one sector is supplied to a digital disk CIRC code encoder instead of audio data, subjected to error correction coding processing, and further converted by the formatter into storage data as shown in FIG. This recorded data is supplied to the cutting machine of the digital disc.

FIG. 8 shows the configuration of an embodiment of the demodulation system according to the present invention. In FIG. 8, reference numeral 1 denotes a digital disk in which the digital signal of the above-mentioned format is spirally recorded. The disk 1 is rotated by a spindle motor 2. In this case, the spindle motor 2 is controlled by the spindle servo circuit 3 so that the disk 1 rotates at a constant linear velocity.

4 indicates an optical head, and the optical head 4
Has a laser source for generating a laser beam for reading, an optical system such as a beam splitter, an objective lens, and a light receiving element for the laser beam reflected by the disk 1. The optical head 4 can be moved in the radial direction of the disk 1 by a thread feed motor 5. The thread feed motor 5 is driven by a thread drive circuit 6. Further, the optical head 4 is displaceable in two directions, a direction orthogonal to the signal surface of the disk 1 and a direction parallel to the signal surface, and is controlled so that focusing and tracking of laser light during reproduction are always good. To be done. For this purpose, the focus servo circuit 7
And a tracking servo circuit 8 are provided.

The reproduction signal of the optical head 4 is supplied to the RF amplifier 9. The optical head 4 is provided with, for example, a focus error detection section formed of a combination of a cylindrical lens and a four-divided detector and a tracking error detection section using three laser spots. RF amplifier 9
Is output to the clock extraction circuit 10. The output (data and clock) of the clock extraction circuit 10 is supplied to the frame synchronization detection circuit 11. The digital signal stored in the disk 1 is EFM-modulated. EFM modulation is a method of block-converting 8-bit data into a preferable pattern of 14 bits (that is, 14 bits in which the minimum inversion time of the modulated signal is long and the low frequency component is small). The digital demodulation circuit 12 is configured to perform EFM demodulation. The bit clock extracted by the clock extraction circuit 10 and the frame synchronization signal detected by the frame synchronization detection circuit 11 are supplied to the digital demodulation circuit 12 and the spindle servo circuit 3.

In the digital demodulation circuit 12, the sub-coding signal is separated, and this sub-coding signal is supplied to the system controller 14 via the buffer memory 13. A CPU is provided in the system controller 14, and the disk 1
Rotation operation, thread feed operation, optical head 4
The reading operation and the like are controlled by the system controller 14. A control command is supplied to the system controller 14 via an interface 20 described later. That is, the disc 1 using the sub-coding signal
The system controller 14 controls the reading of the desired digital signal from the.

The main digital data output from the digital demodulation circuit 12 is supplied to the RAM 16 and the error correction circuit 17 via the RAM controller 15. The RAM controller 15, the RAM 16 and the error correction circuit 17 perform the processing of removing the time base fluctuation and the error correction, and the main digital data is taken out from the output. The output of the RAM controller 15 is supplied to the demultiplexer 18. Demultiplexer 18
Is controlled by whether the disc being played is a compact disc for stereo music signals or a digital data disc for storing digital data.
The system controller 14 switches the output system path. As an example, the controller bit of the Q channel of the sub-coding signal recorded in the lead intra of the disc 1 identifies whether the disc being reproduced is for stereo music signals or for storing digital data. It Along with this switching of the output system path, a control signal indicating the disc type discrimination result is supplied to the RAM controller 15, and an additional error correction operation is performed on the reproduction output of the disc for digital data storage.

A data conversion circuit 19 is connected to the output system path selected at the time of disk reproduction for digital data storage. A reproduction sub-coding signal is supplied from the buffer memory 13 to the data conversion circuit 19 together with the reproduction digital data, and the reproduction data is converted into a serial signal form. FIG. 9 shows an example of the word format of the serial signal output from the data conversion circuit 19. This serial signal has 32 bits as one word. The first 4 bits are the preamble, the next 4 bits are the auxiliary bit of data, and the next 20 bits are the data. Digital data
When 16 bits are 1 word, the lowest bit (LSB)
From 16 bits are inserted. Four bits are added after the digital data. Of these four bits, the bit indicated by V is a flag indicating whether or not the word is valid, the bit indicated by U is each bit of the subcoding signal, and the bit indicated by C identifies the channel. It is a bit that does, and P is a parity bit. The bit U of the sub-coding signal is inserted one by one in each of the word formats and transmitted sequentially.

The above-mentioned word format is considered in consideration of audio data, and is supplied to the interface 20 in the next stage, and is converted into a standard computer data format. Further, data for the system controller 14 is supplied from the microcomputer system 21 via the interface 20. The microcomputer system 21 specifies a read address, and supplies a drive control signal such as a start signal to the interface 20 and the system controller 14 in addition to the read address.

An interpolation circuit 22 is connected to the output path of the demultiplexer 18 selected when the disk being reproduced is for stereo music signals, and error data that cannot be corrected is corrected. It is divided into left and right channels by the interpolation circuit 22, and the data of each channel is converted into an analog signal by the D / A converters 23L and 23R, and is taken out to the output terminals 25L and 25R via the low pass filters 24L and 24R, respectively.

In one embodiment of the present invention, the buffer memory 13 removes the time-axis variation of the sub-coating signal. This time base correction is the same as that performed by the RAM controller 15 and the RAM 16 for the digital signal of the main channel. That is, the RAM controller 15 forms a write clock synchronized with the reproduction signal from the detected frame synchronization signal, and the RAM clock is generated by this write clock.
When writing a digital signal to 16 and reading a digital signal from RAM 16, a read clock formed from the output of the crystal oscillator is used. The write clock and the read clock are used for writing and reading the sub-coding signal to and from the buffer memory 13. Therefore, the sub-coding signal read from the buffer memory 13 does not include the time axis fluctuation, and the time relationship with the digital signal of the main channel is prevented from changing due to the time axis fluctuation. .

In one embodiment of the present invention, at the time of disk reproduction for digital data storage, the microcomputer computer system 21 first executes a read command to a predetermined address. This address is the Q-channel absolute time display code itself, and is supplied to the system controller 14 via the interface 20.
The system controller 14 controls the thread drive circuit 6 and moves the optical head 4 to a position near the target reading position while watching the sub-coding signal reproduced by the optical head 4. In this example, since the reproduced sub-coding signal contains an error, the set sub-coding signal is not reproduced and the access operation is not terminated. I'm trying to get started. Then, when the reproduced sub-coding signal coincides with the specified address, or the reproduction is started from the correct sub-code signal position in the vicinity, and the frame synchronization signal is counted. I'm trying to catch the block that does.

FIG. 10 shows an example of an error correction circuit at the time of disk reproduction for digital data storage. In FIG. 10, for simplification, it is used as both the audio signal disk and the digital data storage disk. The CIRC code decoder is omitted. That is, the reproduced data excluding the sector synchronization signal of one sector stored in the RAM 16 is the data after the decoding of the CIRC code, and an error flag indicating the presence or absence of an error is added to each symbol.

Each symbol is read from RAM16 together with the error flag,
The P-sequence of 26 symbols is supplied to the P-decoder 32 via the data bus 31. In the P decoder 32, a 2-symbol error in one P sequence is corrected using the error flag obtained by decoding the CIRC code (26,24) Reed-Solomon code is decoded, and the symbol after this combination But
Written to RAM16. In this case, when the error is corrected by the P decoder 32, the error flag related to the symbol is cleared. When the P decoding for one sector is completed, the data read from the RAM 16 is supplied to the Q decoder 33 via the data bus 31.

Deinterleaving is performed by controlling the address of the RAM 16, and the Q decoder 33 corrects a 2-symbol error in one Q sequence for each Q sequence of one sector (45, 43).
The Reed-Solomon code is decoded. When the error is corrected by this decoding, the error flag related to the symbol is cleared. Next, P decoding is performed again and Q decoding is further performed. Thus, P decoding and Q
After the decoding is alternately performed twice, the reproduced digital data after the error correction from the RAM 16 is supplied to the CRC checker 34, the error is detected, and the error detection result is supplied to the output gate 35. The output gate 35 sets an error flag for the data determined to have an error.

The error detection result of the CRC checker 34 can also be used for error correction in the P decoder 32 and the Q decoder 33. In the P decoder 32 and the Q decoder 33, the C
The error flag generated when decoding the IRC code is used. Therefore, by referring to the error detection result of the CRC checker 34 at the time of P decoding and Q decoding, the CIRC
It is possible to prevent an erroneous correction operation when the error flag of the code is incorrect.

Another embodiment of the present invention will be described with reference to FIGS. 11 and 12. In this example, a new encoder and decoder are added to the encoder and its decoder of CIRC code applied to the disc for digital audio signals.

FIG. 11 shows the configuration of the encoder for the data recorded on the master disk when creating the digital disk. This encoder and the decoder shown in FIG. 12 represent both the case of recording and reproducing a digital audio signal and the case of recording and reproducing digital data. Further, the encoder or decoder is actually composed of the RAM, the RAM controller, the error correction encoder or the error correction decoder as described above, but in FIG. 11 and FIG. For simplicity, the circuit block is configured according to the order of signal processing. At the time of recording and reproducing the digital audio signal, the C ₃ encoder 46 in FIG. 11 is not used and the C ₃ decoder 56 in FIG. 12 is not used.

The encoding and decoding of the CIRC code performed on the digital audio signal will be described first. In FIG. 11, reference numeral 41 indicates a scramble circuit. The scrambling circuit 41, L channel and R channel of each of the even sample data _{L 6 n, R 6 n,} L 6 n +2, R 6 n +2, L 6 n +4, R 6 n +4 and odd Sample data L ₆ n ₊₁ , R ₆ n ₊₁ , L ₆ n ₊₃ , R ₆ n ₊₃ , L ₆ n ₊₅ , R ₆ n ₊₅ ,
And the position of the symbol within one frame are converted. The 16 bits of 1 sample data are divided into the upper 8 bits and the lower 8 bits, and the 8 bits are treated as one symbol to be encoded.
12 sample data (24 symbols) of music data is supplied to the scramble circuit 41, 24 symbols output from the scramble circuit 41 are supplied to the C ₂ encoder 42, and (28,2
4) Reed-Solomon code is encoded.

The parity of 4 symbols generated at the output of this C ₂ encoder 42
The 24-symbol data and the interleave circuit 43 are supplied. The interleave circuit 43 is provided in order to improve the burst error correction capability by separating the recording positions of 28 symbols contained in one C ₂ code sequence. The 28 symbols output from the interleave circuit 43 are supplied to the C ₁ encoder 44, and the (32,28) Reed-Solomon code is encoded. 32 symbols including 4 parities formed by the C ₁ encoder 44 are supplied to the delay circuit 45. The delay circuit 45 is for delaying only the odd symbols in one frame. A sub-coding signal of 1 symbol is added to the 32 symbols output from the delay circuit 45,
After that, EFM modulation is performed. At the time of this EFM modulation, a frame synchronization signal is added to form a recording signal as shown in FIG.

The reproduced signal from the disk is EFM demodulated and is shown in Fig. 12.
It is supplied to the CIRC code decoder and undergoes error correction processing. 32 symbols in one frame are supplied to the delay circuit 55, only even symbols are delayed, and the delay circuit 45 of the encoder 45
The delay given by ₁ is cancelled, supplied to the C ₁ decoder 54, error correction of the (32,28) Reed-Solomon code is performed, and the corrected data and pointer are supplied to the deinterleave circuit 53. The deinterleave circuit 53 is
The interleaving performed by the interleaving circuit 43 is restored, and the output of the deinterleaving circuit 53 is
It is supplied to the C ₂ decoder 52.

The pointer of each symbol generated by the C ₁ decoding is also subjected to the same deinterleaving process as the data in the deinterleave circuit 53. For deinterleave, RAM controller is RA
This is done by generating a predetermined address for M. C
_The pointer formed by the _1- decoder 54 is written in a partial memory area of the RAM and is subjected to the same address control as data. The C ₂ decoder 52 uses the pointer for C ₁ decoding (28,
24) The Reed-Solomon code is decoded. C ₂ decoder 52
The data after error correction and the pointer are supplied to the descrambling circuit 51. Day scramble circuit 51
Performs an operation reverse to that of the scramble circuit 41, and at the output thereof, reproduced data of 24 symbols can be obtained in the original order.

When recording digital data other than digital stereo audio signals, audio sample data L ₆ n
20 symbols are supplied to the C ₃ encoder 46 without supplying 4 symbols corresponding to ₊₅ and R ₆ n ₊₅ . This C ₃ encoder 46 is (24,2
0) Reed-Solomon code is encoded to generate 4 symbol parity symbols. The four symbol parity symbols are supplied to the scramble circuit 41 as data corresponding to the audio sample data L ₆ n ₊₅ and R ₆ n ₊₅ . The subsequent signal processing is the same as that of the digital audio signal described above.

Further, 32 symbols in one frame reproduced from the digital disc are processed by the delay circuit 55, the C ₁ decoder 54, the deinterleave circuit 53, the C ₂ decoder 52, and the descramble circuit 51 as in the case of decoding the digital audio signal. Get decrypted. Then, the output of the descramble circuit 51 is supplied to the C ₃ decoder 56. The C ₃ decoder 56 is a (24,20) Reed-Solomon code decoder corresponding to the C ₃ encoder 46 and is capable of correcting a 2-symbol error included in one code sequence. Furthermore, by using the error flag formed by the CIRC code, it is possible to correct up to 4 symbol errors. Therefore, when playing a disc for storing digital data, 20 symbols of data are played in one frame.

In another embodiment of the invention described above, the C ₃ encoder 46 is
It can be inserted between the scramble circuit 41 and the C ₂ encoder 42, and the C ₃ encoder 56 can be inserted between the C ₂ decoder 52 and the descrambling circuit 51. However, CIRC
Since the encoder and the CIRC decoder are already configured in the LSI circuit, as shown in FIGS. 11 and 12, the C ₃ encoder 46 is provided at the entrance of the CIRC encoder and the exit of the CIRC decoder, respectively. And C ₃
The configuration in which the encoder 56 is connected is preferable in that there is no need to newly design the LSI.

[Advantages of the Invention] According to the present invention, by using a disc for digital audio, it is possible to read digital data such as charactor data, graphics data, and programs, instead of digital audio signals. Can be According to the present invention, at the time of a disc for storing digital data, since the digital data subjected to the CIRC code encoding process is subjected to another error correction encoding process, the error rate of the reproduced data can be made extremely low. it can.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIG. 2 are schematic diagrams used for explaining a recording signal of a compact disk, and FIG. 3 is a schematic diagram showing a data structure of one sector when recording digital data, FIG. 4 is a schematic diagram showing a byte unit structure of this one sector, FIG. 5 is a schematic diagram showing a word unit structure of this one sector, and FIGS. 6 and 7 are related to digital data of one sector. FIG. 8 is a schematic diagram used for explaining the interleave relation of the error correction code, and FIG. 8 is a block diagram of one embodiment of the present invention.
FIG. 9 is a schematic diagram showing an example of a signal format when transmitting reproduced data from a disk, and FIG. 10 is a block diagram used to explain an example of an error correction decoder for digital data of one sector, and FIG. Is a block diagram of an encoder in another embodiment of the present invention, and FIG. 12 is a block diagram of a decoder in another embodiment of the present invention. 1 …… Digital Disc, 4 …… Optical Head, 1
5 …… RAM controller, 16 …… RAM, 17 …… Error correction circuit, 19 …… Data conversion circuit, 20 …… Interface, 22
…… Interpolator, 23L, 23R …… D / A converter, 32 …… P decoder, 33 …… Q decoder, 34 …… CRC checker, 42 …… C ₂ encoder, 44 …… C ₁ encoder , 46 …… C ₃ encoder, 52 …… C ₂ decoder, 54
...... C ₁ decoder, 56 …… C ₃ decoder.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Yoichiro Sako 6-735 Kitashinagawa, Shinagawa-ku, Tokyo, Sony Corporation (72) Inventor Constant P.M.J.B. Ain Dhuyen, Gruene Voutsevik 1 (56) Reference JP-A-57-4629 (JP, A) JP-A-57-46308 (JP, A) JP-A-55-45111 (JP, A)

Claims (1)

[Claims] 1. An input digital audio signal is error correction coded for each error correction block to generate a first check word, and the digital audio signal and the first check word are interleaved and then further. In a digital data transmission method of generating a second check word by performing error correction coding and transmitting the digital audio signal and the first and second check words, digital data other than the input digital audio signal Is error-correction-encoded to generate a third checkword, the error-correction block is formed by the digital data and the third checkword, and then the same error-correction encoding as the error-correction encoding for the digital audio signal is performed. Do the above A method for transmitting digital data, comprising transmitting digital data and the first, second and third check words.