JP2784887B2 - Signal selection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention
It relates to a signal selection circuit for outputting. [0002] 2. Description of the Related Art Optical digital audio discs
Character data and tables other than stereo music using the system
Digital data such as display data and programs
If possible, add a display device to
Charts, statistics, and still images
A visual information playback device and a video game device
Digital audio disc system
Can be applied to a wider range of applications. Current so-called con
The data storage capacity of Pact Disk is about 500 Mbytes
Yes, much larger than the storage capacity of the flexible disk
Benefits. In digital audio discs, error
-Correction code processing uses 16 bits of 1 sample data.
Decompose into upper 8 bits and lower 8 bits, and
Is going. That is, interleave and deinterleave
Encoding and decoding of Reed-Solomon code
Are done on a per-unit basis. Therefore, digital audio
Error correction code is commonly used for signals and digital data.
Can be easily done. Digital data is a music signal
Apply interpolation processing such as average value interpolation
Error rate of playback data compared to music signal
Is preferably lower. Record on compact disc
If the signal to be output is audio data (ie, the current
7 and 8 for the data structure of
It will be described with reference to FIG. Fig. 7 recorded on a compact disc
Digital Audio Data Format
It shows. 588 bits of recorded data are stored in one frame.
And a specific bit pattern for each frame.
After the frame synchronization pulse FS, a 3-bit DC component suppression is performed.
Pressure bits RB are provided, and thereafter each of the 14 bits
Data bit DB of the 0th to 32nd bits of the
The flow suppression bits RB are provided alternately. This de
The 0th data bit DB is a subcode
Signal or user's bit
Used to control the playback of information and display related information
It is. 1st to 12th and 17th to 28th data bits DB
Assigned to the main channel audio data
And the remaining 13th to 16th and 29th to 32nd data bits D
B is the parity of the error correction code of the main channel
Assigned to data. Each data bit DB is recorded
8 to 14 bits by 8-14 conversion
It has been converted. FIG. 8 shows each data except for a DC suppression bit.
With the bit DB as 8 bits, 98 frames are arranged in order.
Indicates the state of being arranged in a column. Subcodes for frames 0 and 1
Coding signals P to W are predetermined bit patterns.
Link pattern. Also, the Q channel
As a result, 16 frames on the terminal side of 98 frames
A CRC code for error detection is inserted. [0005] The P channel is a file showing pause and music.
It's a lag, low level in music, high level in poses
In the readout section, a pulse having a cycle of 2 Hz is used.
Therefore, the detection and counting of this P channel
Therefore, it is possible to select and play the specified music
Becomes The Q channel makes the same kind of control more complicated
For example, Q channel information can be played on a disc
Take it into the microcomputer provided in the device,
Do not immediately switch to playing other music even while music is playing.
Any random song selection can be performed. Other R
Channel to W channel are recorded on the disc
Display songwriters, composers, their commentary, poems, etc.
Used to explain by audio. Of the 98 bits of the Q channel,
Are the sync patterns, and the next 4 bins are
Control bits, and the next four bits are
And the subsequent 72 bits are data bits.
Finally, a CRC code for error detection is added.
You. The track number code is included in 72 data bits.
And the index code X. G
Rack number code TNR can vary from 00 to 99
The index code X is also from 00 to 99
It can be converted. [0007] Further, music data is used as data of the Q channel.
Time display code indicating the time of
From the beginning of the disk program area to the outermost end.
Time display code that displays absolute time that changes continuously with
And are included. Each of these time display codes has two digits
Minutes, seconds, and frames. 1 second
Is divided into 75 frames. Digital data
Access the compact disc in units shorter than the music.
The time display code for the absolute time
Is used. In this example, the main channel data and
Sub-coding when recording digital data
Data structure of P channel and Q channel of audio signal
Is the same as a compact disc. FIG. 9 shows a recording format of digital data.
Show The digital data is (588 × 4 bytes =
2352 bytes) as one block (one sector)
FIG. 9 shows the data structure of this one block. 1 bu
Lock is a 12-byte block synchronization signal (CYNC)
, A 4-byte header, and 2048-byte data (user
User data) and a 4-byte error detection code (ED
C), for example, a CRC code and an 8-byte extension
And a 172 byte P code parity (P parity
) And the parity of the 104-byte Q code (Q
Liability). One block of data is
From now on, only the data that is ultimately needed will be cut out.
It is configured to be able to. FIG. 10 shows a configuration of one block (sector).
This is shown in more detail. In FIG. 10, the left channel and the right channel
Channels are the left and right channels of the stereo music data.
This indicates the correspondence with the pull data.
Makes 16 bits one word, L is the least significant bit, M
Indicates the most significant bit. As mentioned earlier, stereo
In the case of music data, it is specified by a frame synchronization signal.
Data of (6 × 2 × 2 = 24 bytes) is recorded in the section.
The same signal format as the stereo music data.
When digital data is recorded using a mat (FIG. 7),
One block (2352 bytes) starts from the 0th frame.
It is recorded up to 97 frames. Therefore,
98 frames of the changing cycle of the
Digital data can be recorded. The first one of the digital data of one block
The bytes are all 0 bits, followed by 10 bytes
Are all 1 bits, and the next 1 byte is all
This bit is set to 0. This 12-byte section is one block.
Block synchronization signal indicating the beginning of digital data
(Sector synchronization signal). After block sync signal
The header of the minute, second, sector and mode of 1 byte
Be added. This header has an address of one block (sector).
Dress, one block is 75
It takes one second for a block. The mode data is
It indicates the type of data of the one block and the like.
In FIG. 10, D0001 to D2336 are block synchronization signals.
Indicates the byte number of one block excluding the number and the header. D0001 to D2048 are user data
And D2049 to D2052 are error detection codes.
Yes, D2053 to D2060 are spaces, and D2
061-D2232 are P parity, and D2233-
D2336 is the Q parity. Error detection code and error correction code
To explain the configuration, the configuration of one block (sector) is
FIG. 11 shows the values expressed in code units. Figure 11
Wi indicates a word number. W0000 and W000
1 is a header, and W0002 to W1025 are users
Data, W1026 and W1027 error detected
W1028 to W1031 are spaces.
W1032 to W1117 are P parity, and W1
118 to W1169 are Q parity. Error detection mark
No. is encoded by header and user data (W0000).
To W1027) and error correction code
The coding of the signal is performed in the range of W0000 to W excluding the block synchronization signal.
About 1170 words (2340 bytes) of 1169
Done. CRC code used as an error detection code
The mode has the following generator polynomial p (x) as an example.
Things. [0016] (Equation 1)   P (x) = (x¹⁶+ X^Fifteen+ X^Two+1) (x¹⁶+ X^Two+ X + 1) The head and user data are stored in GF2⁸upper
Divide the polynomial expression by the above generator polynomial
The remainder at this time is a 4-byte CRC code. this
The error detection code is based on the reproduction signal reproduced from the disc.
Final reliability check after error correction
Used for In addition to this, when performing error correction,
To prevent error correction
good. The error correction code is one block of W000
0 to W1169 words including the most significant bit M
2 for each byte and the lower byte including the least significant bit L
Divide the data group consisting of the upper byte of 1170 bytes.
Data consisting of lane and lower byte of 1170 bytes
This is performed for each data plane with the plane. On this
Data plane of lower byte and data plane of lower byte.
The encoding performed in each of the views is identical. FIG. 12 shows what the upper byte or lower byte is.
Coding for the data plane composed of either one
Are used for the description. The data plane is the header
And 1032 bytes of user data,
The 1032 bytes are a (24 × 43) two-dimensional array.
Is done. As shown in FIG. 12, it is distinguished by a word number
Each byte is arranged from the first line to the 24th line.
It is. For this (24 × 43) data plane, complete
Crossed interleaving and Reed-Solomon codes
The combined error correction code is encoded. This error
-The correction code is a 1032 byte data plane
1 byte each for two code sequences located in different directions
Interleave processing to include symbols
The Reed-Solomon code is encoded for each code sequence.
Is Umono. As shown in FIG.
One byte is one symbol for every 24 bytes to be placed (2
6, 24), the Reed-Solomon code is encoded.
P parity is added as the 2 bytes below the column
You. Therefore, a code sequence including P parity (P sequence and
) Consists of 26 symbols. GF2
⁸As the above (26, 24) Reed-Solomon code,
For example, the following polynomial p (x) is used. [0021] ## EQU2 ## p (x) = x⁸+ X^Four+ X^Three+ X^Two+1 GF2⁸The above primitive element a is (a = 00000
010), the parity matrix HP is
It will be shown. [0023] (Equation 3) Parity symbol P0 = D (43 × 24 +
N) and P1 = D (43 × 25 + N) (N = 0, 1,
2, ‥‥ 41,42) sets the reproduced P sequence to VP.
Satisfies the following equation: [0025] ## EQU4 ## HP × VP = 0 Here, [0027] (Equation 5) Is as follows. For example, (N = 0)
Hour, the first column [D0000, D0043, D
0086, D0129, D0172, $ D0946
D0989, D1032 (= P0), D1075 (= P
1)] is one reproduced P sequence. Further, the data plane is positioned obliquely with respect to the data plane.
One byte is defined as one symbol for every 43 bytes (45,
43) The Reed-Solomon code is coded,
As the two bytes located in the eyes and the 28th row, the Q
Is added. Therefore, the Q sequence has 45 synths.
It consists of a bol. GF2⁸Above (45, 43)
As a Reed-Solomon code, for example, the following polynomial p
(X) is used. GF2⁸The above primitive element a is (a = 00000
010), the parity matrix HP is
It will be shown. [0031] (Equation 6) The parity symbol Q₀= D (43 × 26 +
N) and Q₁= D (44 × 26 + N) is the reproduced Q
When the series is VP, the following equation is satisfied.
You. [0033] ## EQU7 ## HP × VP = 0 Here, [0035] (Equation 8) Is as follows. (N = 0, 1, 2, 3, ‥‥ 2
4,25) and (M = 0,1,2,3, ‥‥ 41,
42). If (44 × M + 43 × N)> 111
When the relationship of 7 occurs, (44 × M + 43 × N) becomes
It is calculated as (44 × M + 43 × N-1118). Easy understanding of interleave relation of Q sequence
(N = 0,1,2, ‥‥ 24,25)
Direction (M = 0,1,2, ‥‥ 41,42) is horizontal
Array of 1118 symbols including P parity as direction
Are rearranged as shown in FIG. Next to FIG.
Each row arranged in the direction forms one Q sequence. For example, (N
= 0), [D0000, D0044, D008
8, D0132, D0176, ‥‥, D0642, D0
686, D0730, D1118 (= Q0), D114
4 (= Q1)] forms one Q code sequence. Also,
In FIG. 13, each row arranged in the vertical direction forms a P series.
I do. Therefore, FIG. 13 shows that (26, 24)
In addition to the encoding of the code-Solomon code,
In addition, the encoding of the (45, 43) Reed-Solomon code is not performed.
1 shows the configuration of one type of product code obtained. The two Reed-Solomon codes are both 2
Error with parity symbol
Correction up to one symbol error is possible even when there is no flag
Function and the error flag
Error is known, errors up to two symbols
Can be corrected. This error flag includes
CIRC standard used for digital discs
(Cross-interleaved Reed-Solomon code) decoding
Fruit can be used. Therefore, in FIG.
Decoding of a vertical Reed-Solomon code (referred to as P decoding)
) And horizontal Reed-Solomon code decoding (Q decoding)
Are performed alternately, for example, (P decoding → Q decoding → P decoding)
Decoding → Q decoding), the P sequence and the Q sequence
In any case, three or more symbols are error-prone.
Correct all error patterns except when
Positive can be done. Naturally, the cross interleave processing
Disperse burst errors
Thereby, the error correction capability can be further improved. The above-described error correction code is stored in one block.
Data and user data totaling 1118 words each
Two data groups that are divided into
The same is done for lanes. This error correction coding
Each of the data planes that have been subjected to the
A sync signal is added, and one block shown in FIG. 10 or FIG.
Configuration. This one block is the audio data
Instead of the data, the CIRC code of the digital disk
Signal, and undergoes error correction coding.
Next, the recording data as shown in FIG.
Is converted to This recorded data is
Supplied to the cutting machine. FIG. 14 shows the structure of an optical disc reproducing apparatus.
It shows the result. In FIG. 14, 1 is the above two
One of the digital signals in the format
1 shows a digital disk recorded in a digital shape. disk
1 is rotated by a spindle motor 2. this
In this case, spin the disc 1 so that it rotates at a constant linear velocity.
The spindle motor 2 is controlled by the spindle servo circuit 3
Is done. Reference numeral 4 denotes an optical head.
The cull head 4 is a laser that generates a laser beam for reading.
Source, beam splitter, optical system such as objective lens,
It has a light receiving element for the laser light reflected by
You. The optical head 4 is connected to the thread feed motor 5
Therefore, the disk 1 can be moved in the radial direction.
ing. The thread feed motor 5 is driven by a thread drive
Driven by road 6. Also, the optical head
The direction of the disk 4 is perpendicular to the signal surface of the disk 1 and
And can be displaced in two directions.
Focusing and tracking of laser light is always good
Is controlled to be For this purpose, focus
A servo circuit 7 and a tracking servo circuit 8
I have. When the reproduced signal from the optical head 4 is RF
To the pump 9. For the optical head 4, for example
Is it a combination of a cylindrical lens and a quadrant detector?
Focus error detector and three laser spots
And a tracking error detection unit using
You. The output signal of the RF amplifier 9 is supplied to the clock extraction circuit 10.
Supplied. The output of this clock extraction circuit 10 (data
And a clock) are supplied to the frame synchronization detection circuit 11.
You. The digital signal recorded on the disc 1 is E
FM modulated. EFM modulation is 8-bit data
Is the preferred 14 bits (ie, the minimum inverse of the modulated signal).
A 14-bit video with a long rotation time and low low-frequency components
This is a method of performing block conversion into a pattern. Digi
The demodulation circuit 12 is configured to perform EFM demodulation.
You. The bit clock extracted by the clock extraction circuit 10
The frame detected by the lock and frame synchronization detection circuit 11
The frame synchronization signal is transmitted to the digital demodulation circuit 12 and the spindle.
It is supplied to the servo circuit 3. In the digital demodulation circuit 12, the sub-code
Of the sub-coding signal.
Is the system controller 1 via the buffer memory 13
4 is supplied. The system controller 14 has a CP
U is provided to rotate the disk 1 and feed the thread.
Operation, reading operation of optical head 4, etc.
The configuration is controlled by the controller 14. Cis
The system controller 14 includes an interface 2 described later.
A control command is supplied via 0. In other words,
Digital signal from disk 1 using the
The system controller controls the signal reading.
14. The menu output from the digital demodulation circuit 12
In-digital data passes through RAM controller 15
It is supplied to the RAM 16 and the error correction circuit 17. this
RAM controller 15, RAM 16, and error correction circuit
The path 17 removes time axis fluctuations and performs error correction processing.
The main digital data is taken out at the output.
It is. The output of the RAM controller 15 is demultiplexed.
The lexer 18 is supplied. The demultiplexer 18
The live disc is compact for stereo music signals
Disk or digital data storage
Is controlled by the data disk.
The output path is switched by the system controller 14. One case
Is recorded on the lead-in track of the disk 1.
Control of the Q channel of the subcoding signal
The disc being played makes stereo music
Identification of signal or digital data storage
Is done. Along with switching this output path, RAM control
Control signal indicating the disc type discrimination result to the
Signal is supplied and the disc for digital data storage is
The raw output undergoes an additional error correction operation. The output selected during digital disk playback
A data conversion circuit 19 is connected to the power system path. This
The data conversion circuit 19 has the
The reproduced subcoding signal is
Playback data is converted to the form of a serial signal.
It is. FIG. 15 shows a system output from the data conversion circuit 19.
4 shows an example of a word format of a real signal. This
The real signal has 32 bits as one word.
Are the preamble, and the next 4 bits are the data complement.
An auxiliary bit and the next 20 bits are data. digital
When the data is 16 bits as one word, the least significant bit
16 bits are inserted from the LSB (LSB). Digital data
4 bits are added after the data. Of these 4 bits
And the bit denoted by V indicates whether the word is valid.
Is a flag indicating whether the sub-code
The bit indicated by C is a channel signal.
Is a bit for identifying a packet, and P is a parity bit.
You. Bit U of this subcoding signal is
One bit is inserted in each format and transmitted sequentially.
It is. The above word format is used for audio
It was considered in consideration of data, and the next interface
Standard 20 computer data
Converted to format. Also, system control
Data for the device 14 via the interface 20
Microcomputer system (host computer)
21. Microcomputer system 2
1 designates a read address, and the read address
In addition, a drive control signal such as a start signal
Interface 20 and system controller 14
Get The disc being played is a stereo music signal.
Output of the demultiplexer 18 selected at the time of
An interpolation circuit 22 is connected to the system, and error correction is not performed.
Error data is corrected. To the interpolation circuit 22
Is divided into left and right channels.
Data is analog by D / A converters 23L and 23R
And passed through low-pass filters 24L and 24R, respectively.
Are taken out to the output terminals 25L and 25R. Here, the buffer memory 13
The time axis fluctuation of the coding signal is removed. this
Time axis correction is applied to the main channel digital signal.
And the RAM controller 15 and the RAM 16
It is similar to what is done. In other words, RAM controller
The roller 15 reproduces the reproduced signal from the detected frame synchronization signal.
The write clock is synchronized with the
Write a digital signal to the RAM 16 by the
When reading digital signals from RAM 16,
Use a read clock generated from the output of the shaker
I have to. This write clock and read clock are
Writing of sub-coding signal to buffer memory 13
And for reading. Therefore, the buffer memory
13, the sub-coding signal read from
With the main channel digital signal
The interrelationship changes due to this time axis fluctuation
Is prevented. Here, the digital data storage digital
When playing a disc, first, the microcomputer system
At 21, a read instruction for a predetermined address is executed.
Is performed. This address is the absolute time table for the Q channel.
The code itself for the presentation, the interface 20
The address is supplied to the system controller 14 via
Is done. The system controller 14 is
Control circuit 6 to reproduce the data by the optical head 4.
While reading the sub-coding signal
Move the optical head 4 to a position near the
You. Error in sub-coded signal reproduced in this example
Is included by setting the sub-coding
Malfunction that the access operation does not end without the signal being reproduced
Playback from a position a few blocks away to prevent
To start. Then, the reproduced sub-code
The matching signal matches the specified address.
Or from the position of the correct subcoding signal in the vicinity
Starting playback and counting the frame sync signal
Try to grab the target block in any way
ing. FIG. 16 shows a digital data storage directory.
1 shows an example of an error correction circuit (decoder) at the time of disc playback.
In FIG. 16, for simplicity, a disk for an audio signal is shown.
And digital data storage disks
Have been. The CIRC code decoder is omitted.
ing. In other words, one block stored in the RAM 16
The playback data except for the block synchronization signal of the
After decoding the signal, each symbol has an error.
An error flag indicating nothing is added. From the RAM 16 together with the error flag,
VOL is read out, and the data
The signal is supplied to the P decoder 32 via the source 31. P decoder 3
2, the error obtained by decoding the CIRC code
Correction of 2-symbol error in one P-sequence using flag
Correct (26, 24) decoding of Reed-Solomon code
The decoded symbol is written to the RAM 16.
You. In this case, the error is corrected by the P decoder 32.
Error flag for that symbol is cleared
Is done. When P decoding for one block is completed, RA
Data read from M16 is transmitted via data bus 31
It is supplied to the Q decoder 33. By controlling the address of the RAM 16, the
Interleaving is performed, and Q recovery is performed for each Q sequence of one block.
In the encoder 33, two symbol errors in one Q sequence
Of the (45, 43) Reed-Solomon code
Is made. The error corrected by this decoding
Will clear the error flag for that symbol
You. Next, P decoding is performed again, and Q decoding is further performed.
You. Thus, P decoding and Q decoding are alternately performed twice each.
After the error correction,
Data is supplied to the CRC checker 34, and error detection is performed.
And an error detection result is supplied to the output gate 35.
It is. The output gate 35 determines that there is an error.
An error flag is set for the data. The error detection result of the CRC checker 34 is as follows.
Error correction in the P decoder 32 and the Q decoder 33
It can also be used for P decoder 32 and Q decoder 3
In No. 3, the error occurs when decoding the CIRC code during error correction.
The generated error flag is used. Therefore, the CRC
The error detection result of the checker 34 is used for P decoding and Q decoding.
By reference, the error flag of the CIRC code is
It can prevent erroneous correction operation when incorrect.
You. [0054] SUMMARY OF THE INVENTION The present invention relates to the above-described optical system.
Suitable for application to electronic devices such as playback devices of the type disk,
In the signal selection circuit, prioritize multiple signals
It is intended to propose something that can be taken out
is there. [0055] According to the present invention, there is provided a signal selection circuit according to the present invention.
The path has N gates to which a plurality of (N) signals are respectively supplied.
Circuit and all or part of its N gate circuits
To supply gate pulses sequentially and cyclically
Therefore, all or some of the N gate circuits are cyclically
Open and the signal from the open gate circuit
Control sequence to stop counting when output
Gate and gate counter according to the input processing mode.
Is supplied to all or some of the N gate circuits.
Control the counting operation of the control sequence counter
And control means. [0056] According to the present invention, a control sequence counter is provided.
All or one of the N gate circuits
Supply the gate pulses sequentially and cyclically to the
Cycle all or part of the N gate circuits
As well as signals from gate circuits in the open state.
When the signal is being output, the counting operation is stopped. Control hand
Depending on the processing mode, the gate
Is supplied to all or some of the N gate circuits
Thus, the counting operation of the control sequence counter is controlled. [0057] DESCRIPTION OF THE PREFERRED EMBODIMENTS In this embodiment, the present invention is applied to the reproduction of an optical disc.
When applied to a device, the configuration of the playback device, its operation, etc.
For the most part, refer to FIGS.
Here, only the characteristic portions of this embodiment will be described.
In FIGS. 1 to 4, FIG. 14 and FIG.
Corresponding parts will be described with the same reference numerals. [0058] [Peripheral Circuit 1] (FIG. 2) Hereinafter, referring to FIG.
In FIG. 14, the RAM controller 15
-Describes the circuit provided in the part leading to the face 20
I will tell. 40 is a data selector, a RAM controller
15 to the input terminal 41.
Signal and various signals attached to it and supplied to the input terminal 42
Second digital signal and various signals accompanying it
And the third digital signal supplied to the input terminal 43
And one of the various signals attached to it,
The selected signal is synchronized through the demultiplexer 18.
Route 45. The first to third digital signals are
The number of bytes per mode is 3 bytes, 4 bytes and 2 bytes respectively
The content of the first digital signal is a byte signal, as described above.
FIGS. 9 to 11 show signals detailed in FIGS.
The digital signal is obtained by converting the first digital signal into a serial signal.
This is the signal transmitted and received. Third digital
The signal is a commonly used general-purpose signal. This synchronizing circuit (comprising a one-chip IC)
In (45), the following processing is performed. First to third
Of digital signals selected from
Applicable input bit clock and common word clock
From the same number of bit clocks in one word period
Output bit clock and output bit clock.
Clock and a common word clock to a common output byte clock.
Get a lock. External block detected from digital signal
Create an internal block synchronization signal synchronized with the synchronization signal. First to third digital signals (serial signals)
The digit order of the bit signal of each word (the first bit of each word)
Is the LSB or the MSB?). The descrambling of the digital signal is performed. Detection and Error of Digital Signal Error
The state is determined. Reference numeral 47 denotes a buffer RAM, which stores digital data.
Data and error flags for each byte.
This is for correcting data errors. A RAM controller 46 controls the RAM 47.
Roller. The RAM controller 46 has a synchronous circuit
Descrambled output data from path 45, bytes
Error flag, output bit clock, output byte clock
Receives lock, internal block synchronization signal, etc. RAM control
The controller 46 is a CPU of the system controller 14.
Error correction of data stored in RAM 47 by control
The data read from the RAM 47
Microcomputer system via face 20
(Host computer) 21. The error state (data error)
Error signal, error over, etc.)
Through the interface 48 to the system controller 14.
Be paid. [0067] [Peripheral circuit 2] (FIG. 3) Next, the RAM controller in FIG.
The details of the trawler 46 will be described with reference to FIG.
You. Reference numeral 80 denotes a write / read control circuit;
This is a dress / data switching circuit. The synchronization circuit 45 of FIG.
The serial data obtained from the descrambling circuit is
The data is supplied to the column conversion circuit 84 and converted into parallel data.
Thereafter, the data in the buffer RAM 47 is transmitted via the switching circuit 81.
RAM (for example, three RAMs of 2048 x 8 bits)
To be written to 47a)
Have been. Further, the data from the synchronization circuit 45 in FIG.
The error flag for each byte is stored in the RAM via the switching circuit 81.
47 error flag RAMs (8192 × 1 bit R
(Using AM) 47b. Reference numerals 82 and 83 denote addresses for writing data, respectively.
The generation circuit and data read address generation circuit
The dress signal is supplied to the RAM 47 via the switching circuit 81.
It is. The above-mentioned write / read control circuit 80
Based on the input control signal from the stem controller 14
Outputs an output control signal to read / write RAM 47
And the switching of the switching circuit 81 is controlled. CPU 14 of system controller 14
And P / Q parity address conversion ROM 85, error
The correction RAM 86 and the system ROM 87 are connected via a bus.
Connected to each other. ROM 85 and RAM 86
The switching circuit 81 is connected. An error occurs in the data written in the RAM 47a.
And the error flag for each byte is stored in the RAM 47b.
If the data with the error is written to
Read from RAM 47a to error correction RAM 86
After being written and error-corrected there, it is stored in the RAM 47a.
Written again. Then store it from RAM 47a
The read data is read out, and the switching circuit 81-interface is read.
Microcomputer system through the interface 20
(Host computer) 21 to receive data.
Is performed. [0073] [Signal Selection Circuit] (FIGS. 1 and 4)
The signal selection circuit provided in the read control circuit 80
Therefore, a detailed description will be given with reference to FIG. It should be noted that FIG.
3 shows waveforms of signals of respective parts of the signal selection circuit No. 1. The buffer RAM 47 shown in FIGS. 2 and 3
To the microcomputer system (host
Computer) 21 based on the data fetch request.
The modes for writing and reading data are defined as follows. The data from the synchronization circuit 45 is stored in a RAM controller.
The mode for writing to the RAM 47 via the roller 46 is the first mode.
And the sign of the signal associated with it is:
W at least in part₁Is used. The data read from the error correction RAM 86
The mode for writing data to the RAM 47 is changed to the second write mode.
And the sign of the signal associated with it
Part of the W_TwoIs used. Data is read from RAM 47 and
Controller 46-via the interface 20
Computer system (host computer) 21
The mode supplied to the first read mode is referred to as a first read mode.
The sign of the connected signal has at least a part of R₁For
I have. Data is read from RAM 47 and an error
The second read mode is a mode in which the data is supplied to the correction RAM 86 and written.
Mode, and the sign of the associated signal is at least
Also part of it is R_TwoIs used. RAM 47 corrects the error of the data.
To be controlled by the CPU 88 of the system controller 14.
Is accessed (CT of the CPU switching signal in FIG. 4A).
L mode), the first write mode and the second read
Cycle of write mode and second write mode is repeated
Then, the data is written to the RAM 47a and the RAM 4
Of the data written in the RAM 7a using the RAM 86.
-Corrections are alternated. The RAM 47 is a microcomputer system.
System (host computer) 21
(The HOST mode of the CPU switching signal in FIG. 4A)
) Is a sequential first write mode and first read mode.
The data cycle is repeated and the data stored in RAM 47a is read.
Data writing and data stored in the RAM 47a.
Microcomputer system (host computer)
21 are alternately performed. In FIG. 1, 92a to 92d are first to first
4 registers (shift registers), 93a to 93d
It is a data selector attached to each register. 94 is
Pulse-forming circuit comprising two-stage D-type flip-flop circuit
It is. Each other from the system controller 14
Asynchronous first and second write control input signals W
₁, W_Two{Refer to FIG. 4D (V), I respectively.
Second read control input signal R₁, R_Two(FIGS. 4R, N
) Is supplied to the pulse conversion circuit 94, and corresponding to each
Obtained clear pulse CW₁, CW_TwoAnd CR₁, CR
_Two{See Figures 4E (W), J, R, O, respectively}
To be supplied to the clear terminals of the terminals 92a to 92d.
Have been. Each output Q of the registers 92a to 92d_Four｛Figure
4F (X), K, T, and P} are gate circuits (E
(A circuit) 90a to 90d. 91 is 2^TwoSequence counter for hexadecimal control
And is driven by a master clock (see FIG. 4B),
From the counter 91 to the front of the gate circuits 90a to 90d or
A gate pulse is sequentially and cyclically supplied to a part thereof. CPU off from system controller 14
When the switching signal (see FIG. 4A) is in the CTL mode,
Under the control of the path 96, the counter 91 becomes a ternary counter.
The gate circuits 90a, 90b operate as shown in FIG.
And 90d are sequentially supplied with a negative pulse in a cyclic
It is. CPU off from system controller 14
When the switching signal (see FIG. 4A) is in the HOST mode,
Under the control of the circuit 96, the counter 91 becomes a binary counter.
4C, the gate circuits 90a and 90a as shown in FIG.
Negative pulses are alternately supplied to 0c and the pulse is released. Each output of the gate circuits 90a to 90d is
It is supplied to a NAND circuit 95a of the logical circuit 95. In addition, cash register
Each output Q of the star 92a-92d_FourIs the logic circuit 95
The output of the NAND circuit 95b is supplied to the NAND circuit 95b.
Supplied to Then, the output of the NAND circuit 95a is synchronized.
The circuit 96 is supplied to the circuit 96 to control the gate circuits 90a to 90d.
When the output (low level) is obtained from the deviation
If the output (low level) is not obtained from the deviation,
The counter is operated so that the counting operation of the counter 91 is stopped.
The counter 91 is controlled. At this time, each of the counters 91
Both outputs of the NAND circuit become high level (see FIG. 4C).
See). The outputs of the gate circuits 90a to 90d are respectively
The latch output is supplied to the latch circuit 97, and each latch output is
First and second write control output signals W₁(C), W
_Two(C) and the first and second read control output signals R₁
(C), R_Two(C) {See FIG. 4G (Y), L, U, Q}
And supplied to the switching circuits 82 and 83 of FIG. 3, respectively.
Switching of the address signal supplied to the RAM 47 is controlled.
You. The output Q of the register 92a is₁, Q_Four(Anti
) Is the write enable signal W₁(E)
{See FIG. 4H (Z)} and supplied to the RAM 47.
You. Output Q of register 92b_Two, Q_Four(Reverse) Nand
Is the write enable signal W_Two(E) (see FIG. 4M).
And supplied to the RAM 47. The output Q of the registers 92c and 92d is_FourIs
The first and second read latch signals R respectively₁(L), R_Two
(L), each of the latches incorporated in the switching circuit 81 of FIG.
Data supplied to the switch circuit and read from the RAM 47.
Are latched respectively. First and second wait (wait) signals WT
₁, WT_Two(Low level) (see Fig. 4Ω)
Mode and HOST mode. The master clock is a counter 91,
Registers 92a to 92d, pulsing circuit 94, and latch
It is also supplied to the circuit 97. Next, the registers 92a to 92d and the data cells
Of the collectors 93a to 93d and the gate circuits 90a to 90d.
Since the relationship and operation are the same,
92a, data selector 93a and gate circuit 90a
This will be described using an example. As shown in FIG.
Output Q of the terminal 92a_FourIs high, the counter 91
Output (see FIG. 4C) is high level or low level.
The output of the gate circuit 90a is low level and high level, respectively.
Becomes The output of the gate circuit 90a is the data selector 93.
a to the select terminal, and a high-level output
Signal B₁~ B_FourIs output Y₁~ Y_FourAnd
Input D of shift register 92a₁~ D_FourAnd low level
Signal A when the output of₁~ A_FourIs the output signal
Y₁~ Y_FourAnd the input D of the shift register 92a₁
~ D_FourIt is said. Also, the output Q of the shift register 92a₁
Is the signal B of the data selector 93a.₁, A_TwoAnd output
Q_TwoIs signal B_Two, A_ThreeOutput Q_ThreeIs signal B_Three, A
_FourOutput Q_FourIs signal B_FourIt is said. Also, signal A₁
Is always at a high level. Now, the output Q of the register 92a_FourBut high level
Output Q₁~ Q_ThreeIs also at a high level,
The output of the gate circuit 90a changes between a high level and a low level.
Is the output Q of the register 92a.₁~ Q_FourRemains at a high level
It is. Therefore, the input signal W₁(Low level)
4D (V) reference}, from the pulsing circuit 94,
Clear pulse CW to register 92a₁(Low level)
4E (W) is supplied, each output Q₁~ Q
_FourAre both low levels. Output Q of register 92a_FourBut
When the level is low {see Fig. 4F (X)}
When the output of the counter 91 (see FIG. 4C) is at a high level,
In this case, the output of the gate circuit 90a goes high,
Output Q of register 92a₁~ Q_FourAre both low level
Up to. Output Q of register 92a_FourIs low level
The output of the counter 91 is low.
At the beginning, the data selector 93a
Force Y₁Is the signal A₁(High level), this is the register
Input D of 92a₁Therefore, the master clock
Therefore, the output Q of the register 92a₁~ Q_FourIs sequentially high level
Becomes [0096] [Another Example of Signal Selection Circuit] (FIGS. 5 and 6) Next, referring to FIG.
In the following, another example of the signal selection circuit will be described. 150 is above
The entire signal selection circuit described with reference to FIG.
Shown as the alternative circuit body. In FIG.
The signal to be input is the input signal W₁, W_Two, R '₁(Described later), R_Two
Only signals are shown, and other signals are not shown. Reference numeral 151 denotes an input signal R of the main body 150.₁Input
The logic circuit added to the side is shown. Read to logic circuit 151
Pulse and CPU switching signal are supplied, and
The new output signal is input to a new first read control input signal R '.₁
To the main body 150. The logic circuit 151 is controlled.
Control signal M, for example, when the control signal M is at a high level.
Is in wait mode, the input signal R '₁Figure 6C
Input signal R₁And the control signal M is low.
When in the data request mode, the input signal R '₁Is in
Force signal R₁6K input signal (data request
Signal) R '₁Becomes The logic circuit 151 includes, for example, a read pulse
And an OR circuit 152 to which the CPU switching signal is supplied.
The output of the circuit 152 and the inverted signal of the control signal M are supplied.
Exclusive OR circuit 153 and exclusive OR circuit 1
NOR circuit 1 to which the output of CPU 53 and the CPU switching signal are supplied
54. Next, the operation of the signal selection circuit of FIG.
Let's explain with reference to the time chart. 6A to 6H show R
Access to the AM is controlled by the host computer.
Each signal in the eight mode is shown, and RA shown in FIGS.
Access to M is RAM controller-driven data
Respectively in the request mode. However,
FIG. 6C shows the first read control input signal R₁And FIG. 6K
Is the first read control input signal R '₁It is. FIGS. 6A and 6B show the CPU control of the embodiment of FIG.
Control signal and has CTL mode and HOST mode
You. The input signal R of FIG. 6C₁Is a read pal of FIG.
The phase is inverted. Input signal R₁(FIG. 6C)
On the rising edge, the first
In a read mode of the read mode. In addition,
Force signal R '₁The same applies to this. The read pulse shown in FIG.
Changes the address of the address counter at the falling edge of
Starts reading data to the host computer
U. In contrast, the read pulse of FIG.
Read data to the host computer at the fall
Change the address of the address counter at the rise
You. FIGS. 6D and 6L show the data read address of FIG.
Address generation circuit 83 in the first read mode.
Output (carry output, indicating the end of reading)
Indicates CO (high level). FIGS. 6E and 6M show the control signals of the address counter.
Signal, high level is in countable mode, low level is initial
Indicates the value loadable mode. Note that the counter output CO
Before being input (the state shown by the broken line), the CPU switching signal
When switching from T mode to CTL mode,
At this point, the counter control signal becomes high as indicated by the broken line.
Change from level to low level. FIGS. 6F and 6N show signals supplied to the address counter.
Indicates a load pulse (low level). FIGS. 6G and O show the read wait signal.
And this is the input signal R₁, R '₁High edge at the rising edge of
This signal changes from a bell to a low level.
It changes with time, and the high level part is the RAM 47a.
This is the period during which the data read from the latch can be latched. FIGS. 6H and P show the latched data.
And consists of parallel 8-bit data. Now, the input signal R 'in FIG.₁Figure 6J
CPU switching signal in response to the read pulse (see FIG. 6I)
(Rising edge portion) is inverted and added, that is, CP
Switching of U switching signal from CTL mode to HOST mode
At this point, and use this rising edge to
Together with the read command timing. Wait Mode (General for reading solid-state memory)
Mode), the host computer 21
From the system controller 14 based on the read command
Input signal based on a read pulse (FIG. 4B) generated from the
R₁Read data to RAM 47a at the rise of (FIG. 6C)
And the read wait signal (Fig. 6G) is low level.
The data is read out after the signal goes to a high level. In contrast, the data request mode (file
Mode commonly used for reading a floppy disk)
Is the input signal R '₁After the rise of the RAM controller 4
6 monitors the read wait signal (FIG. 6O).
After the signal of the RAM 4 goes from low level to high level, the RAM 4
Data reading is performed at an arbitrary timing from 7a.
You. [0110] According to the present invention described above, a plurality (N)
N gate circuits to which signals are respectively supplied, and the N gate circuits
And circulation for all or some of the gate circuits
N gates by supplying gate pulses
Open all or part of the circuit cyclically and
When a signal is output from the gate circuit in the released state
Is a control sequence counter that stops the counting operation, and
Gate pulse is N gates according to the processing mode set.
Control sequence to be supplied to all or part of the circuit
Control means for controlling the counting operation of the sense counter.
So take out multiple signals with fair priorities
And no signal is output among the N gates.
Gate circuit is skipped and opened cyclically,
Obtain a signal selection circuit that can increase processing efficiency.
Can be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a signal selection circuit according to the present invention; FIG. 2 is a block diagram showing peripheral circuits of the signal selection circuit; FIG. FIG. 4 is a time chart of signals of the signal selection circuit. FIG. 5 is a block diagram showing another embodiment of the signal selection circuit according to the present invention. FIG. 6 is a block diagram of the signal selection circuit. Signal time chart [Fig. 7] Digital audio data format diagram [Fig. 8] Digital audio data format diagram [Fig. 9] Digital data format diagram [Fig. 10] Digital data format diagram [Fig. 11] Digital data format FIG. 12 is an explanatory diagram of an interleave relationship of an error correction code. FIG. 13 is an explanatory diagram of an interleave relationship of an error correction code. 14 is a block diagram of a conventional reproducing apparatus. FIG. 15 is a format diagram of digital data. FIG. 16 is a block diagram showing a part of an error correction decoder of the conventional reproducing apparatus. Gate circuit 91 Control sequence counters 92a to 92d Shift registers 93a to 93d Data selector 95 Logic circuit 96 Synchronous circuit

Claims (1)

(57) [Claims] N gate circuits to which a plurality of (N) signals are respectively supplied, and a gate pulse that is sequentially and cyclically supplied to all or some of the N gate circuits.
All or some of the gate circuits are cyclically opened, and a control sequence counter that stops the counting operation when a signal is output from the gate circuit in the open state; Control means for controlling the counting operation of the control sequence counter so that the gate pulse is supplied to all or some of the N gate circuits in response.