JP3282425B2 - Digital signal recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording apparatus for recording digital signals, and more particularly to a recording apparatus suitable for recording digital compressed video signals transmitted in packet units.

[0002]

2. Description of the Related Art A digital signal recording apparatus for recording a digital compressed video signal on a magnetic tape by using a rotary head is described in Japanese Patent Application Laid-Open No. 5-174496. Using this device, the transmission system shown in FIG. 17, received by the receiver 161, the compressed digital video signal in packet units from the transmitter 160 records, it is possible to reproduce.

In FIG . 17 , reference numeral 160 denotes a transmitter;
Is a receiver, 162 is a recording device, 163 is a video output terminal,
164 is a compression circuit, 165 is an encoding circuit, 166 is a modulation circuit, 167 is a demodulation circuit, 168 is an error detection circuit, 16
9 is a switch, 170 is a decompression circuit, and 175 is an information source. In this system, digital information stored in the information source 175 of the transmitter 160 is subjected to digital compression using a compression circuit 164, and an error is detected by an encoding circuit 165.
A parity for correction is added, modulation is performed by a modulation circuit 166, and the data is transmitted. In the receiver 161, the demodulation circuit 167
The demodulation unit demodulates the received signal, and the error detection circuit 168 detects and corrects the error. When recording on the recording device 162,
An error detected and corrected signal is sent to the signal line 172 to perform recording. To directly view the received video, switch 16
9 is output from the error detection circuit 168 to the recording device 16.
In order to view the video recorded on the recording device 2, the switch 169 selects the output 173 of the recording device, and sends each signal to the decompression circuit 170. In the decompression circuit 170, the compression circuit 164
Is returned to the original video signal and output from the video output terminal 163. Note that the compression circuit 164 is indicated by a dotted line since the signal stored in the information source 175 becomes unnecessary when the signal is compressed in advance.

[0004]

In general, the transmitter 160
Since there are a plurality of receivers 161 connected to, when transmitting a signal, an identification code for a specific receiver, time information and the like are added, and the signals are output in bursts at arbitrary time intervals in packet units. Therefore, the number of packets transmitted per unit time is variable.

[0005] The transmission digital compressed signal may have a transmission error due to noise or the like at the time of transmission. Therefore, an error correction code for error detection and correction is generally added by an encoding circuit 165. . Receiver 1
When it is determined that the error cannot be corrected by the error detection and detection circuit 61, the signal of the packet is stopped to be output to the signal line 172 and the signal may not be output. May further change. In this case, with respect to the packet whose output has been stopped, it is possible to detect that the packet is missing from the time information added to the preceding and succeeding packets.

In the above-mentioned conventional apparatus, no consideration is given to the case where the number of packets to be recorded per unit time is variable. Therefore, if m packets are input in the k-th unit time, n (n <n <
When m) packets are input, in the (k + 1) -th unit time, the k-th packet is recorded as it is for mn packets.

It is also conceivable that the result of detection by the error detection circuit 168 is output to the recording device 162 as a flag as shown by a signal line 174. Further, as shown in FIG. 17, as a countermeasure against transmission errors between the receiver 161 and the recording device 162, an encoding circuit 180 is provided and a signal line 181 is provided.
It is also conceivable that a new parity is added to the signal output to.

In the above-mentioned conventional apparatus, no consideration is given to correspondence to these flags, parity, and the like.

An object of the present invention is to provide a digital signal recording apparatus capable of coping with a case where the number of packets to be recorded per unit is variable and a case where a flag indicating an error condition during transmission is added and transmitted. To provide.

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital signal recording apparatus for recording a digital compressed video signal in a unit of n packets at a specific period, wherein m (m.ltoreq.n) Input means for inputting a digital signal in units, packet information generating means for generating the packet information, and storage means for temporarily storing the digital signal input by the input means and the packet information generated by the packet generating means And the packet information is replaced or added to a part of the digital signal, or the packet information is replaced or added.
This can be attained by providing recording means for recording the obtained packets as digital signals in units of n packets on the recording medium.

[0011] In addition, at least the m number of the storage means
Reset the above packet information indicating that the packet is
Reset means, or the above
Reset the packet information stored in the storage means.
A setting means may be provided.

[0012] indicates the specific period in the m to (m is a natural number, a variable number of m ≦ n) type packets, the input termination part of the m-th or m + 1 th of the digital signal of the packet Recording means may be provided for recording on the recording medium in place of the end signal or for adding the end signal to the digital signal and recording on the recording medium.

[0013]

The packet information generated by the packet generating means is
Since it is recorded on the recording medium together with the input packet,
At the time of birth, it is reproduced by detecting this packet information.
Packet is m valid packets or other than m
It is possible to determine whether the packet is invalid.

Further, at least the m number of the storage means
Reset the above packet information indicating that the packet is
Reset means to reset the part of the
Packet information remains reset and entered
The packet information of the part is
Since the generated packet information is written,
Valid packets and invalid packets can be identified.
Become. In addition, it is stored in the storage unit for each specific cycle.
Comprising reset means for resetting the packet information
This makes it easy to perform the above reset operation regularly.
Becomes possible.

[0015] Further, recording the end signal on a recording medium.
This makes it possible to easily detect the end of a valid packet during reproduction .

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a digital signal recording apparatus according to a first embodiment using the present invention. This apparatus is the recording apparatus 1 shown in FIGS.
62. In FIG. 1, 1 is a signal input terminal, 2 is an input processing circuit, 3 is a selection circuit, 4 is a storage circuit, 5 is a recording processing circuit, 6 is a recording amplifier, 7 is a rotary head, 8 is a magnetic tape, and 9 is a control. An information addition circuit, 10 is an address control circuit, 11 is an ID generation circuit, 12 is a servo circuit, 13 is a timing generation circuit, and 17 is a reset circuit.

FIG. 2 shows a recording pattern of a signal recorded on the magnetic tape 8, reference numeral 23 denotes an additional information recording area for audio signals and the like, reference numeral 27 denotes a data recording area for recording a digital compressed video signal, and reference numeral 31 denotes time information. , Subcode recording areas for recording subcodes such as program information, 22, 26,
Reference numeral 30 denotes a preamble of each recording area, 24, 2
8, 32 are postambles of respective recording areas, 2
5, 29 are gaps between the respective regions, 21, 33
Is the margin at the track end. As described above, by providing a preamble, a postamble, and a gap in each region, it is possible to perform dubbing on each region independently. Of course, signals other than the audio signal and the digital compressed video signal may be recorded in the additional information recording area 23 and the data recording area 27.

FIG. 3 shows a block structure of a signal recorded in the data recording area. One block includes a synchronization signal (2 bytes) indicating the head of the block, and I indicating a packet structure and the like.
D4 (4 bytes), data 19 consisting of 195 bytes
It consists of 5 and 9 bytes of parity for error correction. FIG. 4 shows the structure of the ID 41, in which a 2-bit area code 44 and a 6-bit track address 4
5, 8-bit frame address 46, 8-bit ID
Data 47 is composed of parity of 8 bits for error detection.

First, the operation of the apparatus shown in FIG. 1 will be described.

A digital compressed video signal having a packet structure, which will be described later, is input from the signal input terminal 1 from the receiving device 161 shown in FIG. 17 , and the input processing circuit 2 determines the packet structure and the like. The data is stored in the storage circuit 4 via the memory. At this time, the input digital compressed video signal is transmitted in packet units, but the number of packets transmitted per unit time is not constant but variable. Therefore, the number of packets transmitted per unit time (in this apparatus, the time during which the rotary head rotates 180 °; called one track) is recorded in the ID data 47, and an unnecessary signal is output during reproduction. It is possible to control so that it is not performed. The input processing circuit 2 counts the number of packets transmitted in one track and sends it to the ID generation circuit 11. The signal stored in the storage circuit 4 is added with the parity 43 by the recording processing circuit 5, is further added with the ID 41 and the synchronization signal 40 generated by the ID generation circuit 11, and is subjected to modulation processing. Is recorded on the magnetic tape 8 by the rotary head 7 via the.

As described above, although the number of input packets per track is variable, the number of packets is recorded in the ID data 47, but the number of packets is recorded in the ID data 47. There is a possibility that the number of packets to be erroneously detected and output is erroneously detected. At the time of recording, the storage circuit 4
When the number of input packets is smaller than that of the previous track, the signal input to the previous track remains as it is and is recorded on the magnetic tape 8. Occurs, the signal of the previous track is output. Therefore, in the present apparatus, by recording a packet flag indicating that each packet has been input, the validity of each packet can be determined at the time of reproduction. This packet flag will be described.

FIGS. 5 to 8A show the packet structure of the digital compressed video signal output from the receiving device 161. FIG. This device is capable of recording digital compressed video signals having various types of packet structures.

In the packet structure of FIG. 5, each packet consists of 195 bytes, and the first three bytes are control information 50 indicating data contents, recording time, copy control information, and the like. In this case, since the number of bytes of one packet is equal to the number of data per block shown in FIG. 3, 195-byte data including the 3-byte control information 50 is recorded as one block. However, since there is an unused area in the control information 50, the packet flag described above is written here. As a result, as shown in FIG. 5B, the first three bytes of the data 42 in FIG. 3 are recorded as control information 250 including a packet flag.

FIG. 9 shows the recording timing. The track identification signal 100 indicates the time during which the rotary head 7 makes one rotation in one cycle, is generated by the timing generation circuit 13, and the number of rotations of the rotary head 7 is controlled by the servo circuit 12. The figure shows the operation when three packets are input in the track section 1, 7 packets in the track section 2, 2 packets in the track section 3, and 4 packets in the track section 4. The storage circuit 4 has two banks, and alternately performs writing of an input signal via the selection circuit 3 and reading to the recording processing circuit 5 for each track. In FIG. 9, RAM-A and RAM-B each have 1
Track sections 1 and 3 and RAM-
A is written, RAM-B is read, and in track sections 2 and 4, RAM-A is read and RAM-B is written.

The packet counter 101 of the input processing circuit 2
(Cleared to 0 at the beginning of each track) to count the number of input packets. Each time a packet is input, a write packet flag 103 is generated by the input processing circuit 2 and added to the control information 50 by the control information adding circuit 9 to obtain control information 250. At the timing when the control information 50 is stored in the storage circuit 4, the selection circuit 3 selects the control information addition circuit 9 so that the control information 250 is stored in place of the control information 50. All the packet flags are cleared by the reset circuit 17 for each track, so that the packet flags are added only to newly input new packets. In the next track section, reading to the recording processing circuit 5 is performed. However, in the case of reading more than the number of input packets, since the packet flag is not added, the data is stored before the previous track. It is possible to distinguish old packets from new packets. Thereafter, the data is recorded on the magnetic tape 8 through the same processing as the other data. The packet flag may be reset by clearing the portion related to the packet flag of the control information 250 immediately after reading each packet as shown at 105 in FIG. 9 or at the end of each track as shown at 106. A clear section may be provided to reset the packet flags for all packets. At the time of reproduction, by detecting the control information 250 for each packet, a packet to be output and a packet not to be output can be completely identified. Furthermore, as shown in FIG. 5B, since the control information 250 can detect and correct errors by the parity 43 and the like, the reliability is significantly improved as compared with the judgment based on the number of valid packets of the ID 41 alone. .

FIG. 6 shows a case where the control information 50 is 4 bytes, the time information 3 indicating the time of transmission is 3 bytes, and the packet data is 188 bytes, that is, 195 bytes in total. Also in this case, since the number of packet bytes matches the number of block bytes, 1 packet = 1
Record as a block. Also, by writing the packet flag in the control information 251, the same processing as in the case of FIG. 5 may be performed.

FIG. 7 shows time information 52 of 3 bytes, control information 78 of 1 byte, and packet data 79 of 140 bytes.
This shows a case where one packet is composed of a total of 144 bytes.
In this case, since the number of packet bytes differs from the number of block bytes, four packets are recorded over three blocks as shown in FIG. At that time, 3-byte control information 50 is placed at the head of the data of each block, as in FIG. 5, and 144-byte data is arranged in the remaining 192-byte area. The packet flag contains control information 70, 7
One flag is assigned to each packet by writing to 1, 72 and 73. The timing generation circuit 13 determines the write timing of each control information in the first block, the second block, and the third block, and controls the selection circuit 3 to write the packet flag into the storage circuit 4.

FIG. 8 shows frame information 80 and 4 of 4 bits.
A case where one packet is constituted by a total of 78 bytes of the track information 81 of bits and the packet data 82 of 77 bytes is shown. In this case, five packets are recorded over two blocks. At this time, the control information 50 for each block is not recorded, and the data of 78 bytes are arranged in two blocks in order.
The control information 83 to 87 in FIG.
Since the frame information 80 and the track information 81 in FIG. 9A are used, a packet flag cannot be added. Therefore, in the flag reset 105 or 106 in FIG. 9, the control information 83 to 87 and the like are written to specific values that cannot actually exist using the reset circuit 17. In the packet flag writing, the input signal is stored in the storage circuit 4 as it is. As a result, the frame information 80 and the track information 81 for the old packet are recorded on the magnetic tape 8 as specific values.
By detecting the first abnormality, a valid packet and an invalid packet can be distinguished.

As described above, for each packet,
By recording a flag for identifying a newly input packet or an old packet input before, reliability can be improved as compared with the case where only the ID 41 indicating the number of input packets is used. Since this flag needs to be added to each packet, if the ID 41 added to one block is used, a signal having the packet structure shown in FIGS. 7 and 8 is recorded. At times, it cannot be used, so control information must be used as in the present invention.

It is also conceivable to multiplex-write an already-input packet in a recording area of a packet not to be input without using a packet flag. Hereinafter, this method will be described as a second embodiment.

FIG. 10 is a block diagram showing the configuration of a digital signal recording apparatus according to a second embodiment using the present invention. This device uses a packet number counting circuit 110 to
The number of packets input during one track is counted, and the address control circuit 10 is controlled at the time when the number of packets exceeding the number is read out by reading the signal of the already input packet again. , Multiple writing.

FIG. 11 is a timing chart showing the recording operation of the apparatus shown in FIG. 10 when the same number of packets are input as in FIG. Assuming that three packets are input in the track section 1, the number is counted and held by the packet counting circuit 110. 3 at the same time
Packets are stored in the storage circuit 4. Reading is performed in the next track section 2. At this time, three packets are normally read, but after the fourth packet, the three packets already read are read again under the control of the address control circuit 10. In FIG. 11, RA
In the track section 2 of the M-A 104, the portion marked with * indicates this rereading. In this reading, the last third packet may be repeatedly read, or the second packet and the third packet may be returned to the first packet.
It may be repeated with the individual. Hereinafter, in the interval 3 between tracks, 2
Track packets have been input, so track section 4
The third and subsequent reading operations are the rereading operation.

As described above, without using the packet flag,
By multiplex-writing only the input packet, even if the ID information 41 is erroneously detected at the time of reproduction and the number of outputs is incorrect, only valid packets are output, so that no problem occurs. Further, since the same packet signal is multiplex-written, even if one packet portion causes a reproduction failure, the multiplex-written portion can be output, so that the reliability can be further improved. Further, it is not necessary to perform processing such as resetting of a packet flag during recording.

Further, in the present system, as shown in FIG. 18 , in order to cope with a transmission error between the receiver 161 and the recording device 162, an encoding circuit 180 is provided, and parity for error correction is added. It is also conceivable that the data is transmitted after being transmitted. FIG. 12 is a block diagram showing the configuration of a digital signal recording apparatus according to the third embodiment for coping with this case, and is obtained by adding an error detection circuit 120 to the apparatus shown in FIG. In this case, if the error detection circuit 120 detects an error in the input packet, it is necessary to stop writing the packet flag to the storage circuit 4 and process the packet flag as an invalid packet.

FIG. 13 is a timing chart showing the recording operation shown in FIG. 12, in which the number of input packets is the same as in FIG. However, in the packets shown by the packet input 101, the portions 130 and 134 which are blacked out are shown.
Indicates that the packet has an uncorrectable error detected by the error detection circuit 120. Bad packet 13
When writing 0 into the storage circuit 4, the error detection circuit 120 controls the control information addition circuit 9 to stop adding the packet flag to the control information. In FIG. 13, in the write packet flag 103, a broken line 131 indicates that the addition of the packet flag is stopped. As a result, RAM-A read 1 in track section 2
In 04, since the packet flag for the 132 packet indicated by the thick line is not added (133 indicated by the broken line in the read packet flag 107), it can be identified as an invalid packet during reproduction, and the output can be stopped. Becomes Similarly, the processing indicated by 135 to 137 is performed on the bad packet 134 input in the track section 2. Also, the control information adding circuit 9
D41 includes an error detection circuit 1 based on the number of input packets.
The number excluding the number of bad packets detected at 20 is recorded.

FIG. 14 shows a configuration of a digital signal recording apparatus according to the fourth embodiment in the case where parity for error correction is added and transmitted and packet flags are not used, as in FIG. FIG. 10 is a block diagram showing
The error detection circuit 120 is added to the device of FIG. In this case, when the error detection circuit 120 detects a bad packet, it is necessary to stop writing to the storage circuit 4.
FIG. 15 is a timing chart showing the recording operation in this case. As in FIG. 13, the bad blocks detected by the error detection circuit 120 are indicated by black packets 150 and 151. If the error detection circuit 120 determines that error correction is impossible, the packet counting circuit 110 stops counting packets, and at the same time, controls the address control circuit 10 to stop updating the packet address. As a result, when the next packet is written, the area where the bad packet is stored is overwritten, and the bad packet is skipped and the writing is performed. At the same time, the number of packets with ID 41 is also
Since the number excluding the number of bad packets is recorded, it is possible to record as a result that no bad packet was input. Thereby, the error detection circuit 120
The output of the bad packet detected by the above can be completely prevented.

In this system, as indicated by a broken line 174 in FIG.
From 68, a case where an uncorrectable flag is input may be considered. In this case, the error detection circuit 1 shown in FIGS.
The same processing may be performed by adding the result of the uncorrectable flag from the error detection circuit 168 to the detection result from the error detection circuit 20.

In the first embodiment, the packet flag is reset for each track, and the packet flag is written in the storage circuit 4 every time a packet is input. In each case, a part or all of the control information is set to a specific value, and when the packet is normally input, the input control information is overwritten in the storage circuit 4 as it is to obtain the same effect. Can be obtained. In this case, at the time of reproduction, the control information of the non-input portion or the packet determined to be defective by the error detection circuit 120 has a specific value, so that the packet can be determined to be an invalid packet.

In the first and third embodiments, a part of the input control information is used as the packet flag. However, an area for inserting the packet flag on the magnetic tape can be secured. At this time, a packet flag may be added to each packet data and recorded. In this case, the selection circuit 3 is not required, and the control information addition circuit 9 may directly write to the storage circuit 4 or add the information using the ID generation circuit 11.

The above processing is not performed, and the end flag may be recorded in the control information of the last valid packet in each track or the invalid packet next to the last valid packet. . For example, in the timing diagram of FIG.
Last valid packet 3 in AM packet reading
00, 302, 304 or invalid packets 301, 30
The control information adding circuit 9 adds an end flag to a part of the control information of the packets 3 and 305. This processing is performed in the same manner as the addition of the packet flag using the selection circuit 3 in the circuit of FIG.
1, a part of the control information of the signal read from the storage circuit 4 may be replaced with an end flag. Further, the packet data of the invalid packet next to the last valid packet in each track (for example, 301, 303, 3
05) may be replaced with specific data. At the time of writing to the storage circuit 4, it is difficult to determine whether or not the track is the last track. Therefore, the above-described method which can be operated when reading from the storage circuit 4 can be easily executed. At the time of reproduction, the end of the valid packet area or the start of the invalid packet area can be detected by determining these end flags and specific data. When the maximum number of packets that can be recorded on the track is input, the end flag recording of the invalid packet next to the last valid packet or the rewriting to the specific data is not performed. When the error detection circuit 120 determines that the last input packet is a bad packet, the previous valid packet is processed as the last packet as in the processing of the packet 150 in FIG.

As a method of identifying valid packets and invalid packets, it is conceivable to clear the entire packet data area of the storage circuit 4 for each track before inputting a packet. Since the number of times is extremely increased, it is better to use the present invention. In the first and third embodiments, only a packet flag is added to an invalid packet, and the packet signal 51 is recorded as it is. But with invalid packets,
The recording may be performed after converting the packet signal 51 into a specific signal. As a result, the reliability of distinguishing valid packets from invalid packets can be further improved.

In the above description, the case of recording on a magnetic tape has been described as an example. However, the present invention can be implemented similarly when a disk or the like is used. In this case, the track cycle may be a cycle of one rotation of the disk or one video frame cycle. Although the receiver 161 and the recording device 162 are separate devices, a demodulation circuit 167 and an error detection circuit 168 may be provided in the recording device 162.

[0044]

According to the present invention, in a device for recording a digital compressed video signal in packet units, if the number of packets to be recorded per unit time is variable, it is possible to reliably identify whether or not the packet is a newly input packet. And the output of abnormal data of reproduction can be prevented. Further, even in the case where a flag indicating an error situation during transmission is added and transmitted, a packet in which an error is detected can be processed as an invalid packet, so that a control operation due to a transmission error can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital signal recording device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a recording format of the digital signal recording device.

FIG. 3 is a configuration diagram showing a block format.

FIG. 4 is a configuration diagram showing a format of an ID.

FIG. 5 is a diagram illustrating a packet configuration of first input data and a block configuration diagram when recording.

FIG. 6 is a diagram illustrating a packet configuration of second input data and a block configuration when recording.

FIG. 7 is a diagram illustrating a packet configuration of third input data and a block configuration when recording.

FIG. 8 is a diagram illustrating a packet configuration of fourth input data and a block configuration when recording.

FIG. 9 is a timing chart showing a recording operation of the apparatus of FIG. 1;

FIG. 10 is a block diagram showing a configuration of a digital signal recording device according to a second embodiment of the present invention.

FIG. 11 is a timing chart showing a recording operation of the apparatus of FIG.

FIG. 12 is a block diagram illustrating a configuration of a digital signal recording device according to a third embodiment of the present invention.

FIG. 13 is a timing chart showing a recording operation of the apparatus of FIG.

FIG. 14 is a block diagram showing a configuration of a digital signal recording device according to a fourth embodiment of the present invention.

FIG. 15 is a timing chart showing a first recording operation of the apparatus of FIG.

16 is a timing chart showing a second recording operation of the apparatus of FIG.

FIG. 17 is a block diagram showing a first configuration example of a digital signal transmission system including a digital signal recording device using the present invention.

FIG. 18 is a block diagram showing a second configuration example of a digital signal transmission system including a digital signal recording device using the present invention.

[Explanation of symbols]

 2 input processing circuit, 3 selection circuit, 4 storage circuit, 5 recording processing circuit, 6 recording amplifier, 7 rotating head, 8 magnetic tape, 9 control information adding circuit, 10 address control circuit, 11: ID generation circuit, 13: Timing generation circuit, 17: Reset circuit, 27: Data recording area, 40: Synchronization signal, 41: ID information, 42: Data, 43: C1 parity, 50: Control information, 51: Packet 52, time information, 27, packets, 70 to 73, control information, 78, control information, 80, frame information, 81, track information, 83 to 87, control information, 110, packet number counting circuit, 120, error detection Circuit: 160: transmitter; 161, receiver: 162: recording device; 162: encoding circuit; 250: control information; 251: control information.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H04N 5/92 H04N 5/92 H 7/30 7/133 Z (56) References JP-A-4-255187 (JP, A) JP-A-7-254237 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20/10-20/16 351 H04N 5/91-5/95

Claims (15)

(57) [Claims] 1. A digital signal recording apparatus capable of recording n (n is a natural number) packet-based digital signals on a recording medium in a specific cycle, wherein m (m
Is a natural number, a variable number of m ≦ n) input means, a storage means for temporarily storing the digital signal input to the input means, and the identification means for the digital signal stored in the storage means. Packet information generating means for generating packet information indicating whether the number of packets has been input in a cycle or a packet input in other cycles; and the packet generated by the packet information generating means information, by replacing a portion of the stored digital signal in the storage means, or in addition to this, the
The packet with the replaced or added packet information is
recording means for recording on the recording medium as digital signals in units of n packets, the digital signal recording apparatus comprising: 2. The digital signal recording apparatus according to claim 1, wherein said digital signal includes digital information and control information which is information related to said digital information, and a part or all of said control information is transmitted by said packet information. A digital signal recording apparatus, comprising: a control information converting means for replacing the control information with the control information converting means; and storing an output signal of the control information converting means in the storage means. 3. A digital signal recording apparatus according to claim 1, wherein said digital signal includes digital information and control information which is information related to said digital information, and said storage means is provided prior to input of said digital signal. And control information setting means for converting the control information stored in the control information into a specific value. When the input means inputs the digital signal, the control information is stored in the storage means as it is. Digital signal recording device. 4. A digital signal recording apparatus according to claim 3, wherein said control information is frame information or track information relating to an output device which has output said digital signal to said input means. . 5. A digital signal recording apparatus capable of recording n (n is a natural number) packet units of digital signals on a recording medium in a specific cycle, wherein m (m
Is a natural number, a variable number of m ≦ n), and the m digital signals input to the m-th packet recording area on the recording medium are recorded. In the recording area of the n-th packet,
A digital signal recording apparatus, comprising: recording means for recording any one of the up to m input packets. 6. The digital signal recording apparatus according to claim 5, wherein input means for inputting said digital signal in packet units, packet counting means for counting the number of said packets input to said input means, and said input means Storage means for temporarily storing the digital signal input in step (a), and address control means for controlling an address of the storage means, wherein the recording means stores the digital signal stored in the storage means in the recording medium. When reading signals from the storage means to the storage means, the address control means reads up to the m-th packet storage area when reading the m-th packet. When reading out the (m + 1) th to nth packets, one of the m written packets is read out. Digital signal recording apparatus characterized by Gosuru. 7. A digital signal recording apparatus according to claim 1, wherein an error detection parity is added to said digital signal, and said recording means detects an error in a packet-based digital signal input by said parity. When it is determined that the packet information is present or uncorrectable, the packet information indicating that the m packets are input in the specific cycle is not recorded on the recording medium, or is input in a cycle other than the specific cycle. A digital signal recording device for recording, on the recording medium, the packet information indicating that the packet is a converted packet. 8. The digital signal recording apparatus according to claim 7, wherein: an error detecting means for correcting or detecting an error of the digital signal by using the parity inputted by the input means; Reset means for resetting the packet information stored in the storage means, wherein the packet information generation means, when the error detection means determines that the digital signal is erroneous or uncorrectable, A digital signal recording device which does not generate packet information. 9. A digital signal recording apparatus according to claim 7, wherein said digital signal includes digital information and control information which is information related to said digital information, and uses said parity inputted by said input means. Error detection means for correcting or detecting errors in the digital signal;
Prior to the input of the digital signal, the control means has control information setting means for converting a signal in a storage area of the control information of the storage means to a specific value, and when the input means inputs the digital signal, When there is no error in the digital signal or error correction is performed by the error detection means, the control information is stored in the storage means as it is,
A digital signal recording apparatus, wherein the control information is not stored in the storage means when the error detection means determines that the digital signal has an error or cannot be corrected. 10. The digital signal recording apparatus according to claim 7, wherein said recording means converts the digital signal of the packet determined as having an error or uncorrectable by said parity into an error-free packet. Or a digital signal recording apparatus for recording the digital signal on the recording medium after replacing the digital signal with a digital signal of an error-corrected packet. 11. A digital signal recording apparatus according to claim 1, further comprising a data conversion means for replacing said digital signal with a specific signal. And a digital signal recording apparatus which replaces a digital signal of a packet determined not to be m packets input within the specific period with the specific signal and records the digital signal on the recording medium. 12. A digital signal recording apparatus capable of recording n (n is a natural number) digital signals in packet units on a recording medium in a specific cycle, wherein m (m is a natural number, m ≦ n) within the specific cycle. Variable number of packets)
A part of the digital signal of the m-th or (m + 1) -th packet is replaced with an end signal indicating the end of input, or the end signal is added to the digital signal, and the recording medium is converted into a digital signal of n packets. A digital signal recording device, comprising recording means for recording data on a digital signal. 13. A digital signal recording apparatus according to claim 12, wherein said digital signal includes digital information and control information which is information related to said digital information, and part or all of said control information is transmitted to said end signal. A digital signal recording device comprising a control information conversion means for replacing with a control signal. 14. A digital signal recording apparatus according to claim 1, further comprising reset means for resetting said packet information indicating at least said m packets stored in said storage means. Signal recording device. 15. The digital signal recording apparatus according to claim 1, further comprising reset means for resetting said packet information stored in said storage means at each specific period.