JPH08203213A - Digital signal recording apparatus - Google Patents

Abstract

PURPOSE: To obtain a digital signal recording apparatus by which a new input bucket can be surely discriminated even when the number of recording buckets per unit time is variable by recording an ID, a bucket flag and the like according to the number of buckets so as to be added to bucket information to be recorded via a storage circuit which is reset as required. CONSTITUTION: In an input processing circuit 2, the bucket structure or the like of input digital compressed bucket information is judged, and the bucket information is recorded on a magnetic tape 8 via a storage circuit 4 which is reset in every truck or the like by a reset circuit 17. When the information is recorded, a recording processing circuit 5 adds a flag indicating an effective bucket to an empty region for control information 250 in addition to an ID 41 indicating the number of buckets form an ID generation circuit 11 based on the output of the circuit 2, to the control information 250 at the head part of a bucket and to a parity 45 for error correction on the basis of an error correction processing operation by the circuit 5. A new input bucket can be surely discriminated even when the number of buckets is variable on the basis of the flag of the information 250 even when the ID 41 is read out erroneously by this recording format.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording apparatus for recording a digital signal, and more particularly to a recording apparatus suitable for recording a digital compressed video signal transmitted in packet units.

[0002]

2. Description of the Related Art A digital signal recording apparatus for recording a digital compressed video signal on a magnetic tape using a rotary head is disclosed in Japanese Patent Laid-Open No. 174496/1993. Using this apparatus, the transmission system shown in FIG. 16 can record and reproduce the packet-unit digital compressed video signal received by the receiver 161 from the transmitter 160.

In FIG. 16, reference numeral 160 denotes a transmitter, and 161.
Is a receiver, 162 is a recording device, 163 is a video output terminal,
164 is a compression circuit, 165 is an encoding circuit, 166 is a modulation circuit, 167 is a demodulation circuit, 168 is an error detection circuit, 16
Reference numeral 9 is a switch, 170 is an expansion circuit, and 175 is an information source. In this system, the digital information stored in the information source 175 of the transmitter 160 is digitally compressed by the compression circuit 164, and the error is detected by the encoding circuit 165.
A parity for correction is added, modulation processing is performed by the modulation circuit 166, and the data is transmitted. In the receiver 161, the demodulation circuit 167
The received signal is demodulated, and the error detection circuit 168 detects and corrects the error. When recording on the recording device 162,
An error-detected and corrected signal is sent to the signal line 172 for recording. To see the received video directly, switch 16
9 is the output 172 of the error detection circuit 168
When viewing the video recorded in No. 2, the switch 169 selects the output 173 of the recording device and sends each signal to the decompression circuit 170. In the expansion circuit 170, the compression circuit 164
The signal compressed by is returned to the original video signal and output from the video output terminal 163. It should be noted that the compression circuit 164 is not shown if the signal stored in the information source 175 has been previously compressed, and is therefore indicated by a dotted line.

[0004]

Generally, the transmitter 160
Since there are a plurality of receivers 161 connected to each other, when a signal is transmitted, an identification code for a specific receiver, time information, etc. are added, and burst signals are output in packet units at arbitrary time intervals. Therefore, the number of packets transmitted per unit time is variable.

Further, the transmission digital compressed signal may have a transmission error due to noise or the like during transmission. Therefore, the encoding circuit 165 generally adds an error correction code for error detection and correction. . Receiver 1
When the error detection / detection circuit 168 of 61 determines that the packet cannot be corrected, the output of the signal of the packet to the signal line 172 may be stopped and no signal may be output. Therefore, the number of packets per unit output to the signal line 172. Is likely to change further. In this case, regarding the output stopped packet, it is possible to detect that the packet is missing from the time information added to the packets before and after the output stopped packet.

The above conventional apparatus does not consider the case where the number of packets recorded per unit time is variable. Therefore, if m packets are input in the k-th unit time, and n (n <n
When m) packets are input, the kth packet is recorded as it is as the mn packets in the k + 1th unit time.

It is also possible to output the detection result of the error detection circuit 168 to the recording device 162 as a flag, as indicated by the signal line 174. Further, as shown in FIG. 17, as a countermeasure against a transmission error between the receiver 161 and the recording device 162, an encoding circuit 180 is provided and a signal line 181 is provided.
It is conceivable that a parity is newly added to the signal output to.

The above-mentioned conventional apparatus does not consider the correspondence to these flags and parity.

An object of the present invention is to provide a digital signal recording apparatus which can cope with a case where the number of packets to be recorded per unit is variable and a case where a flag indicating an error condition during transmission is added and transmitted. To provide.

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to provide, in a digital signal recording device for recording a packet-unit digital compressed video signal, an input means for inputting a packet-unit digital signal, and the input means for the packet-unit digital signal. Packet information generation means for generating the packet information each time a signal is input, storage means for temporarily storing the digital signal input by the input means, and the signal stored in the storage means is recorded in the recording medium. This can be achieved by providing a recording means and a reset means for resetting the packet information stored in the storage means for each specific cycle.

When the input digital signal is composed of digital information and control information which is information related to the digital information, prior to input of the digital signal,
Control information setting means for converting a signal in the storage area of the control information of the storage means into a specific value may be provided.

Further, an error detecting means for correcting or detecting an error in the digital signal by using the parity input by the input means may be provided.

[0013]

[Operation] After resetting all the packet information in the unit cycle by the reset means,
By inputting the digital signal and writing the packet information, the packet information of the part that was not input is
It will remain reset. As the packet information of the input portion, the packet information generated by the packet information generating means is written, so that it is surely an effective packet,
It is possible to identify invalid packets.

On the contrary, the control information is rewritten by the control information setting means to a specific value which is not originally used, and then the digital information and the control information are written to control the area not input. Since the information remains the specific value, the valid packet and the invalid packet can be similarly identified.

Further, a packet judged by the error detecting means to have an error can be prevented from being output as a valid packet at the time of reproduction by performing the same processing as an invalid packet which has not been input. Becomes

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the arrangement of a digital signal recording apparatus according to the first embodiment of the present invention. This apparatus is the recording apparatus 1 shown in FIGS.
It corresponds to 62. In FIG. 1, 1 is a signal input terminal, 2 is an input processing circuit, 3 is a selection circuit, 4 is a storage circuit, 5 is a recording processing circuit, 6 is a recording amplifier, 7 is a rotary head, 8 is a magnetic tape, and 9 is control. An information adding circuit, 10 is an address control circuit, 11 is an ID generation circuit, 12 is a servo circuit, 13 is a timing generation circuit, and 17 is a reset circuit.

FIG. 2 shows a recording pattern of signals recorded on the magnetic tape 8, 23 is an additional information recording area for audio signals, 27 is a data recording area for recording a digital compressed video signal, and 31 is time information. , Subcode recording areas for recording subcodes such as program information, 22, 26,
30 is the preamble of each recording area, 24, 2
8 and 32 are postambles of the respective recording areas, 2
5, 29 are the gaps between the respective regions, 21, 33
Is the margin at the track edge. In this way, by providing the preamble, the postamble, and the gap in each area, each area can be post-recorded independently. Of course, signals other than audio signals and digital compressed video signals may be recorded in the additional information recording area 23 and the data recording area 27.

FIG. 3 shows a block structure of a signal recorded in the data recording area. One block is a sync signal (2 bytes) indicating the beginning of the block, I indicating the packet structure, etc.
Data 19 consisting of D4 (4 bytes) and 195 bytes
It is composed of 5 and 9 bytes of parity for error correction. Further, FIG. 4 shows the structure of the ID 41, which includes a 2-bit area code 44 and a 6-bit track address 4.
5, 8-bit frame address 46, 8-bit ID
The data 47 consists of 8-bit parity for error detection.

First, the operation of the apparatus shown in FIG. 1 will be described.

A digital compressed video signal having a packet structure, which will be described later, is inputted from the receiving device 161 shown in FIG. 16 through the signal input terminal 1, the input processing circuit 2 judges the packet structure, etc., and the selection circuit 3 is operated. It is stored in the storage circuit 4 via At that time, the input digital compressed video signal is transmitted in packet units, but the number of packets transmitted per unit time is not constant but variable. Therefore, in the ID data 47, the number of packets transmitted per unit time (in this device, the time when the rotary head rotates 180 °. This is called one track) is recorded in the ID data 47, and an unnecessary signal is output during reproduction. It should be possible to control so as not to do so. The input processing circuit 2 counts the number of packets transmitted in one track, and sends it to the ID generation circuit 11. The signal stored in the memory circuit 4 is added with the parity 43 in the recording processing circuit 5, and further added with the ID 41 and the synchronizing signal 40 generated in the ID generating circuit 11 to perform the modulation processing, and then the recording amplifier 6 The data is recorded on the magnetic tape 8 by the rotary head 7 via.

As described above, although the number of input packets for one track is variable, the number of packets is recorded in the ID data 47, but the ID data 47 is recorded due to an error during reproduction. There is also a possibility that the number of packets to be erroneously detected and output may be erroneous. During recording, the memory circuit 4
In the case where the number of input packets is smaller than that of the previous track, the signal input to the previous track remains as it is and is recorded on the magnetic tape 8. Occurs, the signal of the previous track is output. Therefore, in this apparatus, by recording the packet flag indicating that the packet is input for each packet, the validity of each packet can be judged at the time of reproduction. This packet flag will be described.

5A to 8A show the packet structure of the digital compressed video signal output from the receiver 161. This device is capable of recording digital compressed video signals with various packet structures.

In the packet structure of FIG. 5, each packet consists of 195 bytes, and the first 3 bytes are control information 50 indicating the content of data, recording time, copy control information and the like. In this case, since the number of bytes in one packet is equal to the number of data per block shown in FIG. 3, 195 bytes of data including the control information 50 of 3 bytes are recorded as one block. However, since the control information 50 has an unused area, the above-mentioned packet flag is written here. As a result, as shown in FIG. 5B, the first 3 bytes of the data 42 in FIG. 3 are recorded as the control information 250 including the packet flag.

FIG. 9 shows the recording timing. The track identification signal 100 indicates the time in which the rotary head 7 makes one rotation in one cycle, is generated by the timing generation circuit 13, and the rotation number of the rotary head 7 is controlled by the servo circuit 12. In the figure, the operation is performed when 3 packets are input in the track section 1, 7 packets in the track section 2, 2 packets in the track section 3, and 4 packets in the track section 4. Further, the storage circuit 4 has two banks, and writing of an input signal via the selection circuit 3 and reading to the recording processing circuit 5 are alternately performed for each track. In FIG. 9, each of RAM-A and RAM-B is 1
It corresponds to one bank, and RAM is used in track sections 1 and 3.
A is writing, RAM-B is reading, and in track sections 2 and 4, RAM-A is reading and RAM-B is writing.

Packet counter 101 of input processing circuit 2
The number of input packets is counted by (cleared to 0 at the beginning of each track). The write packet flag 103 is generated by the input processing circuit 2 every time a packet is input, and added to the control information 50 by the control information adding circuit 9 to obtain the control information 250. At the timing when the control information 50 is stored in the storage circuit 4, the selection circuit 3 selects the control information addition circuit 9 so that the control information 250 is stored in place of the control information 50. By resetting all the packet flags for each track by the reset circuit 17, the packet flags are added only to the newly input new packet. In the next track section, the reading to the recording processing circuit 5 is performed, but when reading more than the number of input packets, the packet flag is not added, so the data is stored before the previous track. It is possible to distinguish old packets from new packets. After that, it is recorded on the magnetic tape 8 through the same processing as other data. To reset the packet flag, as shown by 105 in FIG. 9, the portion related to the packet flag in the control information 250 may be cleared immediately after reading each packet, or at the end of each track as in 106. A clear section may be provided to reset the packet flags for all packets. During reproduction, by detecting the control information 250 for each packet, it is possible to completely discriminate between the output packet and the non-output packet. Furthermore, as shown in FIG. 5B, since the control information 250 can detect and correct an error by the parity 43 and the like, the reliability is significantly improved as compared with the determination based only on the number of valid packets of the ID 41. .

FIG. 6 shows a case in which the control information 50 is input in 4 bytes, the time information 3 indicating the transmitted time is 3 bytes, and the packet data is input in 188 bytes, that is, 195 bytes in total. In this case as well, the number of packet bytes matches the number of block bytes, so 1 packet = 1
Record as a block. Further, by writing the packet flag in the control information 251, the same processing as in the case of FIG. 5 may be performed.

FIG. 7 shows 3 bytes of time information 52, 1 byte of control information 78 and 140 bytes of packet data 79.
In this case, a total of 144 bytes constitutes one packet.
In this case, since the packet byte number and the block byte number are different, four packets are recorded over three blocks as shown in FIG. At that time, the control information 50 of 3 bytes is placed at the head of the data of each block, and 144 bytes of data is placed in the remaining 192 bytes area. The packet flag is the control information 70, 7
One flag is assigned to each packet by writing to 1, 72 and 73. The timing generation circuit 13 determines the write timing of each control information in the first block, the second block, and the third block, and controls the selection circuit 3 to write the packet flag in the storage circuit 4.

FIG. 8 shows 4-bit frame information 80 and 4 bits.
A case is shown where one packet is composed of a total of 78 bytes of bit track information 81 and 77-byte packet data 82. In this case, 5 packets are recorded over 2 blocks. At this time, the control information 50 for each block is not recorded, and 78-byte data is sequentially arranged in two blocks.
The control information 83 to 87 in FIG.
Since it is the frame information 80 and the track information 81 in FIG. 9A, the packet flag cannot be added. Therefore, in the flag reset 105 or 106 in FIG. 9, the reset circuit 17 is used to write the control information 83 to 87 to a specific value that cannot actually exist. In writing the packet flag, the input signal is stored in the storage circuit 4 as it is. As a result, the frame information 80 and the track information 81 for the old packet are recorded on the magnetic tape 8 as specific values, so that the frame information 80 and the track information 8 are reproduced at the time of reproduction.
By detecting the abnormality of 1, it is possible to distinguish between a valid packet and an invalid packet.

As described above, for each packet,
By recording a flag for identifying a newly input packet or a previously input old packet, the reliability can be improved as compared with the case where only the ID 41 indicating the number of input packets is used. Further, since this flag needs to be added to each packet, if the ID 41 added one to one block is used, a signal having the packet structure shown in FIGS. 7 and 8 is recorded. Sometimes it is not possible to use, so control information must be used as in the present invention.

It is also possible to use a method of multiple-writing the already-input packets in the recording area of the uninput packets without using the packet flag. Hereinafter, this method will be described as a second embodiment.

FIG. 10 is a block diagram showing the structure of a digital signal recording apparatus according to the second embodiment of the present invention. This apparatus uses the packet number counting circuit 110 to
By counting the number of packets input during one track and reading the storage circuit 4 in excess of that number, the address control circuit 10 is controlled to read the signal of the already input packet again. , Multiple writing is performed.

FIG. 11 is a timing chart showing the recording operation of the apparatus of FIG. 10, when the same number of packets are input as in the case of FIG. If three packets are input in the track section 1, the number of packets is counted and held by the packet counting circuit 110. 3 at the same time
The individual packets are stored in the storage circuit 4. Reading is performed in the next track section 2. At this time, reading of three packets is normally performed, but after the fourth packet, the three packets that have already been read are read again under the control of the address control circuit 10. In FIG. 11, RA
In the track section 2 of the M-A 104, the part marked with * indicates this rereading. In this reading, the last third packet may be read repeatedly, or the second packet may be read again after returning to the first packet.
May be repeated with the first item. Below, between tracks 3 is 2
Since packet input has been performed, track section 4
For the reading of, the third and subsequent operations are the re-reading operation.

As described above, without using the packet flag,
By writing only the input packet in multiplex, even if the ID information 41 is erroneously detected at the time of reproduction and the output number is incorrect, only the valid packet is output, so that no problem occurs. Furthermore, since the same packet signal is written multiple times, even if one packet portion causes a reproduction failure, the multiple written portion can be output, so that the reliability can be further improved. Further, it is not necessary to perform processing such as resetting the packet flag at the time of recording.

Further, in this system, as shown in FIG. 17, in order to cope with a transmission error between the receiver 161 and the recording device 162, an encoding circuit 180 is provided to add a parity for error correction. It may be transmitted after being transmitted. FIG. 12 is a block diagram showing the configuration of a digital signal recording apparatus according to the third embodiment for coping with this case, in which an error detection circuit 120 is added to the apparatus of FIG. In this case, if the error detection circuit 120 detects an error in the input packet, it is necessary to stop writing the packet flag to the storage circuit 4 and process it as an invalid packet.

FIG. 13 is a timing chart showing the recording operation of FIG. 12, and is for the same number of input packets as in FIG. However, in the packet shown in the packet input 101, black-painted portions 130 and 134
Indicates that the error detection circuit 120 has detected an uncorrectable error. Bad packet 13
When writing 0 to the memory circuit 4, the error detection circuit 120 controls the control information addition circuit 9 to stop adding the packet flag to the control information. In FIG. 13, in the write packet flag 103, 131 indicated by a broken line indicates that the addition of this packet flag is stopped. As a result, the reading 1 of the RAM-A in the track section 2
In No. 04, since the packet flag for the 132 packet shown by the thick line is not added (133 shown by the broken line in the read packet flag 107), it can be identified as an invalid packet at the time of reproduction, and the output can be stopped. Becomes Similarly, the processing indicated by 135 to 137 is performed on the defective packet 134 input in the track section 2. Further, the control information adding circuit 9 causes I
The error detection circuit 1 is input to D41 from the number of input packets.
The number excluding the number of bad packets detected in 20 is recorded.

Similarly to FIG. 12, FIG. 14 shows the configuration of the digital signal recording apparatus according to the fourth embodiment when the error correction parity is added and transmitted and the packet flag is not used. 11 is a block diagram showing FIG.
The error detection circuit 120 is added to the above device. In this case, when the error detection circuit 120 detects a defective packet, it is necessary to stop writing to the storage circuit 4.
FIG. 15 is a timing chart showing the recording operation in this case. Similar to FIG. 13, the defective blocks detected by the error detection circuit 120 are shown by black packets 150 and 151. When the error detection circuit 120 determines that the error cannot be corrected, the packet counting of the packet number counting circuit 110 is stopped, and at the same time, the address control circuit 10 is controlled to stop the updating of the packet address. As a result, the writing of the next packet is overwritten in the area in which the defective packet is stored, and the defective packet is skipped and the writing is performed. At the same time, the number of packets with ID41
Since the number excluding the number of bad packets is recorded, it is possible to record as a result, assuming that the bad packet was not input. As a result, the error detection circuit 120
It is possible to completely prevent the output of the bad packet detected by.

Further, in this system, as indicated by a broken line 174 in FIG. 16, the error detection circuit 1 of the receiver 161 is
It is possible that the uncorrectable flag is input from 68. In this case, the error detection circuit 1 shown in FIGS.
The same processing may be performed by adding the result of the uncorrectable flag from the error detection circuit 168 to the detection result from 20.

In the first embodiment, the packet flag is reset for each track, and the packet flag is written in the storage circuit 4 every time a packet is input. The same effect can be obtained by setting a part or all of the control information to a specific value for each time and, when a packet is normally input, overwriting the input control information in the storage circuit 4 as it is. Can be obtained. In this case, at the time of reproduction, it can be determined as an invalid packet because the control information of the uninput portion or the packet determined to be defective by the error detection circuit 120 has a specific value.

In the first and third embodiments, part of the input control information is used as the packet flag, but it is possible to secure an area for inserting the packet flag on the magnetic tape. In this case, a packet flag may be added to each packet data and recorded. In this case, the selection circuit 3 becomes unnecessary, and the control information addition circuit 9 may directly write to the storage circuit 4 or may be added by using the ID generation circuit 11.

The end flag may be recorded in the control information of the last valid packet in each track or the invalid packet next to the last valid packet without performing the above processing. . For example, in the timing diagram of FIG.
Last valid packet 3 in AM packet reading
00, 302, 304 or invalid packets 301, 30
An end flag is added to a part of the control information of the packets 3 and 305 by using the control information adding circuit 9. It should be noted that this processing is performed by using the selection circuit 3 in the circuit of FIG.
1 may be used to replace a part of the control information of the signal read from the memory circuit 4 with the end flag. Further, the packet data of the invalid packet next to the last valid packet in each track (for example, 301, 303, 3
05) may be rewritten with specific data. When writing to the memory circuit 4, it is difficult to determine whether or not it is the last track, so the above method that can be operated when reading from the memory circuit 4 can be easily executed. At the time of reproduction, the end of the valid packet area or the beginning of the invalid packet area can be detected by discriminating the end flag and the specific data. When the maximum number of packets that can be recorded on the track is input, the end flag of the next invalid packet of the last valid packet is not recorded, or the specific data is not rewritten. When the error detection circuit 120 determines that the last input packet is a defective packet, the previous valid packet is processed as the last packet as in the processing of the packet 150 in FIG.

As a method of identifying a valid packet and an invalid packet, it is conceivable to clear the entire packet data area of the memory circuit 4 for each track before inputting the packet. Since the number of times is extremely increased, it is better to use the present invention. In addition, in the first and third embodiments, only the packet flag is added to the invalid packet, and the packet signal 51 is recorded as it is. However, in the invalid packet,
Recording may be performed after converting the packet signal 51 into a specific signal. As a result, the reliability of identification of valid packets and invalid packets can be further improved.

In the above description, the case of recording on a magnetic tape has been described as an example, but the present invention can be similarly implemented when a disk or the like is used. In this case, the track cycle may be one disk rotation cycle or one video frame cycle. Further, although the receiver 161 and the recording device 162 are separate devices, the demodulation circuit 167 and the error detection circuit 168 may be provided in the recording device 162.

[0044]

According to the present invention, in a device for recording a digital compressed video signal in packet units, if the number of packets recorded per unit time is variable, it can be surely identified whether it is a newly input packet. It is possible to prevent the output of abnormal reproduction data. Further, even when a flag indicating an error condition during transmission is added and transmitted, a packet in which an error is detected can be processed as an invalid packet, so that an operation due to a transmission error can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a digital signal recording apparatus according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a recording format of the present digital signal recording apparatus.

FIG. 3 is a configuration diagram showing a block format.

FIG. 4 is a configuration diagram showing an ID format.

5A and 5B are a packet configuration diagram of first input data and a block configuration diagram when recording.

6A and 6B are a packet configuration diagram of second input data and a block configuration diagram at the time of recording.

[Fig. 7] Fig. 7 is a packet configuration diagram of third input data and a block configuration diagram when recording.

FIG. 8 is a packet configuration diagram of fourth input data and a block configuration diagram when recording.

9 is a timing chart showing a recording operation of the apparatus of FIG.

FIG. 10 is a block diagram showing a configuration of a digital signal recording device according to a second embodiment of the present invention.

11 is a timing diagram showing a recording operation of the apparatus of FIG.

FIG. 12 is a block diagram showing a configuration of a digital signal recording device according to a third embodiment of the present invention.

13 is a timing chart showing a recording operation of the apparatus shown in FIG.

FIG. 14 is a block diagram showing a configuration of a digital signal recording device according to a fourth embodiment of the present invention.

FIG. 15 is a timing diagram showing a first recording operation of the apparatus of FIG.

16 is a timing chart showing a second recording operation of the apparatus of FIG.

FIG. 17 is a block diagram showing a first configuration example of a digital signal transmission system including a digital signal recording device using the present invention.

FIG. 18 is a block diagram showing a second configuration example of a digital signal transmission system including a digital signal recording device using the present invention.

[Explanation of symbols]

 2 ... Input processing circuit, 3 ... Selection circuit, 4 ... Storage circuit, 5 ... Recording processing circuit, 6 ... Recording amplifier, 7 ... Rotary head, 8 ... Magnetic tape, 9 ... Control information adding circuit, 10 ... Address control circuit, 11 ... ID generation circuit, 13 ... Timing generation circuit, 17 ... Reset circuit, 27 ... Data recording area, 40 ... Sync signal, 41 ... ID information, 42 ... Data, 43 ... C1 parity, 50 ... Control information, 51 ... Packet , 52 ... Time information, 27 ... Packets, 70-73 ... Control information, 78 ... Control information, 80 ... Frame information, 81 ... Track information, 83-87 ... Control information, 110 ... Packet number counting circuit, 120 ... Error detection Circuit, 160 ... Transmitter, 161 ... Receiver, 162 ... Recording device, 162 ... Encoding circuit, 250 ... Control information, 251 ... Control information.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G11B 20/18 532 B 9558-5D 574 B 9558-5D H04N 5/92 7/30

Claims (14)

[Claims] 1. A digital signal recording apparatus for recording n (n is a natural number) digital signals in packet units on a recording medium for each specific period, wherein m (m is a natural number, m ≦ n) within the specific period. A variable number of packets are input, and packet information indicating that the number of packets input in the specific period is m packets or not indicating the number of packets input in the specific period is the digital signal. A digital signal recording apparatus, characterized in that it is recorded on the recording medium in place of a part of the above or is added to the digital signal and recorded on the recording medium. 2. A digital signal recording apparatus according to claim 1, wherein the input means for inputting the digital signal in packet units and the packet information are generated each time the input means inputs the digital signal in packet units. Packet information generation means, storage means for temporarily storing the digital signal input by the input means, recording means for recording the signal stored in the storage means on the recording medium, and the storage for each specific period. A digital signal recording apparatus comprising reset means for resetting the packet information stored in the means. 3. The digital signal recording apparatus according to claim 2, wherein the digital signal comprises digital information and control information which is information related to the digital information, and part or all of the control information is the packet information. A digital signal recording device, comprising: a control information converting unit for replacing the output signal of the control information converting unit in the storage unit. 4. A digital signal recording apparatus according to claim 1, wherein said digital signal comprises digital information and control information which is information related to said digital information, and input means for inputting said packet-based digital signal. A storage means for temporarily storing the digital information and the control information input by the input means; and a signal in a storage area of the control information in the storage means converted to a specific value prior to the input of the digital signal. Comprising control information setting means and recording means for recording the signal stored in the storage means on the recording medium, and when the input means inputs the digital signal, the control information is stored in the storage means as it is. A digital signal recording device characterized by. 5. The digital signal recording apparatus according to claim 4, wherein the control information is frame information or track information relating to an output device that outputs the digital signal to the input means. . 6. A digital signal recording device for recording n (n is a natural number) digital signals in packet units on a recording medium for each specific period, wherein m (m is a natural number, m ≦ n) within the specific period. Variable number of packets are input, the m digital signals input to the m-th packet recording area on the recording medium are recorded, and the m + 1-th to n-th packets are recorded on the recording medium. A digital signal recording device for recording any of the up to m packets input to the area. 7. A digital signal recording apparatus according to claim 6, wherein the input means inputs the digital signal in packet units, the packet counting means for counting the number of the packets input to the input means, and the input means. The address control means, the storage means for temporarily storing the digital signal input in step 1, the address control means for controlling the address of the storage means, and the recording means for recording the signal stored in the storage means on the recording medium. Controls when reading a signal from the storage means to the recording means, at the time of reading the m-th packet, it reads up to m written packet storage areas. It is characterized by controlling to read out any of the written m packets when reading packets up to Tal signal recording apparatus. 8. A digital signal recording apparatus according to claim 1, wherein the digital signal is added with an error detecting parity, and there is an error in the packet-based digital signal input by the parity or the error cannot be corrected. If it is determined that the packet information indicating that it is m packets input within the specific cycle is not recorded in the recording medium, or that the packet information is not m packets input within the specific cycle. A digital signal recording device characterized by recording the packet information shown in the recording medium. 9. A digital signal recording apparatus according to claim 8, wherein the input means for inputting the digital signal in packet units and the packet information are generated every time the input means inputs the digital signal in packet units. Packet information generating means, error detecting means for correcting or detecting an error of the digital signal using the parity input by the input means, and the digital signal for which error correction or detection is performed by the error detecting means. Storage means for temporarily storing, recording means for recording the signal stored in the storage means on the recording medium, and reset means for resetting the packet information stored in the storage means for each specific period, The packet information generating means has an error or correction error in the digital signal by the error detecting means. If it is determined that, the digital signal recording apparatus characterized by not generating the packet information. 10. A digital signal recording apparatus according to claim 8, wherein said digital signal comprises digital information and control information which is information related to said digital information, and input means for inputting said packet-based digital signal. An error detecting means for correcting or detecting an error in the digital signal by using the parity input by the input means, and the digital information and the control information for which the error correction or detection is performed by the error detecting means Storage means for storing, and prior to input of the digital signal,
The input means comprises the control information setting means for converting the signal in the storage area of the control information of the storage means into a specific value, and the recording means for recording the signal stored in the storage means on the recording medium. When a digital signal is input, when there is no error in the digital signal or when the digital signal is corrected by the error detection means, the control information is stored in the storage means as it is, and the error detection means converts the digital signal into the digital signal. A digital signal recording apparatus, wherein the control information is not stored in the storage means when it is determined that there is an error or the error is uncorrectable. 11. A digital signal recording apparatus according to claim 8, wherein a digital signal of a packet judged to be erroneous or uncorrectable by the parity by the parity is error-free or error-corrected. A digital signal recording device, characterized in that the digital signal of the performed packet is replaced and recorded on the recording medium. 12. A digital signal recording apparatus according to any one of claims 1 to 5 or 8 to 10, further comprising data conversion means for replacing the digital signal with a specific signal. A digital signal recording apparatus, characterized in that the signal of a packet which is judged not to be m packets input within the specific period is replaced with the specific signal and recorded on the recording medium. 13. A digital signal recording apparatus for recording n (n is a natural number) digital signals in packet units on a recording medium for every specific period, and m (m) within the specific period.
Is a natural number, a variable number of m ≦ n), and a part of the digital signal of the m-th or m + 1-th or m + 1-th and subsequent packets is replaced with an end signal indicating the end of input and recorded on the recording medium. Alternatively, the digital signal recording device is characterized in that the end signal is added to the digital signal and recorded on the recording medium. 14. A digital signal recording apparatus according to claim 13, wherein said digital signal comprises digital information and control information which is information related to said digital information, and a part or all of said control information is said end signal. A digital signal recording device comprising a control information converting means for replacing with.