JP2751415B2 - Error detection and correction circuit - Google Patents

Description

The present invention relates to an error correction detection circuit, and more specifically, to an error correction detection circuit.
The present invention relates to a circuit for detecting and correcting an error that occurs during transmission (recording / reproduction) of digital data.

[Prior Art] Generally, a digital data recording / reproducing system,
That is, the data transmission system uses an error correction code for correcting a transmission error. FIG. 3 is a block diagram showing a configuration of a conventional error detection and correction circuit. After being error-correction-coded on the recording (or transmission) side, the input terminal 10 passes through the transmission system,
It is assumed that digital data including a transmission error is input. The data reproduction circuit 12 reproduces the input data of the input terminal 10 by processing such as demodulation, synchronization separation, and ID recognition, and outputs reproduced data. This playback data is the recognized ID
The information is written directly into the data memory 20 based on the information, and is simultaneously applied to the syndrome calculation circuit 14 for error correction.

The syndrome calculation circuit 14 calculates the syndrome of the transmission data by a well-known method, and sequentially writes the syndrome of each code in the syndrome memory 16. The error position and error pattern calculation circuit 18 reads out the syndrome written in the syndrome memory 16 and performs decoding calculation. Here, if the syndromes of the corresponding code are all 0, it is determined that there is no error, and the processing of the code ends. However, when all the syndromes are not 0, that is, when there are errors, and when it is determined that the errors can be corrected based on these syndromes, the circuit 18 calculates an error position and an error pattern, and uses the result. Data
The data in the memory 20 is corrected. If it is determined that error correction is impossible, the data of the corresponding code in the data memory 20 is left as it is, and a process of newly writing a correction flag indicating that an error is included in the data memory 20 is performed. .

The data in the data memory 20 is finally output from the output terminal 22.

[Problems to be Solved by the Invention] In the above conventional example, if the digital data to be handled is image data, it is often the case that uncorrectable data can be effectively corrected by interpolation. In such a case, the probability of erroneous correction becomes a bigger problem than the probability of being uncorrectable and becoming the target of the initial stage of interpolation. That is, the degree of image quality degradation of the reproduced image is larger when erroneous correction occurs.

In particular, when a countermeasure against a burst error such as interleaving cannot be performed sufficiently effectively, a countermeasure for minimizing erroneous correction due to a burst error is required. For example, when a burst error remains in the configuration direction of the error correction code, about 1/500 of a code capable of two error detection and one error correction is about 1/500 of a code capable of two error detection and two error correction. Erroneous correction occurs with a probability of about 20. Normally, the probability of occurrence of such a burst error itself is small, so that the probability of erroneous correction as a code is small. However, when a burst error actually occurs, erroneous correction occurs with a considerably large probability.

As described above, in the case of data that can be effectively dealt with by interpolation processing such as image data, it is important in terms of image quality, that is, signal quality, to lower the error correction probability even if the interpolation probability slightly increases. .

Accordingly, an object of the present invention is to provide an error detection and correction circuit that reduces the probability of erroneous correction due to a burst error.

[Means for Solving the Problems] An error detection and correction circuit according to the present invention comprises: syndrome calculation means for performing syndrome calculation for error correction detection from input data obtained from a reproducing head; and a calculation result of the syndrome calculation means. And a burst error detecting means for detecting an output signal of the reproducing head by envelope detection and detecting a burst error based on the detected output, and a burst error detecting means for detecting a burst error based on the detected output. A burst memory means for storing the detection result of the error detection means in association with each error correction code, and decoding calculation of an error correction code from the syndrome of each error correction code stored in the syndrome memory means; Error correction means for correcting an error in the input data; When the detection result read for each correction code indicates that there is a burst error, the correction by the error correction means is prohibited even if it is determined that the code can be corrected.

[Operation] By the above means, the probability of erroneous correction at the location of a burst error can be reduced.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
Like the input terminal 10, the input terminal 30 receives digital data containing a transmission error (in this embodiment, the output of the reproducing head in the digital VTR reproducing system). The data reproducing circuit 32 reproduces the input data of the input terminal 30 by processing such as demodulation, synchronization separation, and ID recognition, and outputs reproduced data. The reproduced data is directly written into the data memory 40 based on the recognized ID information, and is simultaneously applied to the syndrome calculation circuit 34 for error correction. The syndrome calculation circuit 34 calculates the syndrome of the transmission data by a well-known method, and sequentially writes the syndrome of each code in the syndrome memory 36.

The burst error detection circuit 44 detects a burst error from information at the time of reproduction by the data reproduction circuit 32. As a method of detecting a burst error, for example, a method of monitoring the envelope of a reproduced signal is employed.

FIG. 2 shows a circuit configuration example of a burst error detection circuit in a digital VTR reproduction system. In this case, the output of the reproducing head is input to the input terminal 30, and the output of the reproducing amplifier 50 in the data reproducing circuit 32 is
Supplied to In the burst detection circuit 44, the detection circuit 52 performs envelope detection on the output of the reproduction amplifier, and the comparison circuit 54 compares the detection output of the detection circuit 52 with a predetermined threshold voltage 56. The output of the comparison circuit 54 becomes a burst detection signal which is the output of the burst detection circuit 44. The configuration shown in FIG. 2 utilizes the fact that when the output level of the reproducing head decreases, the probability that the data reproducing circuit 32 does not reproduce data accurately increases, and errors in the reproduced data become extremely large. .

Returning to FIG. 1, the burst error detection circuit 44 detects a burst error as described above and outputs a burst error detection signal. This burst error detection signal is written to the burst memory 46 at the address corresponding to the corresponding code.

The error position and error pattern calculation circuit 38 reads the syndrome written in the syndrome memory 36 and the burst error detection signal of the burst memory 46, and performs decoding calculation of an error correction code. Here, if the syndromes of the corresponding code are all 0, it is determined that there is no error, and the processing of the code ends. However, when all the syndromes are not 0, that is, when there are errors, and when it is determined that the errors can be corrected from these syndromes, the circuit 38 calculates an error position and an error pattern, and uses the result to calculate the error position and the error pattern. Correct the data in the data memory 20. At this time, referring to the burst memory 46, if there is a burst error with the corresponding code, the data memory 40
The correction operation of the data is prohibited, and the following processing is performed when the error cannot be corrected.

If it is determined that error correction is impossible, the data of the corresponding code in the data memory 40 is left as it is, and a process of newly writing a correction flag indicating that an error is included in the data memory 40 is performed.

After the above-described processing, uncorrectable data is corrected by the data correction circuit 48 for the data for which the correction flag is set. For example, in the case of image data, correction is performed by interpolation using data of peripheral pixels. After this process,
Data in the memory 40 is output from the output terminal 42.

[Effects of the Invention] As can be easily understood from the above description, according to the present invention, the probability of erroneous correction due to a burst error or the like can be reduced. For example, when dealing with data that can perform interpolation processing effectively, such as image data,
This has the effect of minimizing the degradation of the image quality of the reproduced image.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a circuit configuration of a burst error detection circuit 44 shown in FIG. 1, and FIG. 3 is a block diagram showing a configuration of a conventional example. 30: input terminal, 32: data reproduction circuit, 34: syndrome calculation circuit, 36: syndrome memory, 38: error position and error pattern calculation circuit, 40: data memory, 42: output terminal, 44: burst error detection Circuit, 46: Burst memory,
47: Data correction circuit

Claims (1)

(57) [Claims] (1) From input data obtained from a reproducing head,
Syndrome calculation means for performing syndrome calculation for error correction detection, syndrome memory means for storing the calculation result of the syndrome calculation means in association with each error correction code, and envelope detection of the output signal of the reproduction head. Burst error detection means for detecting a burst error based on the detection output, burst memory means for storing the detection result of the burst error detection means in association with each error correction code, and the syndrome memory Error correction means for calculating the error correction code from the syndrome of each error correction code stored in the means and correcting errors in the input data, and reading out each error correction code from the burst memory means. If the detected result indicates a burst error, correct the code. Error detecting and correcting circuit, characterized in that prohibiting correction by the error correcting unit even when it is determined that possible.