JPH09259546A - Error correction system using vanishing flag - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve error correction capability by vanishing correction. SOLUTION: A data is decoded containing a data part and a parity part (ECC) which are modulated by a 2-7 modulation rule to be interleaved (ST12) and the data decoded is deinterleaved (ST14) to generate a matrix formed by a set of a plurality of data trains containing the data part and the parity part. Then, when specified vanishing flag conditions are satisfied (ST24 yes), a vanishing flag is set for each of the data trains of the matrix (SET16). The set vanishing flags are used under specified vanishing flag applying conditions to perform an error correction of the data within the matrix (ST28).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving the error correction capability of data retrieved from a mass storage medium such as an optical disc.

[0002]

2. Description of the Related Art A raw analog signal reproduced from, for example, an optical disk is converted into a binary digital signal of "1" or "0". This operation is called binarization. As the binarization method, a method using a slice level and a method using a signal obtained by differentiating a reproduction signal are known.

A binarized digital signal is a PLL (Phas
e Locked Loop) circuit, and a data sequence synchronized with the recovered clock is obtained from this circuit. This data series is called a channel data series. The channel data series of "1" and "0" obtained through the PLL circuit after binarization is, for example, a [2-7] -modulated code series.

[2-7] modulation means RLL (Run Length)
Limited) code, which is called [2-7] modulation because the minimum run is "2" and the maximum run is "7". A run generally means a continuous or continuous bit length of the same bit (“0” or “1”), but here, unless otherwise specified, the number of continuous bits of “0” is called a run. In the [2-7] modulation, there is no continuous "1" and the number of continuous bits of "0" is "2" or more and "7" or less. Therefore, the RLL code has a finite maximum inversion interval.

The data series (user data series) to be recorded by the user of the optical disk drive device may have a large number of "1" s or "0" s continuous, but by applying the [2-7] modulation, it is inevitable A code in which "1" is generated within a certain period is obtained. The PLL circuit performs phase comparison from the timing of transition of the binary signal (binarized signal) from "0" to "1" or "1" to "0".
[2-7] By performing the modulation, the phase comparison interval is always within a certain period.

The channel data sequence is input to a demodulator and inversely converted into a user data sequence. The user data sequence is recorded on the optical disc in units called sectors.
The sector size is "512 bytes""1kbyte"
There are "2k bytes" and so on.

A header portion formed of embossed pits, user data recorded by irradiating laser light during data recording, VFO, sector number, synchronization code, CRC code, ECC code, etc. are added to this sector. Then, [2-7] modulation is performed, and information is recorded by, for example, mark-to-mark recording.

The synchronization code is, for example, user data "1".
It is a special data series that is added "1 byte" to "5 bytes" and corrects the bit shift etc. by this synchronization code to prevent the error propagation. The CRC code has an error in the read user data. It is used for the purpose of determining whether or not it is present. For example, a "4 byte" CRC code is added to "512 byte" user data.

The ECC code is a code for detecting an error position and correcting an error. For example, an ECC of "80 bytes" for user data of "512 bytes".
A code is added. The sector number is recorded in a portion called a pointer area, and, for example, "4 bytes" sector number data is added to "512 bytes" user data.

User data is input to the optical disk drive device from an information input terminal or the like via a SCSI bus or the like. SCSI (Small Computer System Interfac
e) is a peripheral interface for a small computer, which is used for optical disk drive, CD-ROM, hard disk, image scanner, etc. The obtained user data is stored in a memory such as DRAM in sector units.

User data is interleaved to convert burst errors into random errors or short byte errors. For example, when the user data per “1” sector is “512 bytes”, the pointer (4
Byte), CRC (4 bytes), ECC (80 bytes)
The data of “600 bytes” to which is added is arranged in a (120 × 5) matrix.

This matrix is column 5 of "120 bytes"
Each column consists of "104 bytes" data (any of user data, pointer, or CRC) and "16 bytes" ECC code. For this ECC code, for example, a so-called LDC (Long Distant Code) is used.

[0013]

The LDC is a code having a long minimum distance and a high correction capability, and is one of the standardization plans for optical disks. In this case, the LDC performs error detection and error correction in one column consisting of "120 bytes".
If there is no loss, correction up to "8 bytes" is possible.

Here, "erasure" means "an error in which an error position is known but an error pattern (numerical value) is not known". If the loss can be detected accurately,
It is known that an error correction of up to "16 bytes" is possible with a single row of "120 bytes". But,
In the past, erasure was not detected, and correction was performed up to "8 bytes" per column assuming no erasure. This method can only correct errors up to "40 bytes" (8 bytes x 5 columns) per "1" sector. An object of the present invention is to provide an error correction system having an improved error correction capability by detecting the erasure.

[0015]

In order to achieve the above object, the error correction system of the present invention has a predetermined rule (2
A demodulation means (44.ST12) for demodulating the data including the interleaved data part and the parity part, which are modulated according to -7 modulation rule); and the demodulation means (44).
Deinterleaving (ST14) the data demodulated in step S14 to generate a matrix formed of a set of a plurality of data strings including a data part and a parity part (ECC); Disappearance flag generation means (CPU 30 + firmware) that sets a disappearance flag for each data column of the matrix when the flag generation condition is satisfied (ST24: Yes); and the disappearance flag set by the disappearance flag generation means (30). Error correction means (32.ST) for correcting an error in the data in the matrix under the condition that a predetermined erasure flag is used.
28) and.

Here, the data demodulated by the demodulation means (44) includes a resync code (RS), and the erasure flag generation means (30) is the resync code (RS).
Can be configured to set the disappearance flag in response to the fact that is not detected.

Further, the data demodulated by the demodulation means (44) includes a plurality of resync codes (RS) at fixed time intervals, and the disappearance flag generation means (30) outputs the undetected resync code (RS). The disappearance flag may be set in response to the correction (based on the detected resync code).

The erasure flag generating means (30) sets the erasure flag when the data demodulated by the demodulation means (44) includes an error bit exceeding a predetermined number (threshold value). can do. (For example, when the threshold value is 3, the flag is not set when the number of error bits is 2 or less, and the flag is set when the number of error bits is 3 or more.) Further, the erasure flag use condition is that the erasure flag generation means (30 ), It is possible to determine whether the number of disappearance flags set by (4) is greater than or equal to a predetermined value (for example, eight or more) for each data column of the matrix.

If the number of disappearance flags set by the disappearance flag generating means (30) is less than or equal to the predetermined value (for example, 8), all the set disappearance flags are used and the disappearance flag generating means ( If the number of disappearance flags set by 30) exceeds the predetermined value (8),
It is possible to use the number corresponding to the predetermined value of the first one of the disappearance flags. (In the case of the erasure flag threshold = 8, if the erasure flag is 8 or less, all the flags of 8 or less are used for erasure correction. 8 flags are used for erasure correction.) In the present invention, since the flag indicating erasure is used for error correction, the correction capability is improved compared to the case where the erasure flag is not used.

[0020]

DETAILED DESCRIPTION OF THE INVENTION An error correction system using an erasure flag according to an embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, an optical disc 1 as an information storage medium is rotated by a motor 3 at a constant speed, for example. This motor 3 has a motor control circuit 4
Is controlled by Recording of information on optical disc 1
The reproduction is performed by the optical head 5. Optical head 5
Is fixed to a drive coil 7 that constitutes a movable portion of the linear motor 6, and the drive coil 7 is connected to a linear motor control circuit 8.

A speed detector 9 is connected to the linear motor control circuit 8 and the optical head 5 detected by the speed detector 9 is connected.
Is sent to the linear motor control circuit 8. A permanent magnet (not shown) is provided on the fixed portion of the linear motor 6, and the drive coil 7 is excited by the linear motor control circuit 8 to cause the optical head 5 to move to the optical disk 1.
Is moved in the radial direction.

The optical head 5 is provided with an objective lens 10 supported by a wire or a leaf spring (not shown). The objective lens 10 can be moved in the focusing direction (optical axis direction of the lens) by driving the driving coil 11, and the tracking direction (direction orthogonal to the optical axis of the lens) by driving the driving coil 12. It is also possible to move to.

A laser light beam is emitted from the semiconductor laser oscillator 9 under the drive control of the laser control circuit 13.
The laser control circuit 13 includes a modulation circuit 14 and a laser drive circuit 15, and operates in synchronization with the recording clock signal supplied from the PLL circuit 16. The modulation circuit 14 modulates the recording data supplied from the error correction circuit 32 into a signal suitable for recording, that is, [2-7] modulation data. The laser drive circuit 15 drives a semiconductor laser oscillator (or an argon neon laser oscillator) 19 according to the [2-7] modulation data from the modulation circuit 14.

During recording, the PLL circuit 16 divides the basic clock signal from the crystal oscillator into a frequency corresponding to the recording position on the optical disc 1 to generate a recording clock signal. During reproduction, the PLL circuit 16 also generates a reproduction clock signal corresponding to the reproduced synchronization code, and further detects a frequency abnormality of the reproduction clock signal.

This frequency abnormality is detected by whether or not the frequency of the reproduction clock signal is within a predetermined frequency range corresponding to the recording position of the data to be reproduced on the optical disc 1. Further, the PLL circuit 16 selectively outputs a clock signal for recording or reproduction in accordance with a control signal from the CPU 30 and a signal from the counting section 47 of the data reproducing circuit 18.

The laser light beam emitted from the semiconductor laser oscillator 19 is irradiated onto the optical disc 1 through the collimator lens 20, the half prism 21 and the objective lens 10. The reflected light from the optical disc 1
0, a half prism 21, a condenser lens 22, and a cylindrical lens 23, and are guided to a photodetector 24.

The photodetector 24 is a 4-division photodetector cell 24.
a, 24b, 24c, and 24d. The output signal of the photodetector cell 24a is supplied to one end of the adder 26a via the amplifier 25a. The output signal of the light detection cell 24b is supplied to one end of an adder 26b via an amplifier 25b. The output signal of the light detection cell 24c is
It is supplied to the other end of the adder 26a via 5c. The output signal of the light detection cell 24d is supplied to the other end of the adder 26b via the amplifier 25d.

Further, the output signal of the photodetector cell 24a is
The signal is supplied to one end of the adder 26c via the amplifier 25a. The output signal of the light detection cell 24b is supplied to one end of an adder 26d via an amplifier 25b. Photodetection cell 24
The output signal of c is supplied to the other end of the adder 26d via the amplifier 25c. The output signal of the light detection cell 24d is supplied to the other end of the adder 26c via the amplifier 25d.

The output signal of the adder 26a is a differential amplifier OP
2, and the output signal of the adder 26b is supplied to the non-inverting input terminal of the differential amplifier OP. The differential amplifier OP2 outputs a signal related to the focus point according to the difference between the two output signals of the adders 26a and 26b. This output is supplied to the focusing control circuit 27. The output signal of the focusing control circuit 27 is supplied to the focusing drive coil 12. Thus, the laser light beam is controlled to be always just focused on the optical disc 1.

The output signal of the adder 26c is a differential amplifier OP.
1, and the output signal of the adder 26d is supplied to the non-inverting input terminal of the differential amplifier OP1. The differential amplifier OP1 outputs a track difference signal according to the difference between the two output signals of the adders 26c and 26d. This output is supplied to the tracking control circuit 28. The tracking control circuit 28 creates a track drive signal according to the track difference signal from the differential amplifier OP1.

The track drive signal output from the tracking control circuit 28 is applied to the drive coil 1 in the tracking direction.
1 is supplied. Further, a track difference signal used in the tracking control circuit 28 is supplied to the linear motor control circuit 8.

By performing the above-mentioned focusing and tracking, each photodetecting cell 24a of the photodetector 24,
... the sum signal of the output signals of 24d,
The change in the reflectance from the pits (recording information) formed on the track is reflected in the output signal of the adder 26e, which is the addition of the two output signals c and 26d. This signal is supplied to the data reproducing circuit 18. Data reproduction circuit 18
Reproduces recorded data based on a reproduction clock signal from the PLL circuit 16.

The data reproducing circuit 18 also includes an adder 26.
The sector mark in the preformatted data is detected based on the output signal of e and the reproduction clock signal from the PLL circuit 16, and based on the binarized signal and the reproduction clock signal supplied from the PLL circuit 16. Two
The track number and sector number as address information are reproduced from the digitized signal.

The reproduced data of the data reproducing circuit 18 is the bus 2
9 is supplied to the error correction circuit 32. The error correction circuit 32 outputs an error correction code (EC
C) to correct the error, or add an error correction code (ECC) to the recording data supplied from the interface circuit 35 and output it to the memory 2.

The reproduced data error-corrected by the error correction circuit 32 is the bus 29 and the interface circuit 3.
5 is supplied to a storage medium control device 36 as an external device. The recording data emitted from the storage medium control device 36 is supplied to the error correction circuit 32 via the interface circuit 35 and the bus 29.

When the objective lens 10 is being moved by the tracking control circuit 28, the linear motor control circuit 8 causes the objective lens 10 to be positioned near the center position within the optical head 5, that is, the optical head 5.
Is moved.

The D / A converter 31 controls the focusing control circuit 27, the tracking control circuit 28, the linear motor control circuit 8 and the CPU 30 which controls the entire optical disk device.
Used for exchanging information with

The motor control circuit 4, the linear motor control circuit 8, the laser control circuit 15, the PLL circuit 16, the data reproduction circuit 18, the focusing control circuit 27, the tracking control circuit 28, the error correction circuit 32, etc. are connected via a bus 29. It is controlled by the CPU 30. The CPU 30 performs a predetermined operation by a program (system software or firmware) recorded in the memory 2.

Here, an example of the sector format in the optical disc 1 is shown in FIG. The user data per sector is "512 bytes". The numbers in the figure represent the number of (data) bytes. In the following description,
When simply referred to as bytes, it represents the number of user bytes, and the channel bits are the same as 16 bits.

VFO1 (Variable Frequency Oscillato
r) is an area for pulling in the PLL, and is a channel bit in which a sequence of "010 ..." Is recorded for "12" bytes (192 bits in the channel bit).

AS is an abbreviation for (Address Sync), which is a "1" byte synchronization code indicating where the sector address starts, and may also be referred to as AM (Address Mark). As the pattern, a special pattern that does not appear in the data part "0100100000000100" is used.

ID1 (Identifier 1) to ID3 (Identi
fier 3) is an area showing “5” bytes of address information. The contents of the "5" bytes are "3" bytes for the sector address (including the ID number) and "2" bytes for the CRC.

The sector address has "22" bits before modulation, the ID number is "2" user bits, and the total is "24" user bits = "3" bytes. Therefore, in this format, it is possible to take "4", "194", and "304" values as the sector address.

The ID number is, for example, "1" in the case of ID1 and is a number indicating the number of the three times overwriting. Since this ID can take values from "1" to "3", "2" bits are required.

CRC (Cyclic Redundancy Check) is
The error detection code for the "3" bytes of the sector address (including the ID number) is "2" bytes. With this error detection code, it is possible to detect the presence or absence of an error in the read ID (“5” bytes).

Similar to VFO1, VFO2 also records the same pattern for locking the PLL for "8" bytes. PA (Postambles) is an area of "1" bytes or "6" bytes called a postamble and has ID3.
Or it is located after the data section. This is an area provided so that word delimiters always occur until the end when modulated to a [2-7] modulation code which is a variable word length modulation method. PA
Is "16" to "32" in the area without GAP (Gap)
Takes randomly one of the channel bit lengths.

ALPC (Auto Laser Power Control)
Has a length of "4" bytes, and the pattern "33", "33", "30", "1A" is recorded in hexadecimal notation. Although VFO3 is also an area for PLL lock, it is also an area for the purpose of synchronizing byte boundaries by inserting a synchronization code in the same pattern.

DS (Data Sync) is DM (Data Mark)
) Is also called, and is a synchronization code for synchronizing byte boundaries for the data portion that follows. DATA (Data
field) is called a data part, and is a user data, a resync code, an error correction code (ECC; Erro).
r Correction Code), CRC, pointer area, etc. These data are arranged in a matrix in a predetermined order and subjected to [2-7] modulation, and then recorded on the optical disc 1.

The BUF (Buffer) is an area for absorbing disk rotation fluctuations and the like and does not record anything. FIG. 1 shows essential parts (41 to 47) of the data reproducing circuit 18 in the information processing device (optical disk device) configured as described above.

As shown in FIG. 1, the signal reproduced from the optical disc 1 is supplied to a binarization circuit 41, where it is binarized with a constant threshold level TH as a reference.
The output signal of the binarization circuit 41 is supplied to the PLL circuit 16 and converted into a data series synchronized with the reproduction clock signal of the optical disk reproduction means.

The output signal of the PLL circuit 16 is supplied to the 8-bit shift register 42, where it is converted into an 8-bit parallel signal. This signal is the pattern detection circuit 4
3, demodulation ROM 44, and error flag generation circuit 45
Is supplied to.

The pattern detection circuit 43 detects a resync code, which is a synchronization signal, of the signals from the 8-bit shift register 42. The demodulation ROM 44 demodulates the signal from the 8-bit shift register 42 based on, for example, the [2-7] code conversion rule. The demodulated signal is supplied to the effective length counter 46 and the parallel / serial (P / S) conversion circuit 47. The effective length counter 46 is for knowing the word boundary of the variable length block code by [2-7] code conversion.

The parallel / serial conversion circuit 47 converts the output signal of the 8-bit shift register 42 into the effective length counter 4
According to the output of 6, each word (word; parallel data) is converted into a serial signal and output. This serial output signal is supplied to the memory 2 and stored therein.

In the memory 2, under the control of the CPU 30,
Each demodulated data and each error correction code are arranged and stored in a matrix. In the array, a plurality of interleaved columns each including a predetermined number of data and a predetermined number of error correction codes (ECC) are formed.

The format of each data and each error correction code in the memory 2 is illustrated in FIG. 4 (512 byte format) or FIG. 5 (2 kbyte format).

In FIG. 4, DS1 to DS3 are data sync codes, which are not shown in the data section. "1" to "512" in FIG. 4 represent the "1" to "512" bytes of the user data. "P1.
1 ”to“ P1.4 ”are pointer areas (4 bytes),
The self-address and the like are recorded. Similarly, "1" in FIG.
~ "2048" are user data "1" to "204"
It represents the 8th byte and represents "P1.1" to "P1.
4 "represents a pointer area.

In FIG. 4, "CRC1" to "CRC"
4 "(4 bytes) enables error detection of (user data" 512 "bytes + pointer" 4 "bytes).
"E1.1" to "E5.16" are error correction codes, which are added by "80" bytes. With this error correction code, error correction can be performed in the vertical direction of FIG. Vertical rows are called interleave,
There are five columns in the vertical direction, and the number is "0" for each.
It is referred to as an interleave "0" by adding "4".

One interleave includes "104" bytes of user data, pointer data, CRC and "1".
It consists of 6 ”bytes of error correction code, and is“ 1 ”in total.
It is 20 "bytes.

The error detection and error correction capability by the error correction code is assigned "8" bytes for one interleave when there is no loss and "16" bytes for one interleave when there is a loss.

Here, "disappearance" refers to an error whose position is known but whose error pattern (numerical value) is not known. Therefore, the case of the above-mentioned disappearance means the case where only the position is known for all the errors of "16" bytes.

On the other hand, the case of no erasure means that the error position and the error pattern are not known for all the errors of "8" bytes. The error position and error pattern are each considered as one unknown, and this is "16".
The following can be corrected.

For example, the error "12" without disappearance for "4" bytes and the disappearance for "8" bytes.
The bytes are correctable. This is because {(position + pattern) × 4 = 8} for “4” bytes and {(pattern) × 8 = 8} for “8” bytes, and the total number of unknowns is “16”.

In the example of FIG. 4, the resync code "RS" is set for each "15" byte of each data and error correction code.
1 ”to“ RS39 ”exist. In the example of FIG.
Resync codes "RS1" to "RS73" exist for each "30" bytes of each data and error correction code.

The error flag generating circuit 45 of FIG. 1 has the following functional blocks [1] to [4] (FIG. 4).
Format). These functional blocks can be implemented by dedicated hardware or device firmware (system software).

[1] Of the signals from the 8-bit shift register 42, data that does not match the code conversion rule (for example, [2-7] modulation rule) of the demodulation ROM 44 is detected, and the same data as the detected data exists. A first designation block 451 for issuing an error flag signal for designating the interleave in the memory 2. This first designated block 45
1 includes a demodulation ROM that is the same as the demodulation ROM 44 in order to detect data that does not match the code conversion rule.

[2] The second designated block which issues an error flag signal for designating all interleaves in the memory 2 when the number of interleaves designated by the first designated block 451 is a predetermined value, for example, "3" or more. 45
2.

[3] Abnormality in time interval of each resync code detected by the pattern detection circuit 43 (missing bit etc.)
Anomaly detection block 454 to detect if there is. [4] When the abnormality detection block 454 detects an abnormality,
Third designation block 4 which issues an error flag signal for designating data in the memory 2 corresponding to the abnormal period
53.

These error flag signals are supplied to the error correction circuit 32. The error correction circuit 32 has the following functional blocks [1] and [2]. These functional blocks can also be implemented by dedicated hardware or device firmware (system software).

[1] Of the data in the memory 2, the first designated block 451 or the second designated block 452.
A first correction block 321 that corrects the content of the interleaved data specified by the error flag signal from the same based on the error correction code of the same interleave.

[2] Of the data in the memory 2, the contents of the data designated by the error flag signal of the third designation block 453 are corrected based on the interleaved error correction code in which the data exists. Correction block 322.

Next, the operation of the configuration shown in FIGS. 1 and 2 will be described. The reproduction signal generated from the reproduction signal generator of FIG.
It is binarized by the binarization circuit 41. This binary signal is P
In the LL circuit 16, it is converted into a data series synchronized with the reproduction clock signal. The output of this PLL circuit is 8
It is converted into a parallel signal by the bit shift register 42,
It is supplied to the pattern detection circuit 43, the demodulation ROM 44, and the error flag generation circuit 45.

The pattern detection circuit 43 detects a resync code in the signal from the 8-bit shift register 42. Then, this detection signal is supplied to the error flag generation circuit 45.

In the demodulation ROM 44, the signal from the 8-bit shift register 42 is demodulated based on the [2-7] code conversion rule. This demodulated signal is converted into a serial signal by the P / S conversion circuit 47 and supplied to the memory 2.

In the memory 2, each data to be demodulated and each error correction code are arranged and stored in a matrix form, and an interleaved column consisting of a predetermined number of data and a predetermined number of error correction codes (ECC) in the array. Are formed in plural.

In the error flag generating circuit 45, of the signals from the 8-bit shift register 42, the demodulation ROM 44
The data that does not match the [2-7] code conversion rule of is detected. An error flag signal for designating the interleave in the memory 2 in which the same data as the detected data exists is issued from the error flag generation circuit 45.

For example, in FIG. 4, when error data that does not match the [2-7] code conversion rule exists in the interleave "3", an error occurs in the interleave "3" as shown in FIG. The flag "1" is set.

In the error correction circuit 32, the interleave "3" is designated based on the error flag signal from the error flag generation circuit 45, and the data content (pattern) of the interleave "3" is the same interleave "3". It is corrected based on the error correction code.

By thus designating the error position of the data by the error flag generation circuit 45, all the error correction codes for "16" bytes in each interleave are used only for the content (pattern) correction. be able to. So-called erasure correction is possible.

By this erasure correction, the error correction capability is improved without impairing the effect of high density recording of the optical disk device and without prolonging the time required for correction as in the case of multiplexing error correction codes. Can be achieved.

Incidentally, for example, the attachment of dust to the optical disc 1 not only damages the data for "1" bytes, but also often adversely affects the data before and after that. Therefore, in a situation where an error flag is set in three or more interleaves, for example, in a situation in which the error flag “1” is set in the interleaves “1” “3” “4” as shown in FIG. Similarly for "0" and "2", all interleaves "0" and "1" are judged based on the judgment (estimation) that the data may be damaged.
Error flags (actual error flags) are set for "2", "3", and "4".

In this case, all interleaves "0"
The data content (pattern) in "1", "2", "3", and "4" is corrected based on the error correction code of each interleave.

On the other hand, as an error that cannot be detected by the [2-7] code conversion rule, there is an error such as a missing bit due to a defect of the optical disc 1. If this error occurs, the data series will be completely different from the original one.

Therefore, in the configuration of FIG. 1, the pattern detection circuit 43 detects the resync codes “RS1” to “RS39” existing for each “15” bytes of each data and error correction code of FIG. 4 and the detection thereof. The error flag generation circuit 45 counts the time interval of each resync code.

For example, when the time interval from the detection of the resync code "RS1" to the detection of the resync code "RS2" is smaller than the reference value, it is determined that the two resync codes are abnormal. 4C, an error flag "1" is set for the data between the resync codes "RS1" and "RS2". This error flag is illustrated by the "*" mark (disappearance flag) in FIG. 5 (2 kbyte format).

In the case of FIG. 4, the contents (patterns) of all the data between "RS1" and "RS2" are corrected based on the error correction code of each interleave. As described above, since it is possible to correct an error in the data series, it is possible to further improve the error correction capability together with the correction based on the [2-7] code conversion rule.

FIG. 6 is a flow chart for explaining the operation (firmware processing) of the error correction system according to the embodiment of the present invention. The process of this flowchart is executed by the CPU 30 of FIG. 2, for example.

Playback signal (analog) from optical disc 1
Is input to the binarization circuit 41 of FIG. 1 (step ST
10), this signal is subjected to a predetermined process (which has already been described with reference to FIG. 1) by the circuits 41 to 42, and is demodulated in the ROM 44 [2-7] (step ST12).

The demodulated data is subjected to predetermined processing (described with reference to FIG. 1) by the circuits 46 to 47, deinterleaved (step ST14), and stored in the memory 2. A predetermined amount of data stored in the memory 2 forms a matrix composed of a data section and an ECC section as shown in FIG. 4 or 5 (step ST16).

On the other hand, the resync code is detected by the pattern detection circuit 43 from the binarized reproduction signal before being demodulated by the ROM 44, and the error flag generating circuit 45 detects a data error and a synchronization code (resync code) in the binarized reproduction signal. , Data sync code) is checked (step ST18).

If there is no error in both the data and the synchronization code (YES in step ST20), the data in the matrix is sequentially output from the memory 2 without error correction (step ST30).

When there is an error in the data and / or the synchronization code (NO in step ST20), the generation condition of the disappearance flag is checked (step ST22). Here, there are the following three conditions for generating the erasure flag: <1> When a pattern deviating from the [2-7] modulation (from the shift register 42 in FIG. 1) is generated, the erasure flag is generated.

<2> When the resync cannot be detected (by the abnormality detection block 454 in FIG. 1), a loss flag is generated. <3> When the bit correction is performed by the resync, it is considered that the previous and previous disappearance positions (three columns before) are erased, and an erase flag is set in those columns. If there is no erasure position before that, the erasure flag is set only in the previous column.

When the erasure flag generation condition is not satisfied (NO in step ST24), normal error correction processing is performed (step ST26). When the erasure flag generation condition is satisfied (YES in step ST24), the erasure correction process is performed using the generated erasure flag under a predetermined erasure flag use condition (step ST28).
Here, the conditions for using the predetermined erasure flag are as follows: <4> For example, in the error correction of the non-product code in FIG. 7, the number of error bits arranged in the data input direction is a predetermined threshold value. If (for example, 3) or more, an erasure flag is set in the column to perform erasure correction.

<5> For example, in the case of error correction of the product code in FIG. 8, if the number of erasure flags arranged in the data input direction is equal to or less than a predetermined threshold value (for example, 8), erasure correction is performed using all erasure flags. To do. When the number of erasure flags arranged in the data input direction (for example, 16) exceeds a predetermined threshold value (8), erasure correction is performed using only the first 8 flags.

<6> For example, in the error correction of the product code of FIG. 8, when the matrix data is divided into some along the data input direction and the error is corrected, erasure correction is performed.

The disappearance flag use conditions <4 to 6> can be changed corresponding to the disappearance flag generation conditions <1 to 3>. How to change is determined by the firmware that executes the processing of FIG. For example, the threshold value of the disappearance flag use condition <4> is set to “3” for the disappearance flag generation condition <1>, and the disappearance flag use condition <4> for the disappearance flag generation condition <2>. Threshold at
It is possible to set it to 4 ". This makes it possible to flexibly change the correction capability of erasure correction according to the content of the error (depending on the writing of the firmware or the system software).

FIG. 9 exemplifies a matrix in the case where an error correction system according to an embodiment of the present invention is applied to error correction of a non-product code, and an uncorrectable error occurs without erasure correction. ing.

Since the 16-byte ECC shown in FIG. 9 can correct only errors up to 8 bytes, the 10-byte error correction shown in FIG. 9 cannot be performed at step ST26 shown in FIG. 6, for example. However, the error shown in FIG.
If the firmware is written so that the condition (Yes) in 4 is satisfied, error correction up to 16 bytes is possible by performing erasure correction using the erasure flag as shown in FIG. . That is, the erasure correction (step ST28) of FIG. 6 is performed, and the correction result as shown in FIG. 11 can be obtained.

FIG. 12 shows erasure correction (first horizontal error correction) when the error correction system according to the embodiment of the present invention is applied to error correction of a product code.
Exemplifies a matrix when a correctable error occurs. Further, FIG. 13 shows that after the horizontal error is corrected by the erasure correction using the erasure flag of FIG.
It is a figure explaining the 2nd error correction (longitudinal direction) by the data after correction.

That is, if the error correction in the horizontal direction of FIG. 12 is performed and the error correction in the vertical direction of FIG. 13 is performed after the erasure correction, even if the number of bits constituting the ECC1 section is small (4 in this case). (Byte) A relatively high correction capability is obtained. Then, the corrected data is further corrected by the ECC2 section, so that the final correction capability is significantly improved.

In the above embodiment, the case where the [2-7] code conversion is performed has been described as an example, but it can be similarly performed when other code conversion, for example, the [1-7] code conversion is performed. is there. In addition, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention.

[0102]

By performing erasure correction based on a combination of predetermined conditions (erasure estimation condition and erasure flag generation condition), for example, without erasure correction, only one line consisting of "120 bytes" can be used to correct errors up to "8 bytes". What could not be done is "16 bytes" in a row of "120 bytes".
Error correction up to "byte" is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of an error correction system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of an optical disc device to which the error correction system of FIG. 1 is applied.

FIG. 3 is a diagram for explaining a sector format of an optical disc which can be applied to the optical disc device of FIG.

4 is a diagram illustrating a matrix of data and an ECC code (in the case of one sector 512-byte format) used in the error correction system of FIG.

5 is a diagram showing an example of a matrix of data and an ECC code (in the case of 1 sector 2 kbyte format) used in the error correction system of FIG.

FIG. 6 is a flowchart diagram illustrating an operation (firmware processing) of the error correction system according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating a case where the error correction system according to the embodiment of the present invention is applied to error correction of a non-product code.

FIG. 8 is a diagram illustrating a case where the error correction system according to the embodiment of the present invention is applied to error correction of a product code.

FIG. 9 is a diagram exemplifying a matrix when an error that cannot be corrected occurs without erasure correction in the case where the error correction system according to the embodiment of the present invention is applied to error correction of a non-product code.

10 is a diagram exemplifying a case where a disappearance flag is set in the matrix of FIG.

11 is a diagram showing a matrix after the error of FIG. 9 is corrected by erasure correction using the erasure flag of FIG.

FIG. 12 shows a case where a correctable error occurs due to erasure correction (first horizontal error correction) when the error correction system according to the embodiment of the present invention is applied to error correction of a product code. The figure which illustrates a matrix.

FIG. 13 is a diagram for explaining the second error correction (vertical direction) by the corrected data after the horizontal error is corrected by the erasure correction using the erasure flag of FIG. 12;

[Explanation of symbols]

2 ... Memory 16 ... PLL circuit 18 ... Data reproduction circuit 30 ... CPU (disappearance correction firmware processing) 32 ... Error correction circuit 321 ... First correction block 322 ... Second correction block 41 ... Binarization circuit 42 ... Shift register 43 ... pattern detection circuit (resync code detection) 44 ... demodulation ROM (2-7 demodulation) 45 ... error flag generation circuit (disappearance flag processing) 46 ... effective length counter 47 ... P / S (parallel / serial) conversion circuit 451 ... 1 designated block (error flag generation instruction) 452 ... 2nd designated block (error flag generation instruction) 453 ... 3rd designated block (error flag generation instruction) 454 ... Abnormality detection block (resync code bit missing detection)

Claims (6)

[Claims] 1. A demodulation means for demodulating data which is modulated according to a predetermined rule and includes an interleaved data part and a parity part; de-interleaved data demodulated by the demodulation means, and a data part and a parity part. Generating means for generating a matrix formed of a set of a plurality of data strings including; an erasing flag generating means for setting an erasing flag for each data string of the matrix when a predetermined erasing flag generating condition is satisfied; An error correction system, comprising: an error correction means for correcting an error in data in the matrix by using an erasure flag set by the erasure flag generation means under a predetermined erasure flag use condition. 2. The data demodulated by the demodulation means includes a resync code, and the erasure flag generation means is configured to set the erasure flag in response to the fact that the resync code is not detected. The error correction system according to claim 1, wherein the error correction system is provided. 3. The data demodulated by the demodulation means includes a plurality of resync codes at fixed time intervals, and the erasure flag generation means sets the erasure flag in response to correction of the undetected resync code. The error correction system according to claim 1, wherein the error correction system is configured to stand upright. 4. The erasure flag generation means is configured to set the erasure flag when the data demodulated by the demodulation means includes more than a predetermined number of error bits. The error correction system described in. 5. The erasure flag use condition is configured to be determined by whether or not the number of erasure flags set by the erasure flag generating means is a predetermined value or more for each data column of the matrix. The error correction system according to any one of claims 1 to 4, which is characterized. 6. If the number of disappearance flags set by the disappearance flag generating means is less than or equal to the predetermined value, all the disappearance flags set up are used, and the number of disappearance flags set by the disappearance flag generating means is The error correction system according to claim 5, wherein when the number exceeds the predetermined value, the number corresponding to the predetermined value of the first one of the erasure flags is used.