JP3355633B2 - Data transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates to a method of transmitting data by inserting a resynchronization signal for each predetermined data unit in order to prevent error propagation.

[0002]

2. Description of the Related Art FIG. 9 shows that a servo system is a CS (continuous servo) system, which is 5 inches, 1024 bytes / byte.
The MO indicates the sector format of the sector.

[0003] In the figure, "SM" is a sector mark. The pattern is 5 bytes long and “1 ¹⁰ 0 ⁶ 1 ⁶ 0 ¹⁴ 1 ⁶ 0 ⁶
1 ⁶ 0 ⁶ 1 ¹⁰ 0 ² 1 ¹ 0 ² 1 ¹ 0 ² 1 ¹ 0 ¹ "where 1 ^a , 0 ^b
Are a channel bits "a" and "0"
Is repeated b times.

[0004] "VFO1" to "VFO3" are VFO sinks (PLLs). The pattern is a continuous pattern, as follows.

VFO1-010010010010... 0010 (12 bytes) VFO2-100100100100... 0010 (8 bytes) 000100100100... 0010 (8 bytes) VFO3-010010010010. "AM" is an address mark. The pattern is 2 bytes and is “0100100000000100”.

“ID1” to “ID3” are addresses, each having the same pattern. Two bytes as a track number and one byte as a sector number are recorded by (2, 7) modulation. Furthermore, for these, a 16-bit CRC is introduced, and (2,7)
Recorded by modulation. The generator polynomial is G (x) = x ¹⁶ + x ¹² + x ⁵ +1.

"PO" is a postamble. The area from the sector mark “SM” to the postamble “PO” is the preformat area.

[0008] Following this preformat area,
"TOF", "FLAG", "GAP", "ALPC"
Is arranged. “TOF” corresponds to a mirror surface without a groove. “FLAG” is a flag indicating that writing has been performed. The pattern to be set is “10
0 ”continues for 5 bytes. Before and after“ FLAG ”,
It is protected by a gap "GAP" of 3 bytes each. "A
“LPC” is an area for controlling laser power.

"SYNC" is a data field synchronization signal. The pattern is 3 bytes and "0100001001000010
00100010010001001000001001001000 ”.“ VFO
3 ".

"DATA FIELD" is a data field in which user data and the like are recorded, and is 1259 bytes. It is arranged following “SYNC”.

"BUFFER" is a margin for rotation jitter, is provided in 20 bytes, and is "DATA F".
IELD ".

Thus, one sector is constituted by a total of 1360 bytes from the sector mark "SM" to "BUFFER".

FIG. 10 shows an MO of 1024 bytes / sector.
3 shows a configuration of a data format of a disc.

"SB1" to "SB3" are synchronization signals of a data format recorded in "SYNC". "R
“S1” to “RS59” are resyncs, and are allocated every 20 bytes, that is, every two interleaves.

"D1" to "D1024" are user data (1024 bytes), and 10 bytes in the column direction.
They are arranged in the row direction in the order of bytes.

"P1,1" to "P3,4" are control data (12 bytes) in replacement processing and the like, and are arranged following user data. “C1” to “C4” are CR
C (4 bytes) and user data “D1” to “D
1024 ", control data" P1,1 "to" P3,4 "
Is an error detection code.

"E1,1" to "E10,16" are parity for error correction, and the generation direction of the parity is the Row direction. (120, 104, 17) Reed-Solomon code × 10 interleave is used.

By the way, in the above-mentioned CS system,
(2, 7) modulation is adopted as a modulation method. Since this modulation has a variable word length, it is necessary to determine word boundaries at the time of modulation and demodulation. However, there is an advantage that the conversion table is very small (7 types) and the hardware scale is small.

However, there is an error propagation in the (2, 7) modulation. Therefore, in order to eliminate the influence of the bit slip, in the CS system, resync is inserted at regular intervals as described above.

[0020]

However, even if the bit slip stops there due to resync, an error occurs in the predetermined unit section. Conventionally, there is no method for detecting this, which hinders improvement in data reliability.

Therefore, according to the present invention, an error is detected for each unit related to a resync unit, and the reliability of data is improved.

[0022]

SUMMARY OF THE INVENTION This invention relates to a data transmission method for transmitting a data sequence designated by the synchronizing signal, the data string, a separate re-synchronization signal to each predetermined data unit and the synchronization signal A predetermined data unit into which the resynchronization signal is inserted
Integer multiple or 1 / integer of
For each data unit divided , at least
It is characterized in adding Lud over data to detect errors in the chromatography data units.

[0023]

According to the present invention, for example, an error due to a bit slip can be detected for each unit associated with a predetermined data unit into which a resynchronization signal is inserted, and erasure information can be sent to a subsequent error correction processing stage to increase the number of correctable bytes. This makes it possible to greatly improve the reliability of data.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows an example in which the present invention is applied to a data format of 1024 bytes / sector, and portions corresponding to FIG. 10 are denoted by the same reference numerals.

The resync is inserted every 20 bytes, that is, every two interleaves, but in this example,
One byte error detection code or error correction code is added to each unit (illustrated by DC1 to DC60). For example, simple parity or CRC (Cyclic Redundanc)
y Check Code) is added. This results in insertion of resyncs RS1 to RS59 every 21 bytes.

The data format of the present embodiment is configured as described above, and the rest is configured similarly to the example of FIG.

In this example, since an error detection code or an error correction code is added for each resync unit,
An error can be detected for each unit. For this reason, an error due to a bit slip can be reliably detected, and erasure information can be sent to a subsequent error correction processing stage to increase the number of correction bytes, thereby greatly improving data reliability.

The (120, 104, 17) lead
From the viewpoint of the Solomon code × 10 interleave parity, erasure information at the same location can be obtained, so that the calculation can be shared in the error correction processing stage, and there is an advantage that the correction (decoding) processing is simplified.

Next, another embodiment of the present invention will be described with reference to FIG. The data format of this example is 10 bytes in the column direction and 12 bytes in the row direction.
It is composed of 4 bytes. The example of FIG. 2 differs from the example of FIG. 1 in that a one-byte error detection code or error correction code is inserted into the data format.

In the figure, "SB1" to "SB3" are synchronization signals. “RS1” to “RS61” are resyncs, and are allocated every 20 bytes, that is, every two interleaves. “DC1” to “DC27” are error detection codes or error correction codes, and one byte is added to every two units of resync, ie, 39 bytes.
For example, simple parity or CRC is added.

The 1-byte error detection code or error correction code is RowNo. 0-107 are arranged. As a result, Row No. The remainder of the portion from 0 to 107 is 1053 bytes, and as in the example of FIG.
0 bytes of user data and control data can be allocated.

Row No. In the part of -1 to -16,
(124,108,17) Reed-Solomon code × 10
Interleaved parity is allocated. The direction in which the parity is generated is the Row direction.

In this example, every two units of resync
That is, since a 1-byte error detection code or an error correction code is added to 39 bytes, an error can be detected for each unit. Therefore, similarly to the example of FIG. 1, an error due to a bit slip can be reliably detected, and erasure information can be sent to a subsequent error correction processing stage to increase the number of error correction bytes, thereby greatly improving data reliability. .

Further, from the viewpoint of parity, since the lost information at the same location can be obtained, the calculation can be shared in the error correction processing stage as in the example of FIG. 1, and the correction (decoding) processing is simplified. There is.

In the example of FIG. 2, Row N
o. A one-byte error detection code or error correction code is arranged only in the portions 0 to 107.
No. It is also possible to arrange in the same manner in the portions of -1 to -16.

Next, another embodiment of the present invention will be described with reference to FIG. This example is Column
It consists of 25 bytes in the n direction and 120 bytes in the Row direction. Also in this example, a one-byte error detection code or error correction code is inserted into the data format as in the example of FIG.

In the figure, "SB1" to "SB3" are synchronization signals. “RS1” to “RS119” are resyncs, and are allocated every 25 bytes, that is, every one interleave unit.

"DC1" to "DC104" are error detection codes or error correction codes, and one byte is added to each unit of resync, that is, 24 bytes. For example, simple parity or CRC is added.

The 1-byte error detection code or error correction code is a RowNo. 0-103 are arranged. As a result, Row No. The remainder of the portion from 0 to 103 is 2496 bytes, and user data and control data can be allocated to this portion.

FIG. 4A shows a frame format (EFM) of a CD (compact disk). A 24-bit pattern frame synchronization signal SYNC,
1 symbol subcoding, 12 symbols of data, 4 symbols of P parity, 12 symbols of data,
Four symbols of Q parity are arranged in order. Here, one symbol is 14 bits, and bits (3 bits each) for combining each symbol are not shown. One frame corresponds to data of 6 samples (16 bits / sample) of each of the L and R2 channels sampled at 44.1 KHz.

In the sub-coding, one block is made up of 98 frames, and FIG. 5 shows this state.
FIG. 6 shows the sub-coding format,
One block consisting of 96 bytes is formed with two synchronization patterns 0 and S1 at the beginning. Of the data P, Q, R, S, T, U, V, and W of 8 bits (after EFM demodulation) of the third to 98th frames excluding the first and second frames corresponding to the synchronization patterns S0 and S1 , P, and Q are used for access, and the 6 bits of R to W are used for special purposes such as displaying still images and karaoke characters.

In each of 98 frames (one sector) constituting one block of the sub-coding, 588 samples (L0 to L587, R0 to R587) of the L and R2 channels,
That is, 2352 bytes (1 byte = 8 bits) of data are included (FIG. 4B).

In the example of FIG. 3, 2496 bytes of user data and control data can be allocated, and the CD
(CD-ROM) data for one sector (2352+
98 = 2450 bytes).

In addition, Row No. Parities of (120, 104, 17) Reed-Solomon code × 25 interleave are arranged in the portions from −1 to −16. The direction in which the parity is generated is the Row direction.

In this example, for each unit of resync,
That is, since a 1-byte error detection code or error correction code is added to 24 bytes, error detection can be performed for each unit. Therefore, similarly to the example of FIG. 1, the error due to the bit slip can be reliably detected, and the erasure information can be sent to the subsequent error correction processing stage to increase the number of error correction bytes, thereby greatly improving the reliability of data. .

Further, from the viewpoint of the parity, the erasure information at the same location can be obtained, so that the calculation can be shared in the error correction processing stage as in the example of FIG. 1, and the correction (decoding) processing is simplified. There is.

In the example of FIG. 3, Row N
o. A one-byte error detection code or error correction code is arranged only in the portions 0 to 103.
No. It is also possible to arrange in the same manner in the portions of -1 to -16.

FIG. 7 is basically the same as the example shown in FIG. 3, except that the 1-byte error detection code or error correction code "DC1" to "DC104" is set to 1 every other byte. It is generated by delaying by an interleave unit (25 bytes). This is to prevent a small error occurring at a byte boundary from causing a two-byte error.

Next, with reference to FIG. 8, a recording / reproducing system for recording / reproducing on the MO disk in the data format as described above will be described.

In FIG. 1, reference numeral 1 denotes a magneto-optical disk (hereinafter, referred to as an “MO disk”). The MO disk 1 is driven to rotate by a spindle motor 2.

The data Din from the input terminal 3 is supplied to an error detection / correction encoding circuit 4. In the encoding circuit 4, for example, an error detection code or an error correction code “DC1” to “DC60”, a parity, or the like is added to Din in the data format shown in FIG. The operation of the encoding circuit 4 is controlled by a controller 5 having a CPU. Although the description is omitted, the same applies to the operation of each of the following circuits.

The coded data Din 'output from the coding circuit 4 is supplied to a modulation circuit 6, for example, (2, 7)
Modulation is performed.

The modulation data output from the modulation circuit 6 is supplied to a synchronization addition circuit 7 to which synchronization signals "SB1" to "SB3" and resyncs of "RS1" to "RS59" are added.

The recording data output from the synchronization adding circuit 7 is supplied to a magnetic head driving circuit 8. Then, a magnetic field corresponding to the recording data is generated by the magnetic field generating coil 9, and the recording data is recorded on the MO disk 1 in cooperation with the laser beam from the optical head 10.

The optical head 10 is moved from the MO disk 1.
The data reproduced by is supplied to the amplifier 11 and amplified. The output data of the amplifier 11 is supplied to a servo circuit 12, where the rotation servo of the spindle motor 2 is performed based on the reproduced data, and the tracking servo and the focus servo of the optical head 10 are performed.

The output data of the amplifier 11 is supplied to a synchronization detecting / removing circuit 13 where a synchronizing signal and resync are detected and removed, and then supplied to a demodulating circuit 14. The demodulation circuit 14 demodulates the reproduced data.

Reproduction data D output from demodulation circuit 14
out 'is supplied to an error detection / correction decoding circuit 15. In the decoding circuit 15, the added 1-byte error correction code or error detection code “DC1” to “D
An error due to a bit slip or the like is detected based on “C60”. Then, the lost information due to the error detection is stored in the RAM of the controller 5 in the form of a flag, for example.

Further, the decoding circuit 15 performs error correction processing based on the parity while using the erasure information stored in the RAM of the controller 5. By using the erasure information, the number of error correction bytes can be increased.

The data Dout that has been subjected to the error correction processing in the decoding circuit 15 is output to an output terminal 16.

In FIG. 8, reference numeral 17 denotes a keyboard for key operation by a user, and reference numeral 18 denotes a display showing the contents of operation and the like.

In the above embodiment, a one-byte error detection code or error correction code is added for each unit of 1 or 2 times the resync, but the unit to be added is not limited to this. Instead, it may be added in units related to resync. For example, in the example of FIG. 1, every interleave unit, that is, 0.5 of resync
It is also conceivable to add each double unit.

The error detection code and error correction code added as described above may be included in the data format (see the examples of FIGS. 2, 3, and 7), or may not be included in the data format (see FIGS. 2, 3, and 7). (See the example in FIG. 1).

In the above-described embodiment, the error detection code or error correction code to be added is one byte, but is not limited to this. However, the greater the data length, the greater the redundancy.

In the above embodiment, an example of recording on an MO disk has been described. However, the present invention can be applied to a case of recording on another optical disk, hard disk, floppy disk, optical card, magnetic card, or tape. Can be. Of course, the present invention can be applied to a communication system.

[0065]

According to the present invention, for example, an error due to a bit slip can be detected for each unit associated with a predetermined data unit into which a resynchronization signal is inserted, and erasure information is sent to a subsequent error correction processing stage. The number of correctable bytes can be increased, and data reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a data format of one embodiment.

FIG. 2 is a diagram showing a data format of another embodiment.

FIG. 3 is a diagram showing a data format of another embodiment.

FIG. 4 is a diagram showing a frame format of a CD.

FIG. 5 is a diagram showing a block (sector) format of a CD.

FIG. 6 is a diagram illustrating a sub-coding format.

FIG. 7 is a diagram showing a data format of another embodiment.

FIG. 8 is a diagram showing a recording / reproducing system for a magneto-optical disk (MO disk).

FIG. 9 is a diagram showing a sector format of a 5-inch MO disk of CS system, 1024 bytes / sector.

FIG. 10 is a diagram showing a data format of a 5-inch MO disk of CS system, 1024 bytes / sector.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Magneto-optical disk 4 Error detection / correction encoding circuit 5 Controller 6 Modulation circuit 7 Synchronization addition circuit 9 Magnetic field generating coil 10 Optical head 13 Synchronization detection / removal circuit 14 Demodulation circuit 15 Error detection / correction decoding circuit SB1-SB3 Synchronization Signals RS1, RS2, ... Resync DC1, DC2, ... Error detection code or error correction code ECC Parity for error correction

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 20/12 G11B 20/18

Claims (1)

(57) [Claims] 1. A data transmission method for transmitting a data sequence with a synchronization signal attached thereto, wherein a resynchronization signal is inserted into the data sequence for each predetermined data unit separately from the synchronization signal. May be an integer multiple of the specified data
Is 1 / integer and the above data string is divided into multiple
The per data unit, the data transmission method comprising adding Lud over data to detect a <br/> error of the data unit at least its own.