JP2606202B2 - Playback device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus suitable for use in a digital audio tape recorder or the like using a rotary head.

[Summary of the Invention]

The present invention relates to a reproducing apparatus in which a recording medium in which a plurality of signal blocks are provided on a recording track uses a rotary head and rotates the rotary head at a speed of twice or more a normal speed to perform reproduction. Error detection of the reproduced signal is performed for each predetermined signal block, the detected signal and the reproduced signal of the corresponding signal block are written into the storage means, and then the contents of the written detection signal are examined. When the detected signal does not exist, the reproduction signal of the corresponding signal block is prevented from being written into the storage means again, so that only a signal having a small error is obtained from the reproduction signal. Thus, signal processing can be performed.

[Conventional technology]

As a rotary head type recording / reproducing device, for example, R-DAT
A rotary head type digital audio tape recorder called a system has been developed.

Next, the tape format and data format of the tape recorder according to the R-DAT method will be described with reference to the drawings.

FIG. 5 shows a tape format. On a magnetic tape, a track 2A recorded by a first rotating magnetic head A (hereinafter simply referred to as a head A) and a second rotating magnetic head (hereinafter simply referred to as a head B) are shown. 2B) are alternately formed obliquely with respect to the longitudinal direction of the tape 1. Heads A and B having different azimuth angles are provided on the drum at an interval of about 180 °. Then, while the heads A and B make one rotation, the tracks 2A and 2B are formed by approximately 1/2 rotation, respectively.

One track 2A (2B) is called one segment, and
It is divided into six data blocks. Of these, the 34 blocks at both ends become auxiliary data areas,
The center 128 blocks are the PCM area. The auxiliary data area is further divided into a number of sections. In each section, a predetermined signal such as a subcode and a PLL run-in signal is recorded, and a non-signal section is also provided. In one of the sections, an ATF signal serving as a pilot signal for tracking servo is recorded.

In the PCM area, a signal obtained by converting the audio signal into PCM is recorded together with other predetermined data. This PCM area consists of 128 data blocks, one block of which is configured as shown in FIG.

In FIG. 6, one block is composed of 288 bits, an 8-bit (1 symbol) block synchronization signal is added at the beginning, and then an 8-bit PCM-ID is added. After this PCM-ID, a block address is added. The two symbols of this PCM-ID and block address (W
With respect to ₁ and W ₂ ), a simple parity error detection encoding process is performed, and an 8-bit parity is added next to the block address. As shown in FIG. 7, the block address is composed of 7 bits excluding the most significant bit (MSB). When the most significant bit is set to "0", it indicates that the block is a PCM block. The 7-bit block address sequentially changes from (00) to (7F) (in hexadecimal), that is, from “0” to “127”. Also, PCM-IDs in which the lower three bits of the block address are recorded in each of the (000) (010) (100) (110) EVEN blocks are defined. The lower 3 bits of the block address are (001) (0
11) Each ODD block address of (101) and (111) is PCM-
The optional code of the ID can be recorded.

The PCM-ID includes 2-bit ID1 to ID8 and a 4-bit frame address, respectively. ID1 to ID7 each have identification information defined. As this identification information,
For example, identification of audio or other uses, number of channels, on / off of pre-emphasis, characteristics of pre-emphasis, identification of sampling frequency, and the like.

The frame address is composed of 4 bits.
The same frame address is given to tracks 2A and 2B. That is, the tracks 2A and 2B formed by one rotation of the heads A and B have the same frame address. This frame address is the PCM-ID of the EVEN block address
It is sequentially repeatedly recorded as "0" to "F" in the interval (W _1).

Next PCM data consists of 32 symbols, C ₁ code and C
Error detection and error correction using _two codes are enabled. In this case, C ₁ sequence is made possible error detection in 2 blocks of the aforementioned EVEN blocks and ODD blocks as a set.

In a digital audio tape recorder having the above-described tape format and data format, tracking servo is performed based on the ATF signal during reproduction. That is, a tracking error is detected based on the ATF signal included in the reproduced signals obtained from the heads A and B, and the speed of the capstan motor, that is, the tape speed is controlled based on the error signal, thereby performing tracking. I have to.

As described above, the method of performing the tracking servo using the ATF signal requires high accuracy in the mounting accuracy of the heads A and B to the drum and the mounting accuracy such as the angle division, and also uses the drum motor and the capstan motor in common. There is a drawback that the cost is increased due to the inability to perform such operations.

In order to solve these difficulties, a tape speed control method called a no-tracking method has been proposed. The no-tracking method uses a frame address obtained from a reproduction signal, and controls the tape speed by comparing the reproduction frame address with a reference frame address.

FIG. 8 shows an example of a servo circuit of a digital audio tape recorder adapted to perform the no tracking method, and FIG. 9 shows a timing chart thereof. The circuit of FIG. 8 has been filed by the present applicant, but is disclosed here as a prior art prior to the present invention.

In FIG. 8, the tape 1 fed from the supply reel 2 is wound around the peripheral surface of the drum 3 by approximately 90 °, and then travels in the direction of the arrow a by the capstan 4 and the pinch roller 5 to the take-up reel 6. It is wound up. Drums 3 are provided with heads A and B having different azimuth angles at approximately 180 ° intervals.

At the time of reproduction, the heads A and B are, for example, 2000 r.p.
It is rotated at 4000 rpm, for example, twice (or more than twice) from 4000 m. Reproduction signals obtained alternately from the heads A and B are passed through reproduction amplifiers 7 and 8 to contact points a and b of a switch 9,
Is added to The switch 9 can switch between the contacts a and b by a switching pulse SWP shown in FIG. From this switch 9, the reproduced waveform shown in FIG. 9 is obtained. A and B in the reproduced waveform indicate the envelopes of the reproduced signals (RF signals) of the heads A and B, respectively. The reproduced signal having this reproduced waveform is equalized by an equalizer 11,
The signal is supplied to a synchronization signal detection and demodulation circuit 13 through a limiter 12, where one symbol 10
It is demodulated from bits to 8 bits per symbol. At the time of recording, 8 bits of one symbol are subjected to a digital modulation process of converting into a preferable pattern of 10 bits in order to reduce low frequency components as much as possible. There is a need to. The demodulated signal is supplied to the buffer RAM 30 and also to the reproduction frame address detection circuit 14, whereby the reproduction frame address PFAD is extracted as shown in FIG. The reproduction frame address PFAD is sequentially obtained at intervals according to the tape speed and supplied to the subtraction circuit 15.

On the other hand, a pulse 16 × SWP which divides the pulse SWP into 16 as shown in FIG. 9 is obtained from the timing generation circuit 10,
This pulse 16 × SWP is divided by 16 with the 1/16 frequency divider 16,
It is counted by the reference frame address counter 17. This count value is supplied to the subtraction circuit 15 as a reference frame address RFAD as shown in FIG. 9, and is subtracted from the reproduction frame address PFAD to obtain a subtraction value shown in FIG.

Therefore, this subtraction value is a value reflecting the tape speed. In the present embodiment, the PWM
By performing (pulse width modulation), a tape speed control signal is formed.

For this purpose, first, the addition circuit 18 adds “+” to the subtraction value.
8 "is added, and the added value is latched by the latch circuit 19. The pulse 16 × SWP is counted 16 by 16 in a clear circuit 20 comprising a counter to generate a latch pulse shown in FIG. 9, and the added value is latched by the latch pulse. The pulse 16 × SWP is counted down by the down counter 21 and the counted value is compared with the latched added value by the comparing circuit 22, so that the subtracted value as shown in FIG. , A control pulse whose duty ratio changes according to the control pulse.

In the example of FIG. 9, the reference frame address RFAD “0”,
Since the reproduction frame address PFAD is “2”, “3”, “4”... For “1” and “2”, the subtraction value is “2”. Therefore, in this example, it is necessary to reduce the tape speed. For this, add "+8"
Control pulse (duty ratio) at steady speed
50%) is determined in the direction of decreasing the tape speed.

The control pulse becomes a speed control signal by passing through the low-pass filter 23, and controls the speed of the capstan motor 27 that drives the capstan 4 through the adder 24 and the drive circuit 25. This motor 27 has another normal speed servo loop,
The speed 27 is detected by a speed detector 28 such as an FG (frequency generator), and this speed detection signal is converted into a voltage by a frequency voltage conversion circuit 29, and this voltage is subtracted from the above speed control signal by an adder 24. Like that.

According to the no-tracking method described above, the conventional
The tracking servo circuit using the ATF signal can be omitted. Also, the mounting accuracy of the heads A and B does not need to be particularly high. Further, advantages such as that the capstan motor 27 and the drum motor can be shared can be obtained.

[Problems to be solved by the invention]

In the no-tracking method described above, since the heads A and B are rotated at least twice as much as during recording, the same head may scan the same track twice or more and read the same data twice or more. For example, if the rotation speed of the heads A and B is 2
At the time of double, consider a state in which almost just tracking is performed as shown in FIG. 10A or 10B. In the case of FIG. 7A, the head A scans the track 2A once, but the head B
Scans the same track 2B twice. In the case of FIG. 2B, the head A scans the same track 2A twice, and the head B scans the track B once.

The data read by the heads A and B are stored in the buffer RA.
The write address is written in the M30. The write address of the RAM 30 is formed based on the frame address and the block address in FIGS. 6 and 7 described above. Now, it is assumed that the first scan is performed satisfactorily and data with few errors are written in the RAM 30, and then the second scan is performed in a state worse than the first scan to obtain data with many errors. . Since this error-rich data is written to the same address where the data obtained in the first scan of the RAM 30 is written, the data with few errors obtained in the first scan is destroyed. Will be lost.

In the no-tracking method, the heads A and B
Since the data can be read twice or more by rotating it twice or more times, it is necessary to select more reliable data and take it into the memory.

[Means for solving the problem]

In the present invention, means for detecting an error in a reproduction signal for each predetermined signal block, storage means for writing a detection signal of the detection means and a reproduction signal of a signal block corresponding to the detection signal, The contents of the detection signal written in the means are checked, and if the detection signal is a signal that has detected no error, the reproduced signal of the corresponding signal block is written again in the storage means. Blocking means.

[Action]

Even if the same head scans the same track a plurality of times, error-free data can be left in the memory.

〔Example〕

FIG. 2 shows, in principle, an embodiment of the present invention in which the present invention is applied to a digital audio tape recorder which performs the no-tracking method of FIG. 8 described above. Such scanning is performed,
The case where the same data is obtained twice from the same head is shown.

First, the head (A or B) moves one track (2A or 2B)
When scanning the first time, C for the 0th to 127th blocks
Performs error detection using _one code. In this case, the reproduction data of each block is entirely written in the buffer RAM 30, and the syndrome is calculated for each set while the EVEN block and the ODD block are set as one set. When there is no error, a flag is set at the address corresponding to the address of the RAM 30 where the data of the error-free block is written. In the illustrated example, a flag is set for the pair of the second and third blocks, and
A flag is set for the set of the sixth and 127th blocks.

Next, the data obtained by the second scan is written into the RAM 30. At this time, before writing, it is checked whether a flag is set at a flag address corresponding to an address where the data is to be written. Then, the data is written only when the flag is not set. Therefore, the data at that address is updated. If the flag is set, the second data is not written, so that the error-free data written first at that address is stored.

In practice, first, the presence or absence of a flag at an address corresponding to a block of data obtained each time the heads A and B scan each time is checked, and when there is no flag, data is written to that address and error detection is performed. Flag is set when there is no. That is, as shown in FIG. 3, first, in step (1), the presence or absence of a flag corresponding to the address of data to be written is checked, and if there is no flag, the process proceeds to step (2) to write data to the above address. Do. While this writing is being performed, a syndrome operation is performed on the data in step (3) to check for errors. If there is an error, the process returns to step (1). If there is no error, a flag is set in step (4), and then the process returns to step (1).

By repeating the above operation, even if the same head scans the same track twice and data is written twice to the same address, the data without error is reliably stored. be able to.

In FIGS. 2 and 3, a CRC parity check of P = W ₁ + W ₂ is actually performed before detecting a flag and writing data. The above-described operation is performed only when there is no error due to the parity check. Further, when a predetermined amount of data is taken into the RAM 30 and processed, and the processed data is discharged, the flag is also reset.

FIG. 1 shows an embodiment of the present invention for implementing the principles described above.

Part of the input data obtained from the synchronization detection and demodulation circuit 13 is first sent to a CRC check circuit 31, where P = W
₁ + parity check of W ₂ is performed. When there is no error as a result of the parity check, a signal OK is output. Based on the signal OK, the timing generator 32 generates a predetermined timing signal such as a latch pulse and sends it to a predetermined circuit.
The latch circuit 33 takes in the data of the EVEN block and the ODD block from the synchronization detection and demodulation circuit 13 based on the latch pulse. This data is written to the buffer RAM 30 through the gate 34 and the data bus 35. This write address is generated by the address generation circuit 36 based on the frame address and block address of the input data, and the generated address is transmitted through the gate 45 and the address bus 41.
The data is supplied to the RAM 30. While this write, the data is also sent to the syndrome calculation circuit 37 error detection by C ₁ code takes place. When there is no error, the flag F is written through the gate 38 and the data bus 35 into the flag address of the RAM 30 corresponding to the address where the data is written.

The flag register 39 stores the RAM 30 before writing data.
The flag of the corresponding flag address is read, and a signal is sent to the timing generator 32 when there is no flag. Based on this, the timing generator 32 generates a write pulse for the RAM 30. The bus controller 42 sends a predetermined control signal to the gates 34 and 38 through the controller 40 based on the timing signal, and controls the other gates 43, 44 and 45 at a predetermined timing. The flag OFF circuit 46 is R in the initial state.
Reset all flags F of AM30.

The no-tracking servo circuit 47 has the circuit configuration of FIG. 8, and a pulse is supplied from the timing generation circuit 10.

The PCM interleave address generation circuit 48 generates an interleave address for deinterleaving the data written in the RAM 30 based on a signal from the timing generation circuit 10 and supplies the interleave address to the RAM 30 through the address bus 41. The ECC circuit 49 performs an error correction process on the data written in the RAM 30 based on the address generated by the ECC address generation circuit 50.

The data of the RAM 30 on which the above-described predetermined signal processing has been performed is read out at a predetermined timing and sent to the interpolation circuit 51, where after performing predetermined interpolation processing such as previous value interpolation, the D / A converter It is supplied to 52 and converted into an analog audio signal. RAM3
When data is read from 0, the above flag OFF circuit
All the flags of the RAM 30 are reset based on the signal from 46.

FIG. 4 shows a specific circuit configuration near the syndrome operation circuit 37, the timing generator 32, and the bus controller 42.

The data of the arithmetic circuit 37 is one block 32 symbols of syndrome, system performs a calculation with respect to the odd-numbered symbol 1 syndrome calculating circuit 37 ₁ and the system 2 syndrome calculation circuit 37 ₂ for operation with respect to the even-numbered symbol
And each is configured as shown. These circuits 37 _1, 37 ₂ are operated on the basis of a signal OK by the parity check.

The timing generation circuit 32 generates EVEN,
A timing signal for managing data of two blocks of ODD is generated. These timing signals include:
Flag read signal FR, flag write signal FW, the system 1, system 2 syndrome calculation circuit 37 _1, 37 ₂ of the identification signal ID,
Flag read request signal FRQ, flag write request signal FWQ, system 1 syndrome operation request signal Q
₁ , a system 2 syndrome operation request signal Q _{2 and the} like are generated. Timing signal These various respective predetermined gate, it is sent to the syndrome calculation circuit 37 _1, 37 ₂ and the bus controller 42 or the like through the gate circuit, such as AND gates. The flags F ₁ and F ₂ of the systems 1 and ₂ obtained from the syndrome operation circuits 37 ₁ and 37 ₂ are finally written into the RAM 30 from the gates 53 and 54 through the data bus 35 and further through the registers 55 and 56. AND gate 57, 58, OR gate
59, sent to the bus controller 42 via the AND gate 60. Based on this, the bus controller 42 outputs a write / read signal R / W for the RAM 30.

〔The invention's effect〕

By taking advantage of the operation of reading data twice or more in the no tracking method, more reliable data can be taken into the memory. In particular, in the almost just tracking state as shown in FIG. 10, the error-free data is not destroyed, and can be reliably stored and used for signal processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a basic timing chart of the embodiment, FIG. 3 is a flowchart relating to flag processing, and FIG. 4 is a circuit configuration of a main part of FIG. FIG. 5 is a diagram showing a tape format to which the present invention can be applied, FIG. 6 is a diagram showing a PCM data block format in the tape format, and FIG. 7 is a diagram in the PCM data format.
FIG. 8 is a diagram showing a format of W ₁ and W ₂ , FIG. 8 is a block diagram of a tape speed control circuit by a no tracking method to which the present invention can be applied, FIG. 9 is a timing chart of FIG.
FIG. 10 is a diagram showing the relationship between the scanning trajectory of the rotary head and the recording track by the no tracking method. In the reference numerals used in the drawings, A, B... Head 1... Magnetic tape 32... Timing signal generating circuit 30... Buffer RAM 37... Syndrome calculation circuit 47.

Claims (1)

(57) [Claims] 1. A reproducing apparatus wherein a recording medium having a plurality of signal blocks provided on a recording track is reproduced using a rotary head, and wherein the same signal block is reproduced a plurality of times. Detection means for detecting an error in a reproduced signal for each signal block; storage means for writing a detection signal of the detection means and a reproduction signal of a signal block corresponding to the detection signal; Check the content of the above detection signal,
Means for preventing the reproduction signal of the corresponding signal block from being written into the storage means again when the detection signal is a signal indicating that there is no error. .