JPH07101544B2 - Error detector - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection device using a CRC code during bidirectional reproduction of serial data recorded on one track on a magnetic tape.

2. Description of the Related Art In recent years, a magnetic recording / reproducing apparatus using a magnetic tape, which is a large-capacity and low-cost recording medium, has made remarkable progress.

However, the essential problem of the magnetic tape is the difficulty of high-speed access caused by the winding time. To solve this problem, one of the commonly used methods is to record the address signal of the tape, such as SMPTE time record, on one of the fixed head tracks on the magnetic tape. It is used for reproduction, confirmation of the address signal, and control of high-speed access. The address signal such as time record information to be recorded is mainly digital data and is digitally magnetically recorded by an FM modulation method or the like. However, in recording / reproducing using magnetic tape, etc., the data loss phenomenon due to the occurrence of dropout is unavoidable. Therefore, conventionally, an error detection code such as CRC code is added together with the data at the time of recording, and there is no code error at the time of reproducing. Is generally used to check the signal, select the signal, and improve the reliability of the reproduced signal.

CRC code has been used for a long time in communication lines, etc. (for example, Hiroshi Miyagawa et al. "Code Theory", (Showa 53.4.30), Shokoido, P190-), and conventionally it is a recording signal, that is, a transmission signal and a reproduction signal. That is, the time series of the received signals are configured on the premise that they are the same.

The above-mentioned conventional error detection device will be described below with reference to the drawings.

FIG. 5 shows the structure of a conventional error detection device using a CRC code. In FIG. 5, reference numeral 51 is a sync signal detection circuit, 52 is a control signal generation circuit, and 53 is a CRC error detection circuit.

The operation of the conventional CRC code error detection apparatus configured as described above will be described below.

The signal format at this time is shown in FIG. The signal transmitted as shown in FIG. 3 (A) is received as shown in FIG. 3 (B). This applies not only to the communication line but also to the conventional magnetic recording / reproducing apparatus.

First, the sync signal detection circuit 51 detects a sync signal serving as a delimiter in the playback signal from the received playback signal and playback clock. A CRC error detection circuit 5 is generated by the control signal generation circuit 52 from the detected sync signal and the above-mentioned reproduced clock.
The control signal required for 3 is generated and the presence or absence of a code error in the reproduced signal is detected.

As described above, the presence or absence of a code error in the reproduction signal can be detected by the configuration shown in FIG. 5 only when the transmission signal and the reception signal have the same time series.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, as described above, when the CRC code is used for the inspection of the reproduction signal from the access track of the magnetic tape, the reproduction is performed in the direction opposite to the recording direction of the magnetic tape, that is, the so-called reverse rotation. The case of reproduction may occur. In this case, the time series of the signal reproduced from one track is opposite to that in the case of normal reproduction in bit units, which is a phenomenon that is not taken into consideration in the conventional communication line.

In view of the above problems, the present invention provides a CR signal, which will be described later, even if the signals are reversed in time series during reverse reproduction of the magnetic tape.
Provided is an error detection device capable of detecting the presence or absence of a code error in a reproduced signal as it is, even if a CRC code created by a preset method is used as an encoding method relatively often used when creating a C code.

Means for Solving the Problems In order to solve the above problems, the error detection device of the present invention is
Synchronous signal detecting means for reproducing serial data recorded on one track on the recording medium in the same direction or in the opposite direction to that at the time of recording, and detecting the cycle of the synchronous signal from the reproduced signal,
A reproducing direction detecting means for finding a reproducing direction of the synchronizing signal, a control signal generating means for generating a control signal required by the synchronizing signal, an adding means modulo 2, a generating polynomial and a reciprocal polynomial of the generating polynomial. CR that can be divided
It is configured to include an error detecting means for detecting an error by the C code.

Operation According to the present invention, the reproduction direction detecting means first identifies whether the magnetic tape is normal rotation reproduction or reverse rotation reproduction,
The sync signal detecting means detects the period of the data in the reproduced signal, the control signal generating means creates the necessary control signal, and the adder circuit modulo 2 performs the modulo 2 addition to the necessary portion of the reproduced signal, and The CRC error detection means capable of division processing by the generator polynomial and its reciprocal polynomial enables error detection as it is, regardless of whether the reproduction signal is normal rotation reproduction or reverse rotation reproduction.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. First, FIG. 3 shows a general signal format. Third
In the figure, (A) is the signal format at the time of recording, and an m-bit CRC code (CRC) for 1-bit data (DATA)
Is added, and a k-bit synchronization signal (SYNC) is further added to have a code length of n bits in total. FIG. 3B shows the data at the time of normal reproduction, and the same time series signal as that at the time of recording can be obtained. FIG. 3C shows a signal at the time of reverse reproduction, and the time series of the signal is opposite to that at the time of recording.

Also, when generating a CRC code during recording, as an initial condition, there are a preset method that is performed after all internal shift registers are set to "1" and a reset method that is performed after all are set to "0". In the embodiment, the preset method will be mainly described.

Before that, first, an outline of an error detection method using a CRC code will be described with reference to the signal format of FIG.

Assuming that the message polynomial to be transmitted is M (x) and the check polynomial C (x), the transmission polynomial P (x) is represented by the following equation (1).

P (x) = M (x) × ^m + C (x) (1) CRC code means that this P (x) is divisible by the generator polynomial G (x), that is, the following expression (2) is satisfied. Like C (x).

P (x) = B (x) · G (x) (2) (where B (x) is a quotient polynomial) Considering the case of reverse reproduction, that is, when the time series of data is reversed before and after, F ^* ( If x) is the reciprocal polynomial of F (x), then P ^* (x) = B ^* (x) G ^* (x) (3). This can be easily derived by rearranging Z = x ^{−1 in} equation (2) and then multiplying both sides by x ⁿ . Therefore, during reverse reproduction, the reciprocal polynomial G ^{* of the} generator polynomial
It can be seen that it is sufficient to perform division by (x).

The above discussion was for the reset method in which the initial values of the division registers are all "0". In the case of the preset method where the initial values of the registers are all "1" Considering a constant that is A (x), P (x)
Will be added and divided. That is, P (x) + A (x) = B ′ (x) · G (x) (5) Therefore, even in the case of the preset method, it may be divided by the generator polynomial G (x) at the time of normal rotation. When reversing the preset method, the reciprocal polynomial of the equation (5) is taken as in the reset method, and P ^* (x) + A ^* (x) = B ^{′ *} (x) · G ^* (x) ...
(6) However, in order to perform this operation with the preset divider, it is necessary to add A (x) again in order to cancel A (x) that is added as the initial value. is there.
The following expression (7) shows the case where A (x) is added again.

A (x) + P ^* (x) + A ^* (x) + A (x) = B ^'*
(X) · G ^* (x) (7) Therefore, at the time of inversion of the preset method, after the addition of A (x) and A ^* (x) to the received inversion polynomial P ^* (x), the reciprocal of the generator polynomial It is sufficient to divide by the polynomial G ^* (x). By the way, since A (x) is a constant of "1" for all mbits from the beginning as shown in equation (4), A
^{* For} (x), all mbits from the end are constants with "1". Processing for adding the A (x) and ^A * (x) in ^P * (x) is ^therefore the beginning and end, respectively mbit of ^P * (x) "1"
Will be added.

Next, examples of the present invention will be described.

FIG. 1 shows the configuration of an error detecting apparatus according to an embodiment of the present invention. In FIG. 1, 11 is a reproduction direction detection circuit composed of a latch, 12 is a synchronization signal detection circuit composed of a serial-parallel conversion shift register and a comparator, and 13 is a control signal generation circuit composed of, for example, a counter and an AND / OR gate. ,
Reference numeral 14 is an adder circuit consisting of exclusive OR modulo 2, and 15 is a CRC error detection circuit composed of a shift register, an AND gate and an exclusive OR.

The operation of the error detecting circuit configured as described above will be described below with reference to the timing chart of FIG. FIG. 4 (A) shows the timing of the normal rotation reproduction, and FIG. 4 (B) shows the timing of the reverse rotation reproduction.

First, the reproduction signal a input to the synchronization signal detection circuit 12 is serial-parallel converted and compared with a predetermined synchronization signal code sequence in a k-bit parallel data state, and when they match, it is output as a synchronization signal. At this time, a part of the sync signal code sequence is provided with asymmetry, that is, for example, a code sequence such as "0011 ... 1101" is provided as the sync signal at the time of recording, and the sync signal is reproduced in the direction of reproduction from the reproduction time series. The detection is performed by the reproduction direction detection circuit 11. Based on the obtained synchronizing signal and reproduced clock b, the control signal generating circuit 13 outputs the preset signal d
The addition signal f is created. As a means for creating, the reproduced clock b may be frequency-divided by a counter while resetting with a synchronizing signal, and the output thereof may be combined by an AND / OR gate, or may be constituted by a shift register. The preset signal d is output at the end of the sync signal portion, that is, immediately before the data and the CRC portion added to the data.

If the CRC code is created by the preset method, the reset signal e is not used. The modulo 2 addition signal f is always "L" in the normal rotation reproduction, and only the CRC part and the last m-bit portion in the reproduction signal data is "H" in the reverse reproduction.
And That is, as described above in principle, the data for adding the m-bit code of all “1” to the modulo 2 to the m bits at the beginning and the end of the CRC part added to the data of the reproduction signal and the data. Invert. The signal obtained by adding the modulo 2 enters the CRC error detection circuit 15, and is divided by the reciprocal polynomial of the original generator polynomial at the time of normal reproduction, and by the reciprocal polynomial of the original generator at the time of reverse reproduction. Whether or not there is an error is detected based on the value of the detection signal g. As an example of the error detection circuit 15, a circuit example when the generator polynomial is the equation (8) is shown in FIG.

G (x) = x ¹⁶ + x ¹² + x ⁵ +1 (8) In FIG. 2, 21 is a shift register consisting of 16 stages,
Each has a preset and reset terminal. 22 is an exclusive OR, 23 is an AND gate, 24 is a preset terminal for the whole, 25 is a reset terminal for the whole, 26 is a switching terminal for dividing by a generator polynomial or its reciprocal polynomial, 28 is a reproduction A signal input terminal 27 is an error detection signal terminal for outputting a division result.

If the CRC code is created by the reset method,
The reset signal e is used instead of the preset signal d, and the method 2
As described above, the addition signal f may be always set to "L" in both normal rotation reproduction and reverse rotation reproduction.

In the present embodiment, the reproduction direction detection circuit 11 is detected from the asymmetry of the reproduction time series of the sync signal code sequence, but of course this may be detected from the rotation direction of the magnetic tape running system drive motor or the like. .

As described above, according to this embodiment, in addition to the conventional structure, the addition circuit 14 having the reproduction direction detection circuits 11 and 2 as a modulus has the structure, even if the CRC code creation at the time of recording is the preset system, It is possible to detect the code error of the reproduced signal with the same configuration as it is, whether the reset method, the normal rotation reproduction or the reverse rotation reproduction, and the circuit configuration can be simplified.

As described above, according to the present invention, whether the signal time series at the time of reproduction is the same as that at the time of recording, the signals are reversed, or at the time of recording.
Whether the CRC creation method is the preset method or the reset method, it is possible to detect a code error in the same process, and by using a common circuit, it is possible to significantly reduce the circuit scale. It is possible to realize an excellent error detection device capable of performing the above.

[Brief description of drawings]

FIG. 1 is a block diagram of an error detecting device in an embodiment of the present invention, FIG. 2 is a circuit diagram of a CRC error detecting circuit which is a main part of FIG. 1, and FIG. 3 is a time series of recording and reproducing signals. 4 is a timing chart showing the operation in the configuration of FIG. 1, and FIG. 5 is a block diagram showing a conventional CRC error detecting device. 11 …… Playback direction detection circuit, 12 …… Sync signal detection circuit, 13
...... Control signal generation circuit, 14 …… Addition circuit modulo 2
15 …… CRC error detection circuit.

Claims (3)

[Claims] 1. A single track on a recording medium records serial data in which a data sequence consisting of a sync signal, data, and a CRC code is repeated at a constant cycle, and when reproducing, the recording medium is recorded on the recording medium with the same normal data. Of the reproduction signal and the reproduction clock that are reproduced by driving in the reverse direction or the reverse direction, the synchronization signal detection means for detecting the cycle of the synchronization signal, the reproduction direction detection means for finding the reproduction direction of the synchronization signal, and the reproduction direction detection means. Depending on the output, if it is a forward reproduction, it is a generator polynomial, and if it is a backward reproduction, an error detection means by a CRC code that performs division processing by a reciprocal polynomial of the generation polynomial, and a signal further input to the error detection means If it is a reverse reproduction signal of the data encoded by the preset method, a predetermined value is added to a part of the reproduction signal and the CRC code part and input to the error detecting means. Adding means for, and error detection apparatus characterized by comprising a control signal generating means for generating respective control signals necessary to perform the above process. 2. The error detecting device according to claim 1, wherein the reproduction direction detecting means uses time-series asymmetry of the synchronizing signal. 3. The error detecting device according to claim 1, wherein the reproducing direction detecting means detects the rotational direction of the recording medium drive system.