JPH0591099A - Data recovery method - Google Patents

Abstract

PURPOSE:To improve the data recovery function at retrial by selecting and recovering one conversion table among plural conversion tables normally and selecting and recovering other conversion table at the retrial. CONSTITUTION:A binarizing signal and a high frequency clock are inputted to a binarizing signal normalizing circuit 16, which generates a signal going to 1 at a leading edge of the binarizing signal and going to 0 at the trailing edge of a bit clock signal. The generated signal is given to a DFF 17, and the signal is sampled by the bit clock and data are extracted and outputted from the DFF 17. In this case, a controller selects a switching signal and outputs it to a ROM 15. Then the data loaded from the ROM 15 to a counter 14 are switched and a different recovery state from the usual recovery state is caused for data recovery. That is, since the recovery state at retrial differs from the usual recovery state failed in recovering data, the data are effectively recovered more than that not switched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing method for changing a data reproducing condition between a normal time and a retry.

[0002]

2. Description of the Related Art When recording digital data, MF
When a self-clock modulation method such as M, (2,7) modulation is used, the change point of the data stream during reproduction (in the case of mark length recording, the change point of 0 → 1 or 1 → 0 In the case of recording, from 0 → 1 change point),
It is necessary to recover the bit clock and extract the data with the bit clock. As a data reproducing circuit using such a bit clock, there are an analog PLL structure and a digital PLL structure.

FIG. 5 shows a conventional analog PLL configuration, in which a bit clock is obtained from the voltage controlled oscillator 1 and the phase edge of the data edge (change point) is compared with that of the bit clock by the phase comparator 2 to output the comparison output voltage. Is supplied to the voltage controlled oscillator 1 through the low pass filter 3 to correct the phase of the bit clock.

This analog PLL configuration has a drawback that the free-running frequency of the voltage controlled oscillator 1 is unstable with respect to temperature, humidity, aging, etc., and the PLL is easily unlocked. Further, when reproducing at a different speed, the free-running frequency of the voltage controlled oscillator 1 needs to be accurately adjusted to that speed, which is practically impossible. However, the analog PLL configuration has an advantage that the phase of the bit clock responds to the average phase of the data edges.

In general, a digital PLL structure has a problem in this respect. Even if there is a small jitter due to a peak shift or the like at a data change point, it excessively responds too much and causes a jitter in a bit clock, or an extreme. There is a disadvantage that a bit clock with a short or long cycle is generated.

In Japanese Examined Patent Publication No. 3-30338, as shown in FIG. 6, for example, a load type 4-bit counter 5 is used.
This problem is solved by using the ROM 6 and the ROM 6. According to this circuit, a constant that is unique at the data change point is not loaded into the counter 5 as in the conventional case, but a number determined by the output state of the counter 5 at that time is read from the ROM 6 and loaded into the counter 5. Therefore, it is possible to arbitrarily determine the characteristics of the bit clock response to the jitter at the data transition point, and prevent bit clock jitter due to fine jitter due to peak shift at the data transition point, for example, by providing backlash. In addition, a response characteristic similar to that of the analog PLL configuration can be obtained by adding a flywheel effect.

[0007]

When data is reproduced by a data recording / reproducing apparatus for a recording medium such as an optical disk, a magnetic disk, or an optical card, a retry is executed when the reading of the data fails. Is common. However, repeating the retry with the exact same reproduction method is not so effective because it expects to be read accidentally.

In such a case, it is obvious that it is effective to change the data reproducing method and perform the retry. In the data recording / reproducing circuit of the recording medium as described above, as one of the causes of the reading failure, the reproduction signal is disturbed due to dust, stains, or defects on the recording medium, and the bit clock slips, The number of errors increases and error correction becomes impossible.
However, the conventional example cannot effectively cope with such data reproduction at the time of retry.

The present invention has been made in view of the above points, and provides a data reproducing method effective for reproducing data at the time of retry by using a bit clock reproducing circuit having a digital PLL structure and a simple structure. The purpose is to provide.

[0010]

In order to solve the above problems, the present invention proposes an edge detecting means for detecting an edge of a binarized signal, and an edge detecting pulse output from the edge detecting means. The initial value is set as a load signal, the clock of a predetermined frequency is counted, and the initial value of this counter is set according to the output value of this counter and the counter that generates the bit clock based on the count result. Multiple conversion tables to supply,
A data reproducing method using a bit clock generation circuit having a conversion table selection unit for selecting one conversion table from a plurality of conversion tables, which is normally selected from a plurality of conversion tables to obtain data. Is reproduced and at the time of retry, another one conversion table is selected from the plurality of conversion tables to reproduce the data. In this manner, by selecting a conversion table different from the normal reproduction condition and performing reproduction at the time of retry, the function of data reproduction at the time of retry can be improved.

[0011]

Embodiments of the present invention will be specifically described below with reference to the drawings. 1 and 2 relate to a first embodiment of the present invention, FIG. 1 shows a bit clock recovery circuit used in the first embodiment, and FIG. 2 shows contents stored in a ROM. In the following description, the inter-mark recording method will be used as the recording method. That is, the change point of the data stream is 0 → 1
It is supposed to be.

The binarized signal, which is output from an information recording / reproducing head such as an optical head used for reproducing information (data) recorded from a recording medium (not shown) or is used for recording data, and which has undergone waveform shaping, is the first First D flip-flop 1 forming the bit clock recovery circuit 10 of the embodiment
1 is applied to the data input terminal, and the output of the first D flip-flop 11 is applied to the data input terminal of the second D flip-flop 12. The signals applied to the data input terminals of these two D flip-flops 11 and 12 are latched at the rising edge of a high-frequency clock of a constant frequency applied to the clock input terminal, and output from the output terminals.

These two D flip-flops 11, 1
The output of 2 is generated as a detection pulse by detecting the edge of the binarized signal through an exclusive OR gate (referred to as EX gate) 13 and applied as a load signal to the load terminal of the counter 14. The high frequency clock is applied to the clock input terminal of the counter 14.

The output terminal of the counter 14 is connected to an address (input) terminal of a ROM (Read Only Memory) 15 that forms, for example, two conversion tables that can change the reproduction condition, and the data output terminal of the ROM 15 is connected. Is connected to the preset end (load input end) of the counter 14, and the data stored in the ROM 15 is read by the count output of the counter 14, and the read data is applied to the preset end of the counter 14. It is set as an initial value by a load signal.

The binarized signal is input to the binarized signal normalization circuit 16, and the high frequency clock is applied to the clock input terminal of the binarized signal normalization circuit 16.
The binarized signal normalization circuit 16 generates a signal which becomes "1" at the rising edge of the binarized signal and becomes "0" at the falling edge of the bit clock signal. The output of the binarized signal normalization circuit 16 is applied to the data input terminal of the third D flip-flop 17, and this third D flip-flop 17 is applied.
A counter 1 is provided at the clock input terminal of the flip-flop 17.
The uppermost output of 4 is applied as a clock, the data applied to the data input terminal is extracted at the rising edge thereof, and this data is extracted and output.

A switching signal is applied to the uppermost address terminal of the ROM 15, and the information stored in the ROM 15 can be switched by the switching signal. In this embodiment, the high frequency clock has a frequency 16 times as high as that of the bit clock to be obtained. Therefore, the counter 14 is a 4-bit hexadecimal clock.

Data indicating the response characteristic of the bit clock with respect to the jitter of the binarized signal is recorded in the ROM 15. There are two examples of the contents of the ROM 15. This is shown in FIGS. 2 (a) and 2 (b). In FIG. 2A, when the phase shift of the binarized signal is ± 3 clock cycles or more, the phase of the bit clock is shifted by 2 smaller than the phase shift of the binarized signal. .. That is, it is possible to prevent backlash of a predetermined ± 2 clock cycle from being caused and the bit clock to follow the jitter of the binarized signal irritably.

On the other hand, FIG. 2B shows that when the phase shift of the binarized signal is within ± 2 clock cycles or less, the phase of the bit clock does not follow it and exceeds ± 2 clock cycles. Makes the phase of the bit clock follow the phase of the bit clock, and when the phase shift of the binarized signal in the positive direction exceeds four clock cycles, the phase of the bit clock is not made to follow it. It is possible to prevent the jitter and limit the fluctuation of the cycle in the positive direction.

That is, the content stored in the ROM 15 is 2
The conversion table data can change the control method of the phase shift of the reproduced bit clock with respect to the phase shift of the binarized signal in two ways. In this embodiment, the ROM shown in FIG.
15 uses an address of 5 bits. The outputs Q0 to Q3 of the counter 14 are given to the address terminals A0 to A3 of the ROM 15. A switching signal from a controller (not shown) that controls the bit clock recovery circuit 10 is applied to the address terminal A4. That is,
This ROM 15 has a total of 32 words of 4 bits each. These two types of data contents are switched by a switching signal. That is, the switching signal is set to, for example, “0” during normal data reading.
Set to a state in which the conversion table of the lower 16 words is read from the ROM 15, and if data reproduction fails under the reproduction condition and retry is performed, the switching signal is switched to "1", and the ROM 15 is read. The reproduction condition can be switched so that the conversion table data of the upper 16 words can be read. The operation of the data reproducing method of the first embodiment using the bit clock reproducing circuit 10 thus constructed will be described below.

First, during normal data reading, a controller (not shown) outputs a switching signal of "0". Therefore, in this case, the outputs Q0 to Q3 of the counter 14
In response to this, the lower 16 words of data in the ROM 15 are read out, and the counter 14 is held in a state of loading this data at each rising edge of the binarized signal.

In this state, the D flip-flop 1
1, 12 and the EX gate 13 generate a pulse for one cycle of the high frequency clock at the rising edge of the binarized signal. The counter 14 is a load type, and the pulse passing through the EX gate 13 is used as a load pulse.
Given to the load terminal of. The counter 14 is loaded with the data supplied to the load input terminals D0 to D3 at the negative edge of the load pulse and is output from the output terminals Q0 to Q3. Then, the output Q3 is output to the third D flip-flop 17 as a bit clock signal.

The binarized signal and the high frequency clock are 2
A signal that is input to the binarized signal normalization circuit 16 and becomes "1" at the rising edge of the binarized signal and becomes "0" at the falling edge of the bit clock signal is generated, and this output signal is the third D The data is output to the flip-flop 17, sampled by the bit clock signal, and the data sampling output is output from the third D flip-flop 17. This output is input to an error correction circuit of a data demodulation circuit (not shown), and error correction processing is performed. If the error cannot be corrected even after performing this error correction processing, the information (error correction impossible or the like) is transferred to a controller (not shown).

In this case, the controller switches the switching signal to "1" and outputs this signal to the ROM 15.
Therefore, the data loaded from the ROM 15 to the counter 14 is switched, a reproduction state different from the normal reproduction state (condition) is established, and the data reproduction operation is performed. That is, since the reproduction state at the time of this retry is different from the normal reproduction state in which the data reproduction has failed, the data can be reproduced more effectively than when the reproduction state is not switched. Further, it can be realized by a circuit configuration having a simple configuration. For example, in Japanese Patent Publication No. 3-30338, which is a conventional example, only one ROM having an address of 4 bits is used, and the reproduction condition cannot be changed even when the reproduction fails, whereas this embodiment can change it. , The playback function can be improved.

FIG. 3 shows a bit clock recovery circuit 20 used in the second embodiment of the present invention. The bit clock recovery circuit 20 according to the second embodiment is similar to the circuit 10 used in the first embodiment except that the first clock is used instead of the ROM 15.
Two of the ROM 21A and the second ROM 21B are used, and output terminals of these ROMs 21A and 21B are connected to a preset terminal of the counter 14 via a multiplexer 22. The multiplexer 22 outputs the output of one ROM 21A (or 21B) (D0 to D3 in this case) to the other ROM 21B (or 21A) according to the switching signal.
The output of is switched to be applied to the counter 14. Each of the ROMs 21A and 21B in this embodiment has an address of 4 bits and has a capacity capable of storing 16 words of information. For example, the data of the conversion table in which the data of (a) and (b) of FIG. It is the contents. Other configurations are exactly the same as those shown in FIG. 1, and are denoted by the same reference numerals.

In this embodiment, the method of controlling the phase shift of the reproduced bit clock with respect to the phase shift of the binarized signal is changed so that the two systems of ROMs 21A and 21B and their outputs are selected and output to the counter 14. It is realized by providing the multiplexer 22 of. That is, the switching signal from the controller (not shown) that controls the bit clock generation circuit 20 is given to the selection terminal of the multiplexer 22.

First, during normal data reading, the switching signal is set to, for example, "0" so that the output of the ROM 21A is output to the counter 14. Therefore, in this case, D0 to D3 of the ROM 21A are loaded into the counter 14 according to the outputs Q0 to Q3 of the counter 14. Further, when the reading of data fails and retry is performed, the switching signal is set to "1", and the output of the ROM 21B is output to the counter 14 this time. Therefore, in this case, according to the outputs Q0 to Q3 of the counter 14,
D3 will be loaded into the counter 14.

By doing so, it becomes possible to change the characteristics of the bit clock reproduction with a simple structure.

FIG. 4 shows the configuration of the bit clock recovery circuit 30 used in the third embodiment of the present invention. Three
Reference numerals 1 and 32 are D flip-flops, 33 is an EX gate, 34 is a counter, and 35 is an RA having an address of 4 bits.
M (random access memory). Also, 36 is 2
A digitized signal normalization circuit, and 37 is a D flip-flop. Further, 38 is an address from a controller (not shown) when the data is written in the RAM 35.
5, and the output is switched by a switching signal so that the output of the counter 34 is normally supplied as the address of the RAM 35.

D flip-flops 31, 32 and EX gate 33, counter 34, binarized signal normalization circuit 36,
The function of the D flip-flop 37 is exactly the same as that of the first embodiment. In this embodiment, the method of controlling the phase shift of the reproduced bit clock with respect to the phase shift of the binarized signal is changed. A RAM 35 is provided in place of the ROM 15, and the response characteristic of the bit clock is written in the ROM for storing fixed data. This is realized by arranging the data indicating the above in the RAM 35 so as to be rewritable by the controller as required. That is, first, before the normal data read, for example, the response characteristic data shown in FIG. 2A is written in the RAM 35, and the normal data read is performed. When the data reading fails and the retry is performed, the response characteristic data shown in FIG. 2B is written in the RAM 35 and the data read is retried.

By doing so, it becomes possible to change the bit clock reproduction characteristic with the circuit 30 having a simple structure, and the same effect as the first embodiment can be obtained. Note that, for example, in the first embodiment, two conversion tables are formed in the ROM 15 and the other conversion table is selected at the time of retry, but the present invention is not limited to this, and three or more conversion tables are formed, A conversion table different from that during normal reproduction may be selected during retry. In addition, when a plurality of retries are performed, the conversion table may be further changed for each retry or the like, or the conversion table may be selectively set.

[0031]

As described above, according to the present invention, a bit clock recovery circuit having a configuration capable of selecting a plurality of conversion tables for determining the conditions for data recovery is used, and the conditions for normal data recovery differ during retry. Since the data reproduction is performed using the conversion table data, the data reproduction function at the time of retry can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a bit clock recovery circuit used in a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing contents stored in a ROM.

FIG. 3 is a configuration diagram of a bit clock recovery circuit used in a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a bit clock recovery circuit used in a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional analog bit clock recovery circuit.

FIG. 6 is a block diagram of a conventional digital bit clock recovery circuit.

[Explanation of symbols]

 10 ... Bit clock recovery circuit 11 ... Flip-flop 12 ... Flip-flop 13 ... EX gate 14 ... Counter 15 ... ROM 16 ... Binary signal normalization circuit 17 ... Flip-flop

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[Procedure amendment]

[Submission date] November 2, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

These two D flip-flops 11, 1
The output of 2 is generated as a detection pulse by detecting the edge of the binarized signal via an AND gate ( hereinafter referred to as AND gate) 13 and applied as a load signal to the load terminal of the counter 14. The high frequency clock is applied to the clock input terminal of the counter 14.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

In this state, the D flip-flop 1
1, 12 and the AND gate 13 generate a pulse for one cycle of the high frequency clock at the rising edge of the binarized signal. The counter 14 is a load type, AND
The pulse passing through the gate 13 is given to the load terminal of the counter 14 as a load pulse. The counter 14 is loaded with the data supplied to the load input terminals D0 to D3 at the negative edge of the load pulse and is output from the output terminals Q0 to Q3. Then, the output Q3 is output to the third D flip-flop 17 as a bit clock signal.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction content]

FIG. 4 shows the configuration of the bit clock recovery circuit 30 used in the third embodiment of the present invention. Three
Reference numerals 1 and 32 are D flip-flops, 33 is an AND gate, 34 is a counter, and 35 is an R having an address of 4 bits.
It is AM (random access memory). Reference numeral 36 is a binarized signal normalizing circuit, and 37 is a D flip-flop. Further, 38 is an address from a controller (not shown) when the data is written in the RAM 35.
5, and the output is switched by a switching signal so that the output of the counter 34 is normally supplied as the address of the RAM 35.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0029

[Correction method] Change

[Correction content]

D flip-flops 31 and 32, AND
Gate 33, counter 34, binarized signal normalization circuit 3
6. The function of the D flip-flop 37 is exactly the same as that of the first embodiment. In this embodiment, the method of controlling the phase shift of the reproduced bit clock with respect to the phase shift of the binarized signal is changed. A RAM 35 is provided in place of the ROM 15, and the response characteristic of the bit clock is written in the ROM for storing fixed data. This is realized by arranging the data indicating the above in the RAM 35 so as to be rewritable by the controller as required. That is, first, before the normal data read, for example, the response characteristic data shown in FIG. 2A is written in the RAM 35, and the normal data read is performed. When the data reading fails and the retry is performed, the response characteristic data shown in FIG. 2B is written in the RAM 35 and the data read is retried.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

[0031]

As described above, according to the present invention, a bit clock recovery circuit having a configuration capable of selecting a plurality of conversion tables for determining the conditions for data recovery is used, and the conditions for normal data recovery differ during retry. Since the data reproduction is performed using the conversion table data, the data reproduction function at the time of retry can be improved.

[Procedure Amendment 6]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Description of Codes] 10 ... Bit clock recovery circuit 11 ... Flip-flop 12 ... Flip-flop 13 ... AND gate 14 ... Counter 15 ... ROM 16 ... Binary signal normalization circuit 17 ... Flip-flop

[Procedure Amendment 7]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure Amendment 8]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

[Procedure Amendment 9]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

Claims (1)

[Claims] 1. A clock having a predetermined frequency and an edge detection means for detecting an edge of a binarized signal, an edge detection pulse output from the edge detection means being used as a load signal to set an initial value, and a predetermined frequency. Count
A counter that generates a bit clock based on the count result, a plurality of conversion tables that supply the initial value of the counter, and one conversion table are selected from the plurality of conversion tables according to the output value of the counter. A data reproducing method for reproducing data from a recording medium by using a bit clock generating circuit composed of a conversion table selecting means. Normally, one conversion table is selected from a plurality of conversion tables to reproduce the data. The data reproducing method is characterized in that when performing a retry, another one of the plurality of conversion tables is selected to reproduce the data.