JP2882611B2 - Write-once optical recording / reproducing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write-once optical recording / reproducing apparatus, and more particularly, to a write-once optical recording / reproducing apparatus which is continuous with previous recording without providing a gap and a preamble section and has the same modulation rule. The present invention relates to a write-once optical recording / reproducing apparatus for performing additional writing.

[Prior Art and Problems to be Solved by the Invention] Recently, an optical card capable of storing a much larger amount of data than a magnetic card, an IC card, and the like has been developed. In an optical recording / reproducing apparatus for recording information using this optical card as a recording medium, the optical card is irradiated with an intensity-modulated laser beam to change the reflectivity of the medium, thereby recording information. ing.

In the optical card, a plurality of linear tracks are formed in a band shape on the recording surface, and each track is divided into a plurality of sectors as recording units. The sector consists of a preformatted track number section, sector number section, CRC section, and a data section in which data can be written, and considers the case where there is a difference between the bit rate at the time of writing and the bit rate at the time of reading. Generally, there is a gap between sectors. Further, a preamble section and a synchronization section are provided at the head of each sector, and a synchronization section and a postamble section are provided at the end of each sector.

The optical card is used only for reading or for additional writing. When performing additional recording, after a predetermined gap is provided from the end of the already recorded recording sector, a preamble and a synchronization pattern are written, then data is written to the data portion, and further, a synchronization pattern and a postamble are written. It has become. However, it is necessary to provide a gap and a preamble part and a postamble part for each additional recording, so that the redundancy is large and the format efficiency is low.

Therefore, a standardized format proposed by OMCF (Optical Memory Card Forum) may be adopted. In this format, the preamble part, synchronization part, track number part, sector number part, CRC
The synchronization section is preformatted following the section. When performing additional recording, synchronization is performed using the synchronization pattern of the synchronization unit, and data is written continuously from the end of the previous sector and according to the same modulation rule. Further, following this data, the track number, sector number, CRC, and synchronization pattern for the next additional recording are written, and the processing ends. Thereafter, at the time of additional recording, synchronization is performed using the synchronization pattern written by the previous recording, and recording is performed continuously from the end of the sector by the previous recording and according to the same modulation rule as the previous recording. It is supposed to do.

In a conventional write-once optical recording / reproducing apparatus that performs additional writing on an optical card recorded in such a format, first, a previously recorded portion is read. Next, the read signal obtained by reading is binarized and demodulated. Next, the end of the sector is detected from the demodulated data, and the modulation of the data to be added is started by this detection. The modulated data is supplied to a laser diode drive circuit, which changes the optical output of the laser diode based on the modulated data, and writes data to the optical card at the same time that the end of the sector is detected. In this way, writing is continuously performed on the previous recording portion under the same modulation rule.

However, in actuality, a delay of a read signal with respect to scanning of the optical head, a delay of digital processing for binarization, a delay at the time of demodulation, a delay by filter processing, and the like occur. The data to be added is delayed. When the bit rate at the time of writing is slow, the delay amount of such a joint between sectors is relatively small, and can be followed as a small bit jitter, and there is almost no influence at the time of reading. However, when the bit rate is high, the pit interval at the joint of the sectors becomes large, resulting in unprocessable bit jitter, which may result in a bit shift. Then, for example, the clock bit and the data bit may be inverted and read, so that there is a problem in that the data cannot be read.

The present invention has been made in view of such a problem, and by correcting the phase of a write VFO signal for writing data to be additionally written, it is possible to make the seams of the sector continuous and prevent bit shift. It is an object of the present invention to provide a write-once optical recording / reproducing apparatus that can be used.

[MEANS FOR SOLVING THE PROBLEMS] A write-once optical recording / reproducing apparatus according to claim 1 of the present invention comprises: a VFO circuit for obtaining a read VFO signal from a read signal obtained by scanning an optical card with an optical head; A demodulation circuit that demodulates the read signal and outputs demodulated data; a termination recognition circuit that detects a termination of the writing from the demodulated data and outputs a termination signal; and a circuit delay at a timing when the termination signal is input. Delay correction means for generating and outputting a write VFO signal whose phase is adjusted based on a preset value based on the amount and a predetermined count value of the counter clock, and driving the optical head by modulating additional write data with the write VFO signal The write-once type optical recording / reproducing apparatus according to claim 2 of the present invention, wherein the end recognition circuit determines the predetermined end of the last write. It is characterized in that outputs the termination signal before bets.

[Operation] In claim 1 of the present invention, the demodulation circuit is a VFO for reading.
The read signal is demodulated using the signal, and the end recognition circuit detects the end of the previous write from the demodulated data. The delay compensating means, at the timing of the termination signal from the termination recognition circuit,
Write VF phase adjusted based on preset value based on circuit delay and predetermined count value of counter clock
Generate an O signal. The modulating means uses the write VFO to modulate the modulated data and drive the optical head to perform additional writing. Since the phase of the write VFO signal is corrected with respect to the phase of the read VFO signal, the delay of the end signal obtained using the read signal is canceled at the time of writing, and the previous recording and the current recording are not performed. Seams are continuous.

According to a second aspect of the present invention, the termination recognition circuit generates a termination signal a predetermined bit before the termination of the previous write. The delay correction means uses this end signal to write VF
Generate an O signal. As a result, a delay correction amount for several clocks of the write VFO signal is obtained.

Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings. 1 to 6 relate to a write-once optical recording / reproducing apparatus according to a first embodiment of the present invention. FIG. 1 is a block diagram showing a circuit configuration, and FIG. 2 is an explanatory diagram showing a track format of an optical card. FIG. 3 is a block diagram showing the delay correction circuit in FIG. 1, and FIGS. 4 to 6 are timing charts for explaining the operation of the delay correction circuit.

As shown in FIG. 2, the tracks of the optical card used in this embodiment include a VFO pull-in pattern section 1, a synchronization section 2, track / sector number (address) sections 3, 5, and a data section 4.
It is constituted by. The VFO pull-in pattern section 1 is formed with a VFO pull-in pattern which is a continuous pattern with a minimum pit interval (for example, 1T (T is a bit cycle) in MFM modulation). The synchronization section 2 has a synchronization pattern B for a track number. In the track / sector number section 3, a synchronization pattern A is formed following the track number and the sector number to which the CRC is added. The synchronization pattern A is a data synchronization pattern. The data section 4 is composed of data and a synchronization pattern B.

When the optical card is not used, only the VFO pull-in pattern section 1, synchronization section 2, and track / sector number section 3 are prerecorded. To perform additional writing for one sector following the track / sector number part 3, write a data part 4 consisting of data and a synchronization pattern B following the synchronization pattern A, and further write the next part following the data part 4. The track / sector number part 5 for writing is written. The track / sector number section 5 has the same configuration as the track / sector number section 3, and at the time of writing, writes the synchronization pattern A and ends.
Thereafter, similarly, at the time of additional recording, the data section 4 and the track / sector number section 5 are written.

In FIG. 1, a read signal obtained by scanning a pit pattern of an optical card (not shown) by an optical head (not shown) is supplied to a binarizing circuit 11. The binarization circuit 11 obtains a pulse-shaped binarized signal at the edge of the pit due to a change in the level of the read signal due to the difference in the reflectance between the pit portion of the optical card and the other portions. This binarized signal is supplied to the VFO circuit 12 for reading. The VFO circuit 12 is supplied with a VFO clock from the oscillator 13 and
12 generates a read VFO signal from the binarized signal by using the VFO clock, and outputs the read VFO signal to the demodulation circuit 14, the sector end recognition circuit 15, and the delay correction circuit 16. VFO circuit 12
Also outputs a synchronized read signal including a clock.
Note that the oscillator 13 also generates a counter clock obtained by multiplying the VFO clock by 100.

The synchronized read signal and read VFO signal are supplied to the demodulation circuit 14. The demodulation circuit 14 demodulates the read signal using the read VFO signal. In this case, the demodulation circuit 14 supplies the demodulated data including the clock to the sector end recognition circuit 15, and separates the data clock and the demodulated data and supplies the separated data to the control circuit 17.

The sector end recognition circuit 15 has a shift register (not shown), and this shift register latches demodulated data including a clock in response to a read VFO signal. The sector end recognition circuit 15 detects that the output pattern of the shift register matches the synchronization pattern A. As mentioned above, the previous recording ended with the synchronization pattern A,
The sector end recognition circuit 15 detects the end of the previous recording (sector end) by detecting the synchronization pattern A, and outputs a pulse-like sector end signal to the control circuit 17 and the delay correction circuit 16. ing.

The control circuit 17 supplies a control signal to the read VFO circuit 12, the demodulation circuit 14, the sector end recognition circuit 15, and the delay correction circuit 16 to control them. Further, the control circuit 17 receives the data of the track number and the sector number of the data to be additionally written. The control circuit 17 stores this data in the memory 18 and compares it with the track number and the sector number indicated by the demodulated data. That is, the control circuit 17 has a shift register (not shown), and the shift register latches the demodulated data at the timing of the data clock. The control circuit 17 checks the CRC based on the output of the shift register, and if it is correct, determines whether the track number and the sector number indicated by the output of the shift register match the track number and the sector number in the memory 18. to decide. If they match, the control circuit 17 generates a write start sector signal during the period of the synchronization pattern A and outputs it to the delay correction circuit 16. The control circuit 17 provides a write enable signal from the time when the write start sector signal and the sector end signal both become high (hereinafter referred to as “H”) to the time when the write is completed, as a write enable signal. The permission signal is output to the delay correction circuit 16 and the modulation circuit 19.

As shown in FIG. 3, the delay correction circuit 16
1, a latch circuit 22, a reset circuit 23, a 100-digit counter 24, and a gate circuit 25. The AND circuit 21 is supplied with a read VFO signal and a write start sector signal. The AND circuit 21 supplies the read VFO signal to the clock terminal CK of the latch circuit 22 during the “H” period of the write start sector signal. The latch circuit 22 is provided with a sector end signal at the data terminal D, latches the sector end signal at the data terminal D at the falling edge of the clock input to the clock terminal CK,
The load / count mode signal is given to the 100 decimal counter 24. That is, when the write start sector signal changes from a low level (hereinafter, referred to as “L”) to “H” (the leading end of the synchronization pattern A), the sector end signal is “L”,
From the latch circuit, the count mode signal of “L” is counted.
Given to 24. When the sector end signal becomes “H” at the end of the synchronization pattern A, the “H” load mode signal is output to the counter 24 from the latch circuit 22 at the falling timing of the read VFO signal. ing.

100 decimal counter 24 is 50 decimal counter 26 and binary counter 2
Has seven. The 50-ary counter 26 receives a counter clock from the oscillator 13 and counts the counter clock. The count output of the fifty-decimal counter 26 is supplied to a timing signal generation circuit 28 and also to a binary counter 27 via an OR circuit 29 as a carry signal. The timing signal generation circuit 28 determines that the delay amount at the sector joint is 0.
If it is within the range of 25T to 0.5T, the 50-digit counter 26
The timing signal is output to the binary counter 27 via the OR circuit 29 when the counter clock is counted several times from the load timing described later. The binary counter 27 counts the output of the OR circuit 29 so that the output is inverted at the timing of the carry signal from the 50-digit counter 26 or the timing signal from the timing signal generating circuit 28.

When the load mode is designated, the 50-ary counter 26 stores a preset value DI input from the preset input terminal 30.
NA to DINF are loaded at the load timing, and when the load mode is designated, the binary counter 27
The preset value DING from 31 is loaded at the load timing. The output of the latch circuit 22 is also provided to the reset circuit 23. The reset circuit 23 is also supplied with a counter clock, and outputs a reset signal to reset the output of the latch circuit 22 to the latch circuit 22 at the falling edge of the counter clock after the load mode signal is input. This count mode signal causes the counter
26 and 27 start counting from the preset value. The preset values DINA to DING are set based on the amount of circuit delay from when demodulated data is obtained from the read signal, when the sector end signal is generated, and writing is performed.

The output of the binary counter 27 is output via the gate circuit 25 as a write VFO signal. Gate circuit 25 is a control circuit
A write enable signal is given from 17, and the write VFO signal is output to the modulation circuit 19 only during the write enable signal period.

As shown in FIG. 1, data to be additionally recorded is also given to the modulation circuit 19 from the control circuit 17, and the modulation circuit 19 uses the write VFO signal to store the additionally recorded data in the same manner as the previous recording. , And outputs a modulation signal to the laser diode drive circuit 20 during the write permission signal period. The laser diode drive circuit 20 drives the laser based on the modulation signal so that the optical head irradiates the optical card with laser light.

Next, the operation of the write-once optical recording / reproducing apparatus thus configured will be described with reference to FIGS. FIG. 4A shows a write start sector signal.
FIG. 4B shows a sector end signal, and FIG. 4C shows a track format. FIG. 5 shows the vicinity of the end of the synchronization pattern A, FIG. 5 (a) shows the write start sector signal, FIG. 5 (b) shows the synchronization pattern A, and FIG. 5D shows a read VFO signal, FIG. 5D shows a sector end signal, and FIGS.
(F) shows a write VFO signal. FIG. 6 is an enlarged view of the time axis indicated by the broken line in FIG. 5. FIG. 6 (a) shows the read VFO signal, and FIG. 6 (b) shows the sector end signal. FIG. 6 (c) shows the load / count mode signal, and FIG. 6 (d) shows the counter clock.

When performing additional recording, first, a track number and a sector number for writing additional recording data are specified in the explanation circuit 17. The optical head starts reading, and the read read signal is binarized in the binarization circuit 11. VFO circuit for lead 12
Is the VFO for reading by the binary signal from the binary circuit 11
Signal and a synchronized read signal. The demodulation circuit 14 demodulates the synchronized read signal using the read VFO signal. The demodulator data and the data clock from the demodulation circuit 14 are separated and supplied to the control circuit 17, and the demodulated data including the clock is supplied to the sector end recognition circuit 15.

The control circuit 17 detects the track / sector number part in the previous recording from the demodulated data. That is, the control circuit 17
Latches the demodulated data at the data clock timing and performs a CRC check to detect whether the designated track number and sector number match the track number and sector number indicated by the demodulated data. If they match, a write start sector signal which becomes "H" at the start timing of the synchronization pattern A is output as shown in FIGS.

On the other hand, the sector end recognition circuit 15 detects that the same pattern as the synchronization pattern A has been demodulated by latching demodulated data including a clock at the timing of the read VFO signal, and FIG. As shown in (1), a sector end signal is generated at the end of the synchronization pattern A. The sector end signal and the write start sector signal are supplied to the delay correction circuit 16.

The AND circuit 21 of the delay correction circuit 16 gives the read VFO signal during the “H” period of the write start sector signal to the clock terminal CK of the latch circuit 22. The latch circuit 22 latches the sector end signal at the timing of the signal given to the clock terminal CK,
The load / count mode signal is output to the decimal counter 24. As shown in FIGS. 5B, 5C, and 5D, a sector end signal is generated at the rising timing of the read VFO signal for detecting the end bit of the synchronization pattern A. The load mode signal is supplied to the 100-digit counter 24 at the falling timing of the application VFO signal.

When the load mode is designated, the 100-decimal counter 24 loads the preset values input to the preset input terminals 30 and 31 at the load timing. As shown in FIG. 6, the load mode signal from the latch circuit 22 is changed to “L” count mode signal by the reset signal output from the reset circuit 23 at the falling edge of the counter clock after the load mode signal is generated. Change. Thus, the 100-base counter 24 starts counting from the preset value at the load timing. For example, when the preset value is 20, the 50-digit counter 26 generates a carry signal when counting 30 counter clocks from the load timing. The carry signal is supplied to a binary counter 27 via an OR circuit 29.
To invert the output of the binary counter 27. The output of the binary counter 27 is output to the write VFO through the gate circuit 25.
Output as a signal. That is, the phase of the write VFO signal is set to, for example, a preset value of 2 with respect to the read VFO signal.
By setting it to 0, you can advance by 0.1T.

Now, it is assumed that the circuit delay amount is within 0.25T. In this case, the timing signal is not output from the timing signal generation circuit 28. Therefore, as shown in FIG. 5E, a carry signal is output from the 50-digit counter 26 after a time based on the preset value from the load timing, and the output of the binary counter 27 is inverted. Thereafter, the output of the binary counter 27 is inverted every 50 counts of the counter clock, that is, every 0.25T.

On the other hand, when the amount of circuit delay is in the range of 0.25 to 0.5T, the timing signal is generated from the timing signal generation circuit 28 after several counts after the load timing. This timing signal is supplied to the binary counter 27 via the OR circuit 29, and the output of the binary counter 27 is inverted almost immediately after the load timing, as shown in FIG. Next, a carry signal is generated after a time based on the preset value, and the output of the binary counter 27 is inverted again. Thus, for lead
It is possible to generate a write VFO signal whose phase is advanced by 0.25 to 0.5T from the VFO signal.

VFO for light, phase adjusted based on preset value
The signal is provided to modulation circuit 19. Modulation circuit 19 is a control circuit
The data to be added is given from 17 and the VFO for writing
A modulation signal is created using the signal, and is provided to the laser diode drive circuit 20. The laser diode drive circuit 20 drives the laser diode according to the modulation signal and writes data to be additionally written into the optical card.

Thus, in the present embodiment, the 100-digit counter 24
Generates the write VFO signal by counting the counter clock multiplied by 100 of the read VFO signal,
By loading the value corresponding to the circuit delay into the decimal counter at the timing of the read VFO signal at the end of the previous recording, the phase of the write VFO signal is shifted from the phase of the read VFO signal by the circuit delay. proceeding. Therefore, at the time of reading, the seam of the sector does not become discontinuous, and the data can be read reliably.

FIGS. 7 and 8 relate to a write-once optical recording / reproducing apparatus according to a second embodiment of the present invention. FIG. 7 is a block diagram showing a sector end recognition circuit of the second embodiment, and FIG. FIG. 9 is an explanatory diagram for explaining an operation of the example. FIG. 8 (a) shows the first
FIG. 8B shows the sector end signal of the second embodiment, and FIG. 8C shows the synchronization pattern A.

In this embodiment, the circuit delay amount at the joint of the sectors is 0.5T.
The correction in the case of larger than is enabled. This embodiment is different from the first embodiment in that a sector end recognition circuit 35 shown in FIG. 8 is employed in place of the sector end recognition circuit 15 shown in FIG. 1, and the other configuration is the same as the first embodiment.

The sector end recognition circuit 35 includes synchronization pattern detection circuits 36 and 37.
And a selection circuit 38. The synchronization pattern detection circuit 36 has the same configuration as that of the sector end recognition circuit 15 in FIG. 1. When the same pattern as all the bits (n bits) of the synchronization pattern A is obtained from the demodulated data, the selection circuit 36 A detection signal is output to 38. On the other hand, if the same pattern as the m-bit pattern excluding the (nm) bit at the end of the synchronization pattern A is obtained from the demodulated data, the synchronization pattern detection circuit 37 selects the selection circuit.
A detection signal is output to 38. Select circuit 38
Selects the detection signal of the synchronization pattern detection circuit 37 during the "H" period of the write start sector signal, and selects the detection signal of the synchronization pattern detection circuit 36 at the time of reading and outputs it as the sector end signal. . During periods other than the "H" period of the write start sector signal, the synchronous pattern detection circuit 36 performs match detection for all patterns, thereby preventing a malfunction during reading.

In the embodiment configured as above, the synchronization pattern detection circuit 37 outputs a detection signal when the first m bits of the demodulated data of the synchronization section match the m bits of the synchronization pattern A. If (nm) is a relatively small value, the possibility of erroneously detecting the synchronization pattern A is extremely low even if the match detection is performed with m bits. A detection signal is output from the synchronous pattern detection circuit 37 at the first m-th bit timing, and a sector end signal is output from the selection circuit 38, as shown in FIGS. 8 (b) and 8 (c). , A sector end signal is generated at a timing (nm) bits earlier than the end of the sector. This sector end signal is used as the delay correction circuit 16
And a write VFO signal is created. That is, the phase of the write VFO signal is
, And the phase is advanced based on the number of bits detected by the synchronization pattern detection circuit 37.

Thus, in the present embodiment, 0.5T to (n−
m) It is possible to cope with a circuit delay of a bit pattern interval. For example, if (nm) = 2, then 0.5 to 1
The circuit delay in the range of T can be corrected.

[Effect of the Invention] As described above, according to the present invention, by setting the phase of the write VFO signal in accordance with the delay amount of the circuit,
There is an effect that bit shift can be prevented by making the seams of the sector continuous.

[Brief description of the drawings]

1 to 6 relate to a write-once optical recording / reproducing apparatus according to a first embodiment of the present invention. FIG. 1 is a block diagram showing a circuit configuration, and FIG. 2 is an explanatory diagram showing a track format of an optical card. FIG. 3 is a block diagram showing the delay correction circuit in FIG. 1, FIGS. 4 to 6 are timing charts for explaining the operation of the delay correction circuit, and FIGS. According to the write-once optical recording / reproducing apparatus of the second embodiment,
FIG. 12 is a block diagram showing a sector end recognition circuit of the second embodiment, and FIG. 8 is an explanatory diagram for explaining the operation of the second embodiment. 12: read VFO circuit, 14: demodulation circuit, 15: sector end recognition circuit, 16: delay correction circuit, 17: control circuit, 19: modulation circuit.

Claims (2)

(57) [Claims] 1. A VFO circuit for obtaining a read VFO signal from a read signal obtained by scanning an optical card by an optical head; a demodulation circuit for demodulating the read signal and outputting demodulated data; An end recognition circuit for detecting the end of writing and outputting an end signal; and for a write whose phase is adjusted based on a preset value based on a circuit delay amount and a predetermined count value of a counter clock at a timing when the end signal is input. A write-once optical recording / reproducing apparatus, comprising: delay correction means for generating and outputting a VFO signal; and modulation means for driving the optical head by modulating additional write data with the write VFO signal. 2. The additional optical recording / reproducing apparatus according to claim 1, wherein said termination recognition circuit outputs said termination signal a predetermined bit before a termination of a previous write.