JP2001052341A - Data-reproducing apparatus of optical disk-reproducing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly reproduce data irrespective of a signal length by detecting marks and spaces smaller than a minimum length specified by coding binary signals, and correcting adjacent bits thereby obtaining the minimum length. SOLUTION: When detecting a string of two '1's in a shift register 21, a control circuit 24 changes either the front of the rear from '1' to '0' on the basis of the judge result of a comparator 23 to correct so that three '1's continue. More specifically, when detecting a string of two '1's, the control circuit 24 compares analog values of a sample hold circuit 22 of front and rear bits of the two '1's and changes the bit of the larger analog value from '0' to '1'. When detecting a string of two '0's, the control circuit changes the bit of the smaller analog value of the front and rear bits from '1' to '0', thereby correcting so that three '0's continue. Data errors by an edge shift of binary data of reproduction signals are corrected, so that data can be exactly reproduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus for an optical disk reproducing apparatus for binarizing an analog signal reproduced from an optical disk.

[0002]

2. Description of the Related Art FIG. 7 shows an example of the configuration of an optical disk reproducing apparatus. 7, 1 is an optical disk, 2 is a pickup, 3 is an I / V amplifier, 4 is an analog calculator, 5 is a servo controller, 6 is an equalizer, 7 is a binarization circuit, and 8 is a PL.
L and 9 are sampling circuits, and 10 is a spindle motor.

The optical disc 1 includes a read only type called a ROM and a writable type called a RAM or RW. FIG. 8A shows the state of the writable optical disk after data recording. When the write data is "1" on the optical disk, the recording film undergoes a phase change by the irradiation of the intense laser beam, and a low reflection area called a mark is formed. An area without a mark corresponding to data “0” is called a space, and is an area having a high reflectance.

At the time of data reproduction, a weak laser beam spot moves along a track, and data is read depending on the amount of reflected light. The length of the mark and the space is 1 to 3T, where T is the period of the read clock.
It is encoded so as to take nine discrete values up to 1T.

[0005] The ROM is the same except that the mark described above is a depression called a pit and writing is not possible. In the disk reproducing apparatus, a laser beam emitted from a semiconductor laser in the pickup 2 is reflected by the optical disk 1 and converted into an electric signal by a four-divided light receiving element in the pickup 2 to output four signals A to D. After the output signal passes through the I / V amplifier 3, the analog arithmetic unit 4 performs analog addition of (A + B + C + D), and outputs the result as a reproduction signal RF. Further, another two analog calculation results representing the track error signal TE and the focus error signal FE are output from the analog calculator 4 to the servo control circuit 5.

The data reproducing apparatus 11 comprises an equalizer 6, a binarizing circuit 7, a PLL 8 and a sampling circuit 9.
After removing the C component, gain adjustment is performed on the frequency by the equalizer 6, and thereafter, it is compared with the fixed reference voltage Vref by the binarization circuit 7 and binarized. After this, PL
At L8, a synchronous clock component included in the reproduction signal is extracted. Using the falling edge of the extracted synchronous clock, binarized data is extracted from the reproduced signal binarized by the sampling circuit 9. Here, 1 is used as the binarization circuit.
Are provided, and a reference voltage V of a fixed voltage level is provided.
A method of binarizing by comparing with ref is used.

[0007]

When reproducing data from an optical disk on which information is recorded, a reproduced signal sometimes has a large amplitude fluctuation or amplitude asymmetry. Particularly, in a writable optical disk, the amplitude may fluctuate greatly due to fluctuations in various conditions of writing, etc., and the amplitude of the AC component of the reproduced signal may be close to 0 near the end of the mark. In this case, accurate information cannot be reproduced by the conventional method of comparing with the fixed voltage level reference voltage Vref.

FIG. 8B shows a reproduced signal corresponding to the mark and the space in FIG. 8A. Arrow b1,
b2 is the location where the above problem occurs. Further, as another conventional example, there is a method of controlling the slice level to an appropriate level with respect to the fluctuation of the envelope of the reproduction signal and the asymmetry. For example, Japanese Patent Application Laid-Open No. 9-274770 discloses a control method in which the midpoint between the upper envelope and the lower envelope of a reproduction signal is set to the slice level of the binarization circuit, as shown in FIG. I have.

The method of setting the midpoint of the envelope at the slice level follows the lower limit of the data frequency band and fluctuations below it in principle, and cannot follow higher frequencies. However, in an optical disk capable of writing data of 4 GB or more, the mark and the short mark after the long space and the short space after the long mark, respectively, as shown by arrows b1 and b2 in FIG. The amplitude of the reproduced signal of the space becomes extremely small, becomes almost zero at the boundary between the mark and the space, and the frequency of erroneous detection increases. Since the frequency of such amplitude fluctuation corresponds to 1 / 6T, which is the upper limit of the data frequency band, there is a problem that the information cannot be accurately reproduced because the fluctuation cannot be followed.

At the short mark after the long space,
And one of the causes that the amplitude of the reproduction signal of the mark and the space becomes extremely small at the short space after the long mark, respectively, is that the amplitude of the long mark and the space is extremely large, so that the interference with the adjacent space or the mark is also caused. It is because it becomes big. Another possible cause is that the relationship between the size of the mark and the size of the beam spot during recording is not uniform, and a long mark tends to spread.

An object of the present invention is to provide a data reproducing apparatus of an optical disk reproducing apparatus capable of accurately reproducing data regardless of a signal length.

[0012]

According to a first aspect of the present invention, there is provided a data reproducing apparatus for reproducing an analog signal reproduced from an optical disk of an optical disk reproducing apparatus, wherein Binarizing means for binarizing a signal by comparing it with a reference voltage, and a specified length for detecting a mark and space shorter than a minimum length specified by encoding the signal binarized by the binarizing means A detection unit; and a correction unit that corrects adjacent bits to a minimum length when a mark and a space shorter than the minimum length are detected by the specified length detection unit.

According to the second aspect of the present invention, when the specified length detecting means detects a mark and a space that are less than 2 bits less than a minimum length, the correcting means determines both adjacent bits of the detected mark and the space by the mark and the space. To be corrected. In the invention according to claim 3, when the specified length detecting means detects a mark and a space less than one bit less than the minimum length, the correcting means outputs the reproduced analog signal for both adjacent bits of the detected mark and the space. Are compared, and in the case of a mark, the smaller bit of the signal value is corrected to a mark and a space in the case of a space.

According to a fourth aspect of the present invention, the specified length detecting means is constituted by a shift register, and a signal output from the binarizing means is inputted and shifted to determine whether the length is less than the specified minimum length. Whether the detected analog signal is sampled and held and shifted,
The correcting means determines the magnitude of the signal value of both adjacent bits of the mark and the space.

According to a fifth aspect of the present invention, the prescribed length detecting means is constituted by a register, and a sample and hold circuit for sampling and holding the reproduced analog signal is provided. A register and the sample-and-hold circuit are sequentially designated to record and hold data, and it is detected whether or not less than the specified length from the data recorded and held in the register,
The magnitude of the signal value of the bit adjacent to both the mark and the space is determined from the data recorded and held in the sample and hold circuit.

In the invention according to claim 6, the specified length detecting means detects marks and spaces exceeding the maximum length specified by encoding, and the correcting means detects the marks and spaces exceeding the maximum length by the specified length detecting means. If a space is detected, the adjacent bits are corrected to the maximum length.

According to a seventh aspect of the present invention, when the reproduced analog signal is equal to or more than a predetermined value A from a reference value, the reference voltage of the binarizing means is changed to a predetermined value B.
In the state where the reference voltage of the binarization means is increased or decreased by a predetermined value B, when the reproduced analog signal changes below or above a reference value, the reference voltage of the binarization means is increased or decreased. To the original value.

According to the present invention, there is provided a signal length judging means for judging a mark or space length of a signal to be coded and outputted, wherein the signal length judged by the signal length judging means is less than a predetermined length. At this time, the reference voltage of the binarizing means is increased or decreased by B + C larger than the predetermined value B.

In the ninth aspect of the present invention, the C value is added to a predetermined value for increasing or decreasing the reference voltage every time the signal length determining means determines that the length is equal to or less than a predetermined length.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of an optical disk reproducing apparatus to which the present invention is applied, and FIG. 2 is a block diagram of a correction circuit according to a first embodiment of the present invention. The first embodiment relates to claims 1 to 4.

In FIG. 1, an optical disk 1, a pickup 2, an I / V amplifier 3, an analog operation unit 4, a servo control unit 5, an equalizer 6, a PLL 8, and a spindle motor 10 are the same as those described with reference to FIG. is there. The first embodiment differs from the conventional example in that a correction circuit 20 shown in FIG. 1 is used instead of the sampling circuit 9 of the conventional example.

The correction circuit 20, as shown in FIG.
It comprises a four-stage shift register 21, a four-stage sample-hold circuit 22, a comparator 23 and a control circuit 24. The output of the binarization circuit 7 is input to the shift register 21 and is shifted in synchronization with the clock signal output from the PLL 8.

An analog signal output from the equalizer 6 is input to the sample and hold circuit 22, and the sampled and held analog value is held and shifted by a clock signal. The comparator 23 compares the sample and hold values of the first stage and the fourth stage, and compares the result of the determination with the control circuit 2.
4 is output.

The control circuit 24 includes a four-stage shift register 2
It is determined whether or not data shifted by 1 is less than the minimum length. That is, it is determined whether there is one or two consecutive “1” or “0”.

When "1" detects one column, the control circuit 2
Reference numeral 4 changes the data values of the shift registers before and after the detected shift register from "0" to "1" and corrects three "1s" so as to be continuous. Further, when “0” detects one column, the data values of the shift registers before and after the detected shift register are changed from “1” to “0” and “0” becomes 3
It is corrected so as to be continuous.

The corrected data is shifted in synchronization with the clock pulse, and the final four-stage output is output as binary data. Further, the control circuit 24
When "1" detects two columns in the comparator 23,
Is changed from “0” to “1” based on the determination result of “1”, and correction is performed so that three “1” s are continuous.

That is, when the control circuit 24 detects two columns of “1”, the control circuit 24 compares the analog values of the sample hall circuit 22 of two bits before and after “1” and determines the bit having the larger analog value. On the other hand, "0" is changed to "1". When “0” detects two columns, the smaller bit of the analog value of the preceding and following bits is changed from “1” to “0”, and correction is performed so that three “0” s are continuous.

Therefore, in the binarized data of the reproduced signal, a data error due to the edge shift is corrected, so that accurate data reproduction can be performed.

Next, a correction circuit according to a second embodiment of the present invention will be described with reference to FIG. The second embodiment is according to claim 5. In the second embodiment, the correction circuit 20 includes four registers 31, four sample and hold circuits 32, a pointer 33, and a control circuit 34.

In the second embodiment, the output of the binarizing circuit 7 is input to the four registers 31 in parallel, and the output of the equalizer 7 is input to the sample and hold circuit 32 in parallel. The pointer 33 sends out signals for sequentially designating the four registers 31 and the sample and hold circuit 32 in synchronization with the clock signal output from the PLL 8.

Therefore, the signal from the binarizing circuit 7 and the output signal from the equalizer 6 are held and recorded in the register and the sample and hold circuit designated by the pointer 33. The control circuit 34 stores “1” or “0” in the register 31 as in the control circuit 24 described in the first embodiment.
Bits before and after the number of columns are detected are “0” or “1”
And correct so that three “1” or “0” are consecutive.

When "1" detects two columns, "0" is set for a bit whose analog value of the preceding and succeeding bits is large.
Is changed to “1”, and correction is performed so that three “1” s are consecutive. When “0” detects two columns, “1” is replaced with a bit whose analog value of the preceding and following bits is small. Change to “0” and correct so that three “0” s are continuous.

Next, a correction circuit according to a third embodiment of the present invention will be described with reference to FIG. The third embodiment is according to claim 6. In the first embodiment described with reference to FIG. 2, the correction circuit 20 performs the correction when the data correction is less than the minimum length. However, the third embodiment copes with the case where the data length exceeds the maximum length. Correction.

In FIG. 4, reference numeral 41 denotes a 15-stage shift register; 42, a 15-stage sample-hold circuit; 43, a comparator for comparing the first-stage and fourth-stage sample-hold values; A comparator for comparing the sample and hold value of the stage, 45 is a control circuit.

As in the first embodiment, the shift register 4
The output of the binarization circuit 7 is sequentially shifted to 1 in synchronization with the clock signal from the PLL 8. The analog signal output from the equalizer 6 is applied to the sample hold
The sample is held and shifted in synchronization with the clock signal from L8.

When the control circuit 45 detects "1" or "0" less than the minimum length of 3 bits based on the judgment result of the comparator 43 in the same manner as described in the first embodiment, Are corrected so that three bits are consecutive. When the control circuit 45 detects a sequence of 13 consecutive “1” s or “0s” in the data of the shift register 41, it changes the bits at both ends to “0” or “1” to change the bits to “1” or “0”. Are corrected so that 11 bits continue for 11 bits.

When a row of twelve consecutive "1" s is detected, the comparator 44 compares the analog values of the second and thirteenth stages, changes the smaller one to "0", and "1" is corrected so as to be continuous for 11 bits. Also,
If 12 consecutive columns of “0” are detected, the comparator 44 compares the analog values of the second and 13th stages, changes the larger one to “1”, and sets “0” to 11 bits. Correct to be continuous.

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a configuration diagram of a binarizing circuit according to a fourth embodiment of the present invention. The fourth embodiment is according to claim 7.

In the binarization circuit 7 shown in FIG.
74 is a comparator, and 75 is a control unit. The reference voltage Vref 0 of the comparator 74 is set to Vref 0 = 0 V, and outputs “1” when the voltage of the analog signal output from the equalizer 6 is 0 V or more, and outputs “0” when the voltage of the analog signal is 0 V or less. .

The reference voltage Vref 1 of the comparator 72 is set to Vref 1 = + AV, and is set to “1” when the voltage of the analog signal output from the equalizer 6 is equal to or more than + AV, and to + AV
"0" is output in the following cases.

The reference voltage Vref of the comparator 73 is
2 is set to Vref 2 = −AV, and is set to “1” when the voltage of the analog signal output from the equalizer 6 is equal to or higher than −AV, and to −AV
"0" is output in the following cases.

The control unit 75 outputs "1" from the comparator 72, that is, when the voltage of the analog signal is +
If it is determined to be equal to or higher than AV, the reference voltage Ref of the comparator 71 is set to Ref = + BV (B <A), and the analog signal output from the equalizer 6 is binarized and a binarized signal is output. .

When "0" is output from the comparator 73, that is, when it is determined that the voltage of the analog signal is equal to or lower than -AV, the reference voltage Ref of the comparator 71 is set to Ref = -BV and the equalizer 6 outputs The output analog signal is binarized and a binarized signal is output.

When the comparator 74 outputs “0” from the comparator 74 while the reference voltage Ref = + BV is being output to the comparator 71, the controller 75 changes the reference voltage Ref to the comparator 71 to Ref = 0V. Let it.

The comparator 71 supplies a reference voltage Ref =
-BV is being output, the comparator 74
When “1” is output, the reference voltage Ref to the comparator 71 is changed to Ref = 0V. By changing the reference voltage Ref in this manner, it is possible to follow the amplitude fluctuation in the high frequency band and accurately reproduce data.

Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a configuration diagram of a binarization circuit according to the fifth embodiment. The fifth embodiment relates to claims 8 and 9. The difference between the configuration of the fourth embodiment described in FIG. 5 and the fifth embodiment is that a signal length determination unit 80 is added to the fourth embodiment.

The signal length determination section 80 shows the signal length determination of the control circuit 24 of the correction circuit 20 shown in FIG.
In the fourth embodiment, a comparator 7 for outputting a binary output
Although the reference voltage Ref 1 is increased or decreased by a constant value B from the reference value 0, in the fifth embodiment, the reference voltage Ref is set to an optimum value corresponding to the analog signal input to the binarization circuit 7. I have.

That is, the signal length determining section 80 determines whether or not the binarized data includes a mark or space having a length of 1T or 2T.

When the signal length determination section 80 determines that a mark or space having a length of 1T or 2T is included, the control section 75 increases or decreases the reference voltage Ref of the comparator 71 from the reference value 0. Change the value B to B + C. Even if the state is set to B + C, if the signal length determination unit determines that a mark or space having a length of 1T or 2T is included, the value is changed to B + 2C.

By doing so, the optical disk 1
The analog signal can be binarized in an optimal state even if is changed. When a 1T or 2T mark is detected, the value may be different from B + C, and when a 1T or 2T space is detected, the value may be different from-(B + C ').

In the embodiment, the change of the reference voltage Ref is changed according to the judgment result of the signal length judging unit. However, the binarized data to be output is detected and corrected by an error detection / correction circuit (not shown). May be performed, and an external microcomputer (not shown) may change the reference voltage based on the result.

[0052]

As described above, since the reference value for binarizing an analog signal is switched according to the value of the analog signal reproduced from the optical disk, binarization is performed accurately regardless of the signal length. be able to.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an optical disk reproducing apparatus to which the present invention is applied.

FIG. 2 is a configuration diagram of a correction circuit according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a correction circuit according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a correction circuit according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a binarization circuit according to a fourth embodiment of the present invention.

FIG. 6 is a configuration diagram of a binarization circuit according to a fifth embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional optical disc reproducing apparatus.

FIG. 8 is an explanatory diagram of recording and reproducing analog signals of a signal of an optical disk.

FIG. 9 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 Reference Signs List 6 equalizer 7 binarization circuit 20 correction circuit 21, 41 shift register 22, 32 sample hold circuit 23, 43, 44, 71-74 comparator 24, 34, 45 control circuit 75 control unit 80 signal length determination unit

Claims (9)

[Claims] 1. A data reproducing device for an analog signal reproduced from an optical disk of an optical disk reproducing device, comprising: a binarizing means for binarizing the reproduced analog signal by comparing it with a reference voltage; Length detecting means for detecting a mark and space shorter than the minimum length specified by encoding of the signal binarized by the binarizing means, and the mark and space shorter than the minimum length are detected by the predetermined length detecting means. A data reproducing device for an optical disc reproducing device, comprising: a correcting unit that corrects adjacent bits to a minimum length when the adjacent bit is corrected. 2. The method according to claim 1, wherein when the specified length detecting means detects a mark or space less than 2 bits less than the minimum length, the correcting means corrects both adjacent bits of the detected mark and space into a mark and space. 2. A data reproducing apparatus for an optical disk reproducing apparatus according to claim 1, wherein: 3. The signal value of the reproduced analog signal for both adjacent bits of the detected mark and space when the specified length detecting means detects a mark and space less than one bit less than the minimum length. And correcting a bit having a smaller signal value in the case of a mark and correcting a bit having a larger signal value in the case of a space into a mark and a space. A data reproducing apparatus of the optical disk reproducing apparatus according to the above. 4. A method according to claim 1, wherein said predetermined length detection means comprises a shift register, receives a signal output from said binarization means, shifts the signal, and detects whether or not the length is less than the specified minimum length. 4. The apparatus according to claim 1, wherein said reproduced analog signal is sampled and held and shifted, and said correction means determines the magnitude of a signal value of both adjacent bits of a mark and a space. Data reproducing device of an optical disk reproducing device. 5. A method according to claim 1, wherein said predetermined length detecting means comprises a register, and further comprises a sample and hold circuit for sampling and holding said reproduced analog signal, wherein said correction means synchronizes with said clock signal by said register and said sample and hold circuit. Are sequentially designated to cause data to be recorded and held, the data recorded and held in the register to detect whether or not the length is less than the specified length, and the mark and space to be detected from the data recorded and held in the sample and hold circuit. 4. A data reproducing apparatus for an optical disk reproducing apparatus according to claim 1, wherein the magnitude of the signal value of both adjacent bits is determined. 6. A method according to claim 1, wherein said predetermined length detecting means detects a mark and a space exceeding a maximum length defined by encoding, and said correcting means detects a mark and a space exceeding the maximum length by said predetermined length detecting means. 6. The data reproducing apparatus for an optical disk reproducing apparatus according to claim 1, wherein adjacent bits are corrected to have a maximum length. 7. When the reproduced analog signal is equal to or more than a predetermined value A from a reference value, the reference voltage of the binarization means is increased or decreased by a predetermined value B, and In the state where the reference voltage has increased or decreased by a predetermined value B, the voltage value of the reference voltage of the binarization means is restored when the reproduced analog signal changes below or above the reference value. 7. A data reproducing apparatus for an optical disk reproducing apparatus according to claim 1, wherein: 8. A signal length judging means for judging a mark or space length of a signal to be encoded and output, wherein the signal length judged by the signal length judging means is equal to or less than a predetermined length.
8. The data reproducing apparatus according to claim 7, wherein said reference voltage of said binarizing means is increased or decreased by B + C larger than said predetermined value B. 9. The optical disk according to claim 8, wherein the C value is added to a predetermined value for increasing or decreasing the reference voltage each time the signal length determination means determines that the length is equal to or less than a predetermined length. Data playback device of playback device.