KR980011083A - Optical disc recorder - Google Patents

Abstract

The optical disc recording and reproducing apparatus of the present invention controls the reference voltage of the level slice circuit in the period of the channel bit signal to minimize the influence of the jitter due to the interference of the before and after signals upon reproduction of the optical disc, And an interference amount between the signals from the phase difference between the reference clock and the reproduced channel bit string is detected to control the reference voltage of the level slice circuit to improve the reproduction performance and improve compatibility between the discs.

Description

Optical disc recorder

FIG. 1 is a block diagram of a configuration of an optical disc recording and reproducing apparatus according to a conventional technique. FIG.

FIG. 2 is a view of the light condensing by the optical pickup of FIG. 1;

FIG. 3 is a layout diagram of a photodetector of the optical pickup of FIG. 1; FIG.

FIG. 4 is a block diagram showing the configuration of an equalizer of an optical disc recording and reproducing apparatus according to a conventional technique; FIG.

FIG. 5 is a detailed circuit diagram of a channel bit signal reproducing unit of an optical disc recording and reproducing apparatus according to a conventional technique.

FIG. 6 is a circuit diagram in which an equalizer and a channel bit signal reproducing unit of an optical disc recording and reproducing apparatus according to the related art are digitally constructed.

FIG. 7 is a recording and reproducing signal of an optical disc according to a conventional technique. FIG.

FIG. 8 is a reproduction characteristic diagram of an optical disc according to a conventional technique; FIG.

FIG. 9 is a block diagram of the level slice circuit of the optical disc recording and reproducing apparatus according to the present invention; FIG.

FIG. 10 is a configuration diagram of the first embodiment of the level slice controller in the level slice circuit of FIG. 9; FIG.

11 is an input / output characteristic table of the level slice controller in FIG. 10, (B) is an input / output characteristic table of the first decoder among level slice controllers in FIG. 10, (C) Output characteristics table of the second slice controller of the level slice controller of FIG. 10; (d) an input / output characteristic table of the disk characteristic storage unit;

FIG. 12 is a detailed circuit diagram of a second decoder of the level slice controller of FIG. 10; FIG.

FIG. 13 is a waveform diagram of operation signals of each portion of the level slice controller of FIG. 10; FIG.

FIG. 14 is a configuration diagram of a second embodiment of a level slice controller in an optical disc recording and reproducing apparatus according to the present invention; FIG.

FIG. 15 is a control flow chart of the level slice controller of FIG. 14; FIG.

FIG. 16 is a configuration diagram of a level slice controller according to a third embodiment of the optical disc recording and reproducing apparatus according to the present invention; FIG.

FIG. 17 is an input / output characteristic table of the disk characteristic storage unit of the level slice controller of FIG. 16, and FIG. 16 is an input / output characteristic table of the D flip-flop among the level slice controllers of FIG.

18 is a signal waveform diagram of each part of the level slice controller of FIG. 16;

FIG. 19 is a configuration diagram of a fourth embodiment of the level slice controller in the optical disc recording and reproducing apparatus according to the present invention. FIG.

FIG. 20 is a configuration diagram of a level slice controller according to a fifth embodiment of the optical disc recording and reproducing apparatus according to the present invention; FIG.

FIG. 21 is a configuration diagram of a level slice controller according to a sixth embodiment of the optical disc recording and reproducing apparatus according to the present invention; FIG.

FIG. 22 is a configuration diagram of a seventh embodiment of the level slice controller in the optical disc recording and reproducing apparatus according to the present invention; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

70: Digital level comparator 80: Playback clock detector

90: Level slice controller

The present invention relates to an optical disc recording and reproducing apparatus and, more particularly, to an optical disc recording and reproducing apparatus for improving reproduction characteristics and providing an optical disc recording and reproducing apparatus for improving interchangeability between CD-type discs and between CD- .

2. Description of the Related Art In general, optical discs including a CD (Compact Disk) and a DVD (digital versatile disc) have a pit of a groove or a mark having a different reflectance on a spiral signal track, When reproducing the recorded information together with the recording of such information, the laser beam is condensed using the optical pickup, the condensed beam is tracked along the track of the signal pit or mark, and at the same time, the disk is controlled at a constant speed Information is recorded or reproduced.

As shown in Fig. 1, the optical pickup includes an objective lens 3 for condensing a laser beam on a signal track of the disc, and an objective lens 3 for focusing the movement center position of the objective lens 3 A focus actuator 5 for adjusting the position of the objective lens 3 to bring the reflective surface of the disc into a depth of focus and a beam splitter for separating incident light and reflected light, A laser diode (LD) 8 for generating a laser beam; a laser diode 8 for detecting the output of the laser diode 8; And a laser power detector (P-DET) 9 for transmitting and controlling the laser beam to and from the servo 14. The laser diode and the beam splitter are not shown, A diffractor for generating an auxiliary beam for detecting a signal and a sensor lens for obtaining a focus control signal by astigmatism when the astigmatic method is used.

As shown in FIG. 2, in the case of the three-beam method, the photodetector detects a main beam (LB) for reading an information signal on a signal track whose laser light beam is a pit row of grooves of an optical disc, (LBr, LB1). Therefore, as shown in FIG. 3, the main beam is divided into four parts

(PDE, PDF) for detecting the auxiliary beams above and below the photodetectors (PDA, PDB, PDC, PDD).

The light reflected from the recording surface of the disc on which the information signal is recorded is condensed by the objective lens, condensed again by the sensor lens through the beam splitter, Assuming that the interval, that is, the track pitch is Tp, the auxiliary beams for tracking control signal detection are arranged 0.25Tp apart from the tracks, and the signals a, b, c and d detected by the photodetectors (PDA, PDB, PDC and PDD) frequency reproduction signals RF of the focus control signals Fe and (a + b + c + d) from the signals e and f detected in the photodetector PDE and PDF The tracking control signal Te is obtained.

The tracking control signal Te is input to the tracking servo 12 through the tracking error detector 18 to control the tracking driver 4 of the optical pickup and the focus control signal Fe is output from the focus search unit 17 Is inputted to the focus servo 11 to control the focus actuator 5 of the optical pickup.

On the other hand, the high frequency reproduction signal RF is converted into an analog signal through a digital / analog converter through a pre-amplification, a pulse-width-wise → digital signal processing process, and then output.

More specifically, the preamplification process is performed by amplifying a signal picked up by the photodetector to remove a noise and a distortion of the signal by an equalizer, shaping the waveform through a level slice device, and then performing a data strobe strobo circuit section.

4A and 4B are block diagrams showing the configuration of the equalizer. In this case, the bandwidth of the reproduced signal waveform is narrowed, the inter-symbol interference is minimized, and the high frequency reproduction signal RFe, In the case of a CD, delay units 21 and 21 'are connected in such a manner as to be delayed in three stages as shown in (a). In the case of a high density optical disc such as a DVD, A high differential amplifier is used in which delays 23, 23 ', 23 ", and 23 ?? are connected so as to be delayed in five stages as shown in FIG. 3B. In each stage of all equalizers, amplifiers 22 and 22' (24, 24 ', 24 ", 24 ??), and the delay time and the amplification gain for amplifying the output of each node are symmetrical with respect to the front and rear ends.

5, the level slice circuit includes a comparator 31 receiving the high frequency reproduction signal RFe and the slice level reference signal Vref, a buffer 32 for buffering the output of the comparator 31, And an integrator 33 composed of capacitors C1 and C2 connected between the resistors R1 and R2 and the ground and connected to the non-inverting input terminal (+ And the output of the variable resistor VR1 connected to the inverting input terminal (-) is connected to VCC and the other terminal is connected to the differential amplifier (VEE), and the differential amplifier (32) 34). The operation will be briefly described as follows.

In the level slice circuit portion, the high frequency reproduction signal RFe outputted from the equalizer 20 is inputted to the comparator 31 and compared with the reference voltage Vref. At this time, the output is "1" if it is higher than the reference voltage, Quot; 0 "signal to generate a rectangular shape of the channel bit signal and CHBr, and outputs the signal through the buffer 32, and simultaneously generates the reference voltage Vref.

The reference voltage causes the reproduction signal "0" state and the "1" state to be symmetric, for the following reason.

Generally, in CD and DVD, when the channel is encoded as described above, the ratio of the state of "0" to the state of "1" is the same. Therefore, the ratio of the state of "0" And therefore,

The ratio of the pit portion to the land portion is different because the pit becomes longer due to the accumulation of heat at the end portion of the pit during recording, and the reproduction signal becomes asymmetric. Therefore, by correcting the asymmetry phenomenon by integrating the square wave CHBr of the channel bit signal and adjusting the reference voltage through the variable resistor VR1 so that the 0 state and the 1 state are symmetric as described above, more precise reproduction is possible Do.

The square-wave CHBr of the reproduced channel bit signal is input to a channel bit reproduction clock generator (not shown). The channel bit reproduction clock generator generates a channel bit clock signal The channel bit clock signal CL is periodically changed in accordance with the time of switching from "0" to "1" in the channel bit signal sequence or from "1" to "0" .

FIG. 6 is a view showing a state in which a signal transmitted from an optical pickup is constituted by a digital circuit instead of an analog circuit due to the development of a semiconductor manufacturing technology and a digital signal processing technique, and an RF / 61, and then equalized to a digital equalizer 62. The equalized high-frequency signal DRFe is compared with a reference level signal DVref in the digital level comparator 63, and when it is larger than the reference level signal DVref, And outputs a channel bit signal string CHBr of a rectangular wave with a signal of "0 "

The reference level signal DVref gives a digital signal value of 1 when the square wave channel bit sequence CHBr outputted from the digital level comparator 63 is "1", a digital signal value of -1 when it is "0" ), And the square wave channel bit sequence CHBr is the same as an electric signal that has been optically modulated in order to record a signal on a disk, and the state transition ("0" in the state of "1" Quot; state or "0" state to "1" state), and outputs a channel bit signal sequence (a clock signal CL) as a clock signal CL of a channel bit signal period through a digital reproduction clock generator (DCO) And generates a signal that is in phase with the state transition edge.

As described above, the optical disc is subjected to various reproduction processes from the optical pickup to the digital signal processing until the user views the image or hears the sound. In this reproduction process, more accurate reproduction A channel bit signal reproduced with respect to a reference signal (a clock signal whose average value of jitter is 0 by a phase lock loop circuit corresponding to a channel bit clock at the time of recording and adapted to match a phase change point of the regenerated line bit signal) It is necessary to reduce the jitter back and forth of time.

As shown in FIG. 7, the jitter is obtained by reproducing the square wave signal of the recording channel bit signal (A) and the pit signal stream recorded on the actual (B) disc with the optical pickup, as shown in FIG. 7, The phase shift of the rectangular wave should coincide as theoretically the same signal of the reproduction channel bit signal of (c), but actually, the heat of the laser beam is accumulated at the end portion when the pit is manufactured on the disk, As shown in Fig. 8, the longer the pit length becomes, the higher the level slice is due to the electric noise before and after the reference level, the interference between channel bits, and the crosstalk between adjacent signal tracks. , The conventional equalizer has been used as 3-tap or 5-tap in order to remove it, but the length of the recorded pit signal And the amount of inter-signal interference differs according to the distance between the front and back pit signals. Thus, the symmetrical equalizer is difficult to completely equalize, so that the reduction effect is not large. Also, So that an inherent jitter caused by the jitter is left.

As described above, the conventional optical disc recording and reproducing apparatus is asymmetrically influenced by the before and after signals in which signals recorded on the actual disc are recorded, and the inter-signal interference amount depends on the length of the recorded pit signal and the distance between the pit signals before and after Since the second optical pickup has inherent jitter due to variations in the reproduction characteristics of the optical pickup, the recording characteristics of the disc, and the reproduction environment, the CD-ROM recordable optical disc, that is, the CD standard and the CD (CD-R) and CD-E (CD-E) are different. Therefore, it is necessary to use a dedicated player in accordance with the standard. Therefore, compatibility is poor and compatibility between the CD- (DVD-R), DVD (Digital Versatile Disc), DVD (DVD-RAM), but a recordable disk standard is proposed, the impaired, the recording and playback performance in front of the second issue reasons, there are many problems such as can not be obtained as long as the capacity of existing DVDs.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an optical disc recording and reproducing apparatus capable of solving the above-mentioned problems and reducing time jitter, thereby improving reproduction performance and improving reproduction compatibility of recordable discs.

According to an aspect of the present invention, there is provided an optical disc recording and reproducing apparatus including a digital level comparator for detecting a channel bit signal from a reproduced signal, a reproducing clock detecting unit for detecting a clock signal from the channel bit signal, And a level slice controller for controlling the period of the channel bit signal according to the signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The present invention is characterized in that the length of the signal pit itself recorded on the optical disc and the distance between the pits are 3T, 4T, 5T, ... , 11T, and the length of the channel bit signal is doubled, and the slice level is controlled by limiting and predicting the reference level to a finite number of discontinuous values. For example, in the case of a CD For each of the nine types from 3T to 11T, 18 kinds of predictions are predicted from the pit to the land or from the land to the pit, and the other 19 cases are predicted from before and after. do.

The control values are stored by using a memory element, and the state transition point of the reproduction signal is set as a predicted point, and distances to the state transition points before and after the state transition point are detected and the corresponding storage elements are successively selected.

To this end, the optical disc recording and reproducing apparatus of the present invention is characterized in that the level slice circuit portion includes a reproduction bit stream pattern detector for detecting a pattern of the reproduction bit stream from the high frequency reproduction signal DRFe outputted from the digital equalizer, A phase comparator 92 for comparing the phase of the reproduction clock CL with the phase of the reproduction channel bit signal, And a reproduction control signal selection unit 94 for selecting a control value stored in the reproduction control signal storage unit 93 according to the reproduction bit stream pattern .

FIG. 10 shows a first embodiment of a level slice controller according to the present invention, which includes a plurality of memory elements MEo ... MEn 'to generate a previous control signal DVa (a previous signal pit or a land portion , And a plurality of memory devices MSo ... MSn 'for storing a control signal DVb (a control value corresponding to the influence of the control signal DVb A second disk characteristic storing unit 113 for storing a control value corresponding to the influence of the signal pit or the land portion of the first disk characteristic storage unit 111, A second selection unit 140 for selecting a memory element of the second disk characteristic storage unit 113 and a second selection unit 140 for selecting a memory bit of the channel bit signal CHBr, CL as an input, detects a state transition edge, 2 selection unit 140, a control signal DVa of the first disk characteristic storage unit, and a control signal DVb of the second disk characteristic storage unit to calculate a level slice reference signal DVref And an adder 115 for adding the adder 115.

At this time, the first selector 120 receives the signal DRFe 'that is in synchronization with the reproduction clock CL and is nT time ahead of the high frequency reproduction signal DRFe, and outputs 0 except for the value selected as shown in FIG. 11 (e) And a decoder having an input / output characteristic. The state transition detector 130 delays the reproduction clock signal CL by one clock, and includes a shift register 131 having the same input / output characteristics as the delay register 131, And an exclusive OR gate 132 which receives the reproduced channel bit signal CHBr as a delayed reproduced clock signal and outputs the output of the state transition detector 130 as a reset signal, And a decoder 142 for decoding the output of the counter according to the input / output characteristics such as (B), wherein the first clock And a second disk The storage elements constituting the characteristic storage units output the stored data if selected according to the output of the first and second selection units as shown in (c), and maintain the high impedance state when not selected.

The decoder of the first selector 120 includes a plurality of shift registers SR0 to SRn-1 connected in a multistage manner as shown in FIG. 12 and a plurality of shift registers SR0 to SRn-1 for inverting the output of the shift register SRo An AND gate A1 for receiving an output inverted signal of the shift register SRo and an input inverted signal and an output of the shift register SRi + 1 as an input and outputting an Ei signal; All the input signals except for inverting the output signal of SRi + 1 are input to the AND gate A1 and the AND gate A2 outputting the Ei signal is connected between the shift registers SRo and SRi And receives the inverted inverted signal of the AND gates A1 and A2 and the output inverted signal of the shift register SRi + 1 and the output inverted signal of the shift register SRo and the channel bit signal CHBr ' End to output 1 An output signal of the shift register SRi and an output signal of the shift register SRo and an output signal of the shift register SRo are supplied between the shift registers SRi and SRi + An AND gate A41 which receives the inverted signal of the signal CHBr as an input and outputs Ei +1 and an OR gate OR2 whose input receives the logical sum of the two AND gates A31 and A41 and the AND gate of the previous stage, Each connection of the following shift registers is connected between shift registers SRi and SRi + 1, such as A3, A4 and OR gate OR2.

That is, at each connection end of the shift registers, two AND gates and one OR gate are connected in the same manner as in the shift register SRi and the SRi + 1 connection end, and the input / .

The operation of the level slice controller constructed as described above with reference to FIG. 13 will now be described. First, the digital delay unit 60 calculates the nT time (T: channel bit period) of the high frequency reproduction signal DRFe * output from the digital equalizer of FIG. The high frequency reproduction signal DRFe of the delay signal (b) is input to the digital level comparator 102 together with the level slice reference signal DVref of (c) to output 1 when the high frequency reproduction signal DRFe is large, A channel bit signal CHBr is obtained by outputting "0" as shown in FIG. 4 (d), and a reproduced clock generating unit 80 generates a clock signal CL having a channel bit cycle of (a) Synchronously detects the channel bit from the channel bit signal CHBr and internally uses it as a reference clock signal.

Then, the shift register is output as shown in (e) by shifting by an increasing edge with the square-wave channel bit signal CHBr of the above (D) as an input, and the signal of (E) is shifted by the channel bit signal CHBr When the comparison is made in the exclusive OR gate of the state transition detection unit, it is possible to detect the state transition of the channel bit signal CHBr of the square wave of (d) through the same signal as in (V).

Further, the signal of (b) at the state transition time detected as described above is input to the reset terminal of the counter so as to count the rising edge of the reproduced clock CL after reset. This value is shown in (g) It is reset to 0 at the state transition point. 1 "of the decoded signal according to the distance to the first state change point appearing later appears in the decoded signal by the decoder 142. The signal of" 1 " As shown in FIG.

The reference signal DV0 ref of the level slice (c) is obtained by adding the previous control signal DVb controlled by the selection signal indicated by (a) and (b) to the subsequent control signal DVa and the digital control signal DVasy for correcting the asymmetry have.

That is, according to the present invention, a level of a reproduced high-frequency signal is compared based on an impulse signal according to an amount of interference by a pre- and post-signal, and zero crossing is performed to obtain a reproduced channel bit signal from which a jitter signal due to interference is removed. MSi, MSi ', ... stored in the storage element , MSn, MSN, MEi, MEi, ... , MEn, and Men 'by appropriately determining the digital data.

For a signal having a long pit signal or a signal having a large signal-to-pit distance indicating a low-frequency characteristic, a change in the influence is small. Therefore, the value of n may be reduced to about 8 without correction based on this change. In this case, The number can be reduced.

FIG. 14 illustrates a second embodiment of a level slice controller according to the present invention, which includes an address latch 150 for temporarily storing an address signal from a system controller, An address decoder 160 for decoding an address output from the drag latch 150 and outputting the address to the storage element is further connected to the level slice controller of the first embodiment.

Therefore, the storage elements RMSi, RMSi ', ..., RMSi constituting the first disk characteristic storage unit and the second disk characteristic storage unit , RMSn, RMSN ', RMEi, RMEi', ... , RMEn, and RMEn use a writable storage element, and RSi, RSi ', ..., RSi' output from the address decoder , RSn, RSn ', REi, REi', ... , REn, and REn 'signals.

To this end, as shown in FIG. 15, the optical disc recording and reproducing apparatus reproduces the RMSi, RMSi ',. , RMSn, RMSN ', RMEi, RMEi' ... , RMEn, and RMEn 'are tabulated, and the type of the disc is first determined. Then, RMSi, RMSi',. , RMSn, RMSN, RMEi, RMEi '... , RMEn and RMEn ', and records them in the respective storage elements.

According to the second embodiment, since the values stored in the storage element in the first embodiment are fixed, the control signal for controlling the level slice reference level can be changed according to the reproduction characteristics between the disks, It is possible to improve the compatibility as well as reduce the jitter.

FIG. 16 shows a third embodiment of the level slice controller according to the present invention. The phase comparator 170 is further connected to the first embodiment, and the state telephone detector 130 is provided with a shift register 132 And a shift register 133 for shifting 0.5 clocks are further connected to the first and second disk characteristic storing units, and the counters CMSi, CMSi ', ..., , CMSn, CMSN ', CMEi, CMEi', ... , CMEn and CMEn '. The phase comparator 170 includes an exclusive-OR gate 173 for exclusive ORing the reproduced channel bit signal and the signal delayed by the shift register 132 driven by the reproduction clock CL And outputs the output of the exclusive OR gate 173 as a clock signal. The output of the exclusive OR gate 173 is reset in accordance with the output of the exclusive OR gate 131 of the state transition detection unit 130, , ... , CMSn, CMEi, ... , CMEn's CMSi, ... , CMSn, CMEi, ... A counter 180 for inverting the output of the exclusive OR gate 173 and for outputting the counter CMSi, ..., CMEn to an increment / decrement input (up / down) , CMSn, CMEi, ... And an inverter 172 for applying a clock signal of CMEn to the clock signal.

The counter CMSi, ... , CMSn, CMEi, ... , And CMEn is an increment / decrement counter. In the counting method, if the signal controlling the polarity is "1" as shown in FIG. 17 (A), the output of the counter is counted in the increasing direction. If the phase of the reference clock is higher than the phase of the reference clock, the phase is controlled to be slower. If the phase of the reference clock is slower than the phase of the reference clock,

The D flip flop 171 outputs the reproduction clock signal CL as the input value D and outputs "0" if the edge of the channel bit signal is earlier than the reproduction clock as shown in (B) of FIG. 17, Quot; 1 "is output as the increase / decrease control signal of the counter.

The previous control signal DVa is generated by resetting the counter 141 by the pulse signal detected by delaying the output of the state change generating unit 130, that is, the state transition edge by one clock, and then decoding the counted value SO, Si, Si ', ... Sn, and Sn ', and the output of the shift register 133 of the status phone generation unit is input to the input E of the decoder 142 as a delimiter signal for distinguishing the shift from the pit to the land or the land to the pit, do.

On the other hand, the subsequent control signal DVb is supplied to the counters CMEi, CMEi ', ... , CMEn, CMEn 'are signals synchronized with the reproduction clock CL and decoded from the signal DRFe' nT time ahead of the high frequency reproduction signal DRFe as in the first embodiment. En '.

That is, in the third embodiment of the present invention, as shown in FIG. 18, when the high frequency reproduction signal DRFe level of (B) is larger than the level slice reference signal DVref of (C) The square wave of the rectangular wave of the state (D) can be seen. In the shift register, the square wave of the above (D) is inputted and the driving clock is changed to the reproduction clock CL And the output of the above (D) and (E) is subjected to the exclusive-OR operation so that the state transition point of the channel bit signal of (D) can be detected as shown in (V).

Then, the signal obtained by delaying the (e) signal and the (e) signal by a half reproduction clock through the shift register is subjected to exclusive OR operation to obtain a signal (b), which is obtained by resetting the counter Counting the rising edge of the reproduced clock CL of (a), the value of the counter becomes an increasing value, and is reset to 0 at the next state change point.

1 "of the decoded signal according to the distance to the first state change point appearing later becomes " 1 " The previous level control signal DVb and the subsequent level control signals DVa and DVasy are combined to obtain the level slice reference signal of (c). Also, the pulse signal that detects the state change of the channel bit signal that is normally reproduced is used as the clock signal CLK of the D flip-flop 171 of the phase comparator and the reproduced clock signal CL as the input D, (C) when the state transition detection signal of (b) is earlier than the reproduction clock signal CL of (a), and when the state transition detection signal of , CMSn, CMEi, ... , CMEn is used as a counting direction control signal, and a signal obtained by inverting (a) the state transition detection signal (b) is used as a counting signal, and +1 or - 1 is counted.

Therefore, according to the third embodiment, a square wave is formed so that the reference level of the comparator can be selected by detecting the distance from the state change point of the reproduced channel bit stream to the nearest preceding and succeeding state change point, It is possible to correct the n value which can not be corrected by the equalizer and the n value can be reduced to about 8 as in the other embodiments since the influence is small in the case of the low-pit long-pit signal.

FIG. 19 shows a fourth embodiment of the level slice controller according to the present invention. The level slice controller of the third embodiment includes a first disk characteristic storage unit 110, a first disk characteristic storage unit 110, The decoder 120 for selecting the counter is removed, and the influence of the post-signal is not considered.

According to the fourth embodiment, although the influence of jitter can not be eliminated completely, it can be reduced by half. Therefore, if the jitter can be suppressed only to a certain value or less, error correction is performed through the digital signal processing unit.

FIG. 20 shows a fifth embodiment of the level slice controller according to the present invention. In the fourth embodiment, the integration circuit for correcting asymmetry is eliminated.

This means that when controlling n = 11 in the CD or n = 14 in the DVD, each counter will perform the same function even if the same value is added or subtracted, only the control signal value to correct the asymmetry changes , It is possible to control the whole without using a control signal for correcting the asymmetry.

According to the fifth embodiment, besides reducing the jitter, the circuit can be greatly simplified.

FIG. 21 shows a sixth embodiment of the level slice controller according to the present invention, FIG. 22 shows a seventh embodiment of the level slice controller according to the present invention, and in the sixth embodiment, A reset input terminal is added to each counter of the first and second disk property storing units and reset by a microcomputer before reproduction. In the seventh embodiment, as in the sixth embodiment, each counter of the first and second disk characteristic storing units A preset value is preset by the microcomputer before the reproduction by adding a preset input terminal and a control signal for controlling the level slice reference level according to the reproduction characteristic between each disk by connecting the address latch and the address decoder as in the second embodiment, .

According to the sixth and seventh embodiments, it is possible to prevent the control values, which are completely different from the playback characteristics of the disc, from being recorded in the respective counters at the beginning of the playback.

As described above, according to the present invention, it is possible to limit and predict a control value for controlling the level slice reference according to the pit recorded on the disk to a finite cancellation value, to control the reproduction channel bit signal cycle, The influence of the jitter due to the interference of the before and after signals during reproduction of the optical disk is minimized by detecting the amount of interference between signals from the phase difference between the reference clock and the reproduced channel bit stream and controlling the reference voltage of the level slice circuit The reproduction performance is improved, and compatibility between the discs is improved.

Claims (19)

And a level slice control unit for controlling the reference level of the level slice to be a channel bit period of the reproduced signal in order to reduce the erasure caused by the interference of the before and after signals in the signal reproduction in the optical disc recording and reproducing apparatus, Record player. A digital level comparator for comparing a reproduced signal with a reference voltage level to detect a channel bit signal; a reproduction clock detecting unit for detecting a clock signal from the channel bit signal; And a level slice controller for controlling the level slice controller. The apparatus of claim 2, wherein the level slice controller comprises: a phase comparator for comparing the phase of the clock signal with the channel bit signal to detect an error; and a controller for controlling the reference voltage level according to a result of the phase comparison And the optical disc recording and reproducing apparatus. A state transition detecting section for detecting a state transition point from a reproduced channel bit signal and a reproduced clock signal detected from the channel bit signal; And a selector for selecting a reproduction characteristic value of the disc characteristic storage unit continuously and controlling the level slice reference level according to a turning point. 5. The apparatus according to claim 4, wherein the disc characteristic storage unit comprises: a first disc characteristic storage unit for storing a characteristic value of a signal reproduced first based on a reproduction point; a second disc characteristic storage unit for storing a characteristic value of a signal to be reproduced later; And a storage unit. 5. The optical disc recording and reproducing apparatus according to claim 4, wherein the disc characteristic storage unit comprises a plurality of recording elements. 5. The apparatus of claim 4, wherein the selector comprises a first selector for selecting each disk characteristic value of the first disk characteristic storage, and a second selector for selecting each disk characteristic value of the second disk characteristic storage Wherein said optical disc recording and reproducing apparatus comprises: 5. The apparatus of claim 4, wherein the status change detector comprises: a shift register for receiving the channel bit signal and delaying the channel bit signal by one period of the reproduced clock; and an output of the shift register delayed by one cycle of the channel bit signal and the reproduction clock, And an exclusive OR gate for performing an exclusive OR operation. The apparatus as claimed in claim 7, wherein the second selector comprises: a counter for counting the reproduction clock by using the output of the exclusive OR gate of the state transition detector as a reset signal; and a selector for selecting the output of the counter and the output of the shift register of the state transition detector And a decoder for decoding the input signal as an input signal. The apparatus of claim 9, wherein the decoder comprises: a plurality of shift registers (SR0 ... SRn-1) connected in a multistage, an inverter (I1) for inverting the output of the shift register (SRo) An output inverted signal of the shift register SRo and a channel bit signal CHBr 'and an input inverted signal of a shift register connected to the previous stage are inputted to the AND gate and the output signal of the shift register SRo and the channel bit signal CHBr And an AND gate for receiving the input signal of the shift register connected to the previous stage are connected in a pair and an OR gate for performing an AND operation on the outputs of the two AND gates and applying the result to the end gate connected to the next stage The optical disc recording / reproducing apparatus comprising: A state transition detector for detecting a state transition point from a reproduced channel bit signal and a reproduced clock signal detected from the channel bit signal; And a control unit for controlling the level slice reference level by selecting a playback characteristic value of the disc property storage unit continuously according to a state transition point detected by the state transition point detected by the state transition point detected by the state transition point detecting unit. An address latch for temporarily storing an address value output from the microcomputer; and an address decoder for decoding the address value inputted through the address latch, wherein the address decoder comprises: Optical disc recording Player. 12. The apparatus of claim 11, wherein the disc property storing unit comprises: a first disc property storing unit for storing a property value of a signal reproduced first based on a reproduction time point; a second disc property storing unit for storing a property value of a signal to be reproduced later; And a storage unit. 12. The apparatus of claim 11, wherein the disc characteristic storage unit comprises a first disc characteristic storage unit for storing one of a characteristic value of a signal reproduced first or a characteristic value of a signal to be reproduced later on the basis of a reproduction time point Optical disc recording and reproducing apparatus. A state transition detector for detecting a state transition point from a reproduced channel bit signal and a reproduction click signal detected from the channel bit signal; A selector for selecting a reproduction characteristic value of the disc characteristic storage unit continuously in accordance with a state transition point detected by the state transition point detected by the state transition point detecting unit and comparing the phase of the reproduction click and the state transition edge of the channel bit signal And a phase comparator for adjusting a stored value of the disc characteristic storage unit. 15. The optical disc recording and reproducing apparatus as claimed in claim 14, wherein the disc property storing unit comprises a plurality of counters for increasing or decreasing a count value according to a polarity. 15. The apparatus of claim 14, wherein the disc property storing unit includes: a first disc property storing unit for storing a specific value of a signal reproduced first based on a reproduction starting point; a second disc property storing unit for storing a characteristic value of a signal to be reproduced later; And an optical disc recording and reproducing unit. 15. The apparatus of claim 14, wherein the disc characteristic storage unit comprises a first disc characteristic storage unit for storing either a characteristic value of a signal reproduced first or a characteristic value of a signal to be reproduced first based on a reproduction time point Optical disc recording and reproducing apparatus. 15. The apparatus of claim 14, wherein the status change detector comprises: a first shift register for receiving the channel bit signal and delaying the channel bit signal by one period of the reproduced clock; and a second shift register for delaying the output of the shift register by 0.5 cycle 2 shift register and an exclusive-OR gate for exclusive-ORing the output of the first shift register and the output of the second shift register. 16. The optical disc recording and reproducing apparatus according to claim 15, wherein the counter is further configured to attach a reset terminal to reset or set a desired value according to the disc. ※ Note: It is disclosed by the contents of the first application.