JPH0684119A - Disc apparatus - Google Patents

Abstract

PURPOSE:To positively detect the data in a disc of a fixed magnetic disc apparatus. CONSTITUTION:A differential circuit 18 is provided at the output stage of a head 3. A pulse indicating a peak of the read output waveform is formed based on the differential waveform. A gate pulse is formed by comparators 32, 33, and a read pulse is produced by an AND of the detecting pulse of the peak and the gate pulse. When a read error is detected, a reference voltage of the comparators 32, 33 is switched and the data is read again (re-tried).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fixed magnetic disk device (HDD) or a disk device similar thereto, and more particularly to a disk device capable of reliably detecting data.

[0002]

2. Description of the Related Art A recording medium disk of a fixed magnetic disk device has a large number of tracks (cylinders), and a predetermined track format is written in advance on each track. The track format includes a number of sectors, each sector including an ID field and a data field. CRC (Cyclic Redundancy)
Check) data and ECC (Error Correction Code)
Since the data is written, CRC data and EC
An error check can be performed based on the C data. When an uncorrectable error is detected, the error sector is reread (retry).

[0003]

However, when the peak shift of the read output waveform is significantly generated, or when the waveform distortion is significantly generated, or the amplitude is significantly reduced due to a defect or recording defect of the disk. If it occurs, it becomes impossible to read the data accurately even if it is retried.

Therefore, it is an object of the present invention to provide a disk device which can read data accurately.

[0005]

The present invention for achieving the above object provides a disk apparatus for reading data from a recording medium disk in which data is written in a track including a plurality of sectors. A disc rotation means, a reading means for reading the data written on the disc, and a differentiating circuit coupled to the reading means for differentiating a read output waveform obtained from the reading means. And when the differential output obtained from the differential circuit crosses a reference voltage level approximately halfway between the maximum value (peak value) and the minimum value (valley value) of the differential output. A peak detection pulse forming circuit that forms a peak detection pulse indicating the peak of the read output waveform in synchronization with the normal read output waveform obtained from the reading means. Reference voltage generating means for selectively generating a plurality of reference voltages having different voltage levels set between the peak level and the reference voltage level, and one input terminal coupled to the signal reading means and the other An input terminal is coupled to the voltage comparing means coupled to the reference voltage generating means, the peak detection pulse forming circuit and the voltage comparing means, and the read output waveform obtained from the voltage comparing means indicates the reference voltage. Read pulse forming means formed so as to output a read pulse corresponding to the peak detection pulse only when the peak detection pulse is positioned in the period of the output pulse indicating that the read pulse is formed, and the read pulse forming means. An error detection unit that is coupled to, and detects whether or not the data is read without error based on the read pulse, In response to a signal indicating the error obtained from the error detecting means, the scanning by the reading means is controlled so as to reread the data of at least the sector in which the error has occurred, and at the time of the rereading, the scanning is controlled. The present invention relates to a disk device having a control means for controlling the level of the reference voltage so that the time width of the reference voltage crossing the read output waveform becomes long. It should be noted that, as described in claim 2, it can be configured to obtain a normal phase reading output and a negative phase reading output, and to obtain respective differential outputs.

[0006]

In the present invention, the output pulse of the voltage comparing means is used to judge whether or not the peak detection pulse obtained based on the differentiating means is a signal showing a true peak. That is, only when the peak detection pulse is generated within the period of the output pulse of the comparison means, the true peak is determined. Therefore, false peaks due to noise or the like are excluded. The presence or absence and the width of the output pulse (gate pulse) of the comparison means depend on the read output waveform. If the read output waveform does not cross the reference voltage, no output pulse (gate pulse) is generated. If the output pulse (gate pulse) is not generated from the comparison means, it becomes impossible to determine whether or not the peak detection pulse is the true peak, and the read pulse corresponding to the peak detection pulse is not generated. As a result, the error detecting means produces an output indicating an error. In the present invention, when an error is detected, a comparison output pulse (gate pulse) can be obtained and the width of the output pulse (gate pulse) of the comparison means can be widened even if the read output waveform has a low amplitude. The reference voltage is controlled so that As a result, even if the read output waveform has a low amplitude, a comparison output pulse (gate pulse) can be obtained and a read pulse can be obtained. Further, even if the peak detection pulse is deviated on the time axis, it can be detected.

[0007]

First Embodiment Next, a fixed magnetic disk device according to an embodiment of the present invention will be described with reference to FIGS. In FIG. 1, a recording medium magnetic disk 1 is non-detachably coupled to a disk motor 2. Motor 2 is disk 1
Rotate at high speed and constant speed. The magnetic head 3 as a reading means is composed of a core 4 and a coil 5, and is supported by an arm 6. The head 3 at the tip of the arm 6 is attached to the disk 1
The arm 6 is connected to a head moving device 7 for moving the arm 6 in the radial direction of the position and positioning it on a predetermined track.

The disk 1 has a large number of concentric tracks (cylinders) 8, and data is recorded on each track 8 according to a predetermined track format. There are many formats for one track (43 in this example)
2, each sector 9 includes an ID field 10 and a data field 11 as schematically shown in FIG. 2, and the ID field 10 includes the address signal recording area 1
2 and a CRC data recording area 13 are provided. The data field 11 is provided with a main data (information) recording area 14 and an ECC data recording area 15. In addition to FIG. 2, one sector 9 is provided with a region and a gap in which a signal for tracking servo, a synchronizing signal, etc. are written, but these are omitted in the drawing.

Referring again to FIG. 1, the coil 5 of the head 3 is connected to a differential amplifier circuit 16 as a differential signal output means. Since the relative scanning motion is generated between the disk 1 and the head 3, the pair of output lines 17a and 17b of the differential amplifier circuit 16 has the positive phase read output waveform shown in FIG. The reverse phase read output waveform shown in FIG. 5A and 5B, the output of 4-bit logic "1" is shown in principle.

A pair of output lines 17 of the differential amplifier circuit 16
The differential type differentiating circuit 18 coupled to a and 17b is shown in FIG.
The positive phase and negative phase read output waveforms shown in (A) and (B) are respectively differentiated, and the positive phase and negative phase differential outputs shown in (C) and (D) of FIG. 5 are output to the pair of output lines 19a and 19b. . The waveforms shown in FIGS. 5A to 5D are waveforms that oscillate around the DC reference voltage level (2V) L0. This reference voltage level L0 is the center value between the maximum value (peak value) and the minimum value (valley value) of each waveform.

A pair of output lines 19a of the differentiating circuit 18,
The peak detection pulse forming circuit 20 coupled to 19b is generally called a zero-cross detection circuit, and is shown in FIG.
(C) Detects the time point when the positive and negative phase differential outputs shown in (D) cross the reference voltage level L0, and generates the peak detection pulse shown in FIG. It is a thing.

FIG. 3 shows the differentiating circuit 18 and the peak detection pulse forming circuit 20 of FIG. 1 in principle, and FIG. 6 shows A to A of FIG.
The state at point G is shown. The differentiating circuit 18 includes a differential amplifier 22,
It is configured by a combination of a time constant circuit of a resistor 23 and a capacitor 24. Peak detection pulse forming circuit 20
Is the first and second peak detection comparators 25, 2
6, a reference voltage source 27 as a peak detection reference voltage level giving means, and a peak detection pulse generation circuit 28. The peak detection pulse generation circuit 28 is composed of a pair of mono-multivibrators (MMV) 29, 30 and an OR gate 31. First peak detection comparator 2
One input terminal of 5 is connected to one differential output line 19 a, and the other input terminal is connected to the reference voltage source 27. Therefore, the first peak detecting comparator 25 compares the differential output a of the line 19a shown in FIG. 6A with the reference voltage level L0 of the reference voltage source 27, and the differential output a crosses the reference voltage level L0. Generate the comparison output pulse of FIG. 6C having a pulse width corresponding to Also,
The second peak detecting comparator 26 is provided with the negative phase differential output b of the line 19b and the reference voltage level L0 shown in FIG. 6 (B).
Are compared with each other to generate a comparison output pulse shown in FIG. The pair of MMVs 29 and 30 connected to the pair of comparators 25 and 26 output the pulses shown in FIGS. 6E and 6F in synchronization with the leading edge of the comparison output pulse of FIGS. 6C and 6D. . OR gate 31 connected to MMVs 29 and 30
Sends the pulse of FIG. 6 (G) corresponding to the pulse of FIG. 6 (E) (F) to the line 21. 6A and 6B are shown in FIG.
It corresponds to (C) and (D), and FIG. 6 (G) corresponds to FIG. 5 (E). . The pulses in FIGS. 5 (E) and 6 (G) are shown in FIG.
Since it occurs corresponding to the peaks of the read output waveforms of (A) and (B), it can be called a peak detection pulse.

Referring again to FIG. 1, a positive phase comparator 32 and a negative phase comparator 33 are provided as comparison means for forming a gate pulse. One input terminal of each of the positive-phase and negative-phase comparators 32 and 33 is connected to the normal-phase and negative-phase reading output lines 17a and 17b, and the other input terminal is connected to the voltage dividing point 35 of the reference voltage generating means 34. There is. The reference voltage generating means is a first and a second connected between the DC power supply terminal 36 and the ground.
Of the resistors R1 and R2 and the switch S to the first resistor R1.
And a third resistor R3 connected in parallel via 1. The switch S1 consists of a controllable electronic switch,
Based on the control by the control circuit 37, it is selectively turned on / off to change the voltage division ratio. As a result, the first and second reference voltages L1 and L2 having different levels are obtained at the voltage dividing point 35. The switching of the reference voltage is carried out at the time of detecting the lead error of the data, as will be apparent from the following.

7 (A) and 7 (B) show the positive and negative phase read output waveforms and the first and second reference voltages L1, L2,
Shows the relationship with. The first and second reference voltages L1 and L2 are set between the peak value of the normally read output waveform and the reference voltage level L0. The pulse shown by the solid line in FIGS. 7C and 7D shows the comparison output pulse of the first reference voltage L1 and the read output waveform, and the broken line shows the second reference voltage L1.
2 shows the comparison output pulse of 2 and the read output waveform. By changing the reference voltages L1 and L2, the time width of the comparison output pulse changes like T1 and T2. When the first reference voltage L1 is obtained, the switch S1 is turned on and the second reference voltage L1 is turned on.
The switch S1 is turned off to obtain the reference voltage L2.

The gate pulse output circuit 38 connected to the comparators 32 and 33 is composed of an OR gate, and the gate pulse output circuit 38 shown in FIG.
The gate pulse of FIG. 5H, which is a combination of both the positive-phase and negative-phase comparison output pulses (gate pulse) of (F) and (G), is output to the line 39.

The read pulse forming means 40 comprises an AND gate 41 and an MMV 42, one input terminal of the AND gate 41 is connected to the peak detection pulse output line 21, and the other input terminal thereof is the gate pulse output line 39.
It is connected to the. Therefore, the AND gate 41 is shown in FIG.
A high level pulse is generated as shown in FIG. 5 (I) only when the peak detection pulse of (E) and the gate pulse of FIG. 5 (H) are generated at the same time. The MMV 42 connected to the AND gate 41 sends a read pulse having a constant pulse width to the output line 43 in synchronization with the leading edge of the read pulse shown in FIG.

The control circuit 37 executes various controls of the disk device. A read pulse output line 43 and a read data output line 44 are connected to the control circuit 37, and write (write) is performed via a write control line 45. )
The head moving device 7 is connected to the switch S1 via the circuit 47 and the line 48 and via the line 50.

FIG. 4 schematically shows the control circuit 37 of FIG. The control circuit 37 includes a PLL (phase lock loop) circuit 51. This PLL circuit 5
1 is a phase comparator 52 and a low-pass filter (LPF) 53
And a VCO (voltage controlled oscillator) 54. One input terminal of the phase comparator 52 has a read pulse output line 43.
And the other input terminal is connected to the VCO 54. A pulse train having a period corresponding to the arrangement period of the bit cells is obtained on the output line 55 of the PLL circuit 51 by a well-known principle.

The decoder 56 shown in FIG. 4 is connected to the line 43, and the column supplied from the line 43 is, for example, 1-7RL.
The data modulated in the L system or the MFM system is demodulated in the NRZ system.

A clock generator 57 is connected to the decoder 56 in order to execute the demodulation. The clock generator 57 is connected to the output line 55 of the PLL circuit 51,
A first clock signal is provided on line 57a to decoder 56 based on the pulse on line 55 having a period corresponding to the bit cell. Also, the clock generator 57 is line 57
A second clock signal consisting of a standard clock is applied to the error check and correction circuit 58 by b.

The error check and correction circuit 58 is a decoder.
Connected to the clock 56 and the clock generator 57,
The presence or absence of data error is detected. That is, the presence or absence of a read error is detected based on the CRC data and the ECC data, and the correctable read data is corrected based on the ECC data.

The microcomputer 59 is a CPU, RA
It has M and ROM, and executes various controls. In addition to the error check and correction circuit 58 being connected to the microcomputer 59, a write control line 45, a head movement control line 50, and a switch control line 61 are connected.

An error is detected by the error check and correction circuit 58.
The read data, which has been checked and corrected if necessary, is sent out on line 44. A buffer memory is generally connected to the line 44.

The switch control circuit 63 follows the instruction of the microcomputer 59 when the error is detected by the error check and correction circuit 58 and the switch S of FIG.
Generates a signal that turns on 1. The actual control circuit 37 has many circuits and lines other than the illustrated circuits and lines, but these are omitted because they are not directly related to the present invention.

Next, the effect of changing the reference voltage given from the reference voltage generating means 34 at the time of retry (rereading) based on the error detection will be described. If Figure 5
As shown in FIGS. 7A and 7B and FIGS. 7A and 7B, when the read output waveforms of normal amplitude are obtained on the lines 17a and 17b, the data is read at the standard first reference voltage L1. The lead of can be fully achieved. On the other hand, when the read output waveform of the line 17a includes the low amplitude portions a1 and a2 as shown in FIG. 8A because the disk 1 has a defective portion, the first reference voltage is the same as in the conventional case. When the read output waveform at L1 is sliced by the comparator 32, the low-amplitude portion a1 does not cross the first reference voltage L1 and a gate pulse cannot be obtained. If the gate pulse does not occur at the place where the gate pulse should originally occur, the read pulse cannot be obtained, and reading of this sector becomes impossible. On the other hand, in this embodiment, the data is read by the second reference voltage L2 at the time of retry. In FIG. 8A, the low-amplitude portion a1 crosses the second reference voltage L2, so that a gate pulse can be obtained. As a result, it becomes possible to read the data which could not be read conventionally. In addition, FIG. 8 (A)
When the level of the reference voltage is switched to L2 during the retry, the time width of the read output waveform crossing the reference voltage L2, that is, the width of the gate pulse becomes wider. Even if there is a shift on the time axis of the peak detection pulse of FIG. 5 (E) or FIG. 6 (G) generated based on the differentiation, the peak detection pulse of the wide gate pulse It becomes possible to detect.

If the reference voltage is always set to L2, the original gate function of the gate pulse deteriorates. For example, when the pseudo peak P exists as shown in FIG. 9A, the low reference voltage L2 causes the gate pulse to be divided as shown in FIG. If there is a shift on the time axis of, the read pulse may be divided. Therefore, it is desirable to switch the reference voltage at the time of retry.

FIG. 10 shows a procedure for reading track data. After the start of block 70, the data is read as shown in block 71. Next, as shown in block 72, the presence or absence of an error is determined based on the CRC data and the ECC data. The determination of the presence or absence of this error is performed in sector units. If an error is detected, the number of error detections is counted by the counter at block 73. Next, at block 74, the number of error detections is a predetermined number N (for example, 5).
It is determined whether or not the number of times has reached N), and when the number of times has not reached N, the reference voltage is set to L2 in block 75 and block 7
After returning to 1, the error sector is read again. Block 7
If no error is detected at 2, the process ends as indicated by block 76. When the block 74 detects N errors, a block 77 creates a signal indicating that the read is impossible. If the read is not possible, retry by another method (condition), skip this sector and proceed to the next sector, or interrupt the read. In addition, retry
When the tread is possible, the reference voltage is returned to L1 and the next sector is read.

[0028]

[Second Embodiment] Next, a fixed magnetic disk drive according to a second embodiment will be described with reference to FIGS. However,
11, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 11, only the positive phase output line 17 a of the amplifier circuit 16 is connected to the differentiating circuit 18. The differentiating circuit 18 differentiates the positive-phase read output waveform of FIG. 12A to generate the differential output of FIG. 12B on the output line 19a. The peak detection pulse forming circuit 20 is composed of one comparator and an edge detecting circuit. The comparator detects the differential output of FIG. 12B and the reference voltage level L0 and shapes it into a square wave pulse. It is configured to generate the peak detection pulse shown in FIG. 12C at the leading edge and the trailing edge of the pulse.

One comparator 32 for gate pulse
Are connected in the same way as in FIG. One input terminal of the other comparator 33 for gate pulse is connected to the read output line 17a, and the other input terminal is connected to the second reference voltage generating means 34a. The second reference voltage generating means 34a is similar to the first reference voltage generating means 34 and provides two reference voltages L1 'and L2' lower than the reference voltage level L0 shown in FIG. L1 ',
L2 'is set to have symmetrical values with respect to L1 and L2 with L0 as the center, and can be obtained with the same circuit configuration as the first reference voltage generating means 34. As a result, the comparator 3
The same pulses as those in FIGS. 5F and 5G can be obtained from 2 and 33, and the gate pulse shown in FIG. 12D can be obtained from the gate pulse output circuit 38. FIG. 12 (C)
Since (D) corresponds to (E) and (H) of FIG. 5, the same effect as that of FIG. 1 can be obtained by the device of FIG.

[0030]

[Third Embodiment] FIGS. 13 and 14 show a part of a disk device according to the third embodiment and its operation. The third embodiment is the same as the first embodiment except that the inputs of the comparators 32 and 33 and the reference voltage generating means 34 of the first embodiment are slightly changed. Therefore, only the changes will be described.

Lines 17a and 17b in FIG. 13 are the same as the output lines 17a and 17b of the differential amplifier circuit 16 in FIG. The lines 17a and 17b are not directly connected to the input terminals of one of the two comparators 32 and 33, but are connected to each other via the DC bias addition differential amplifier circuit 90. The output lines 91 and 92 are shown in FIG.
The positive-phase and negative-phase bias addition waveforms shown in (B) are obtained. The reference voltage generating means 34 'is configured by adding a differential amplifier 93, a full wave rectifying circuit 94, and a bias adding circuit 95 to the reference voltage generating circuit 34 of FIG.
The differential amplifier 93 is connected to the lines 91 and 92, as shown in FIG.
The outputs of the waveform differences of (A) and (B) are formed. When this is full-wave rectified and further applied to the terminal 36 through the bias applying circuit 95, the reference voltage including the AC component shown in FIG. 14C is obtained at the voltage dividing point 35. This reference voltage is switched to L11 or L12 by the switch S1 as in FIG. When the reference voltages L11 and L12 are switched, the comparator 3
The gate pulse generation conditions of Nos. 2 and 33 are changed, and the same effects as those of the first embodiment can be obtained. In addition, in FIG.
Resistor R3 is connected in parallel to the second resistor R2 via switch S1.

[0032]

MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible. (1) Instead of the MMVs 29 and 30 of FIG. 3, a differentiating circuit may be provided to form a pulse synchronized with the leading edges of the output pulses of the comparators 25 and 26. Further, the differentiating circuit 18 of FIG. 3 can be two independent positive-phase and negative-phase differentiating circuits. (2) Reference voltage generating means 3 shown in FIGS. 1, 11 and 13
4, 34a, 34 'are configured by a combination of a digital reference voltage generating circuit 80 and a DAC (digital / analog converter) 81 as shown in FIG. 15, and the digital reference voltage is changed at the time of retry to change the output voltage of the DAC 81 ( The reference voltage) can be changed. (3) Instead of the switch S1 of the voltage dividing circuit of the reference voltage generating means 34 'shown in FIG. 13, the inverter 82 shown in FIG. 16 can be used. (4) The reference voltage can be switched in three or more stages. (5) In each embodiment, the output waveform of the amplifier circuit 16 and the output waveform of the differentiating circuit 18 are shown to oscillate up and down around the reference voltage level of DC 2V. May oscillate with zero volts as the reference voltage. (6) CR instead of ECC data
Error using C data and parity check bit
It may be checked and corrected. (7) The present invention can be applied to a magneto-optical disk device, a floppy disk device and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing a fixed magnetic disk device according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a format of tracks on a disc.

FIG. 3 is a diagram showing in detail the differentiating circuit and the peak detection pulse forming circuit of FIG.

FIG. 4 is a block diagram schematically showing the control circuit of FIG. 1.

5 is a waveform diagram showing voltages at points A to J in FIG.

6 is a waveform diagram showing voltages at points A to G in FIG.

7 is a waveform diagram showing the inputs and outputs of the two comparators for the gate pulse of FIG.

8 is a waveform diagram showing the input and output and the read pulse of the positive phase comparator of FIG. 1 when the read output waveform includes a low amplitude portion.

FIG. 9 is a waveform diagram showing the input and output of the positive phase comparator and the read pulse when the read output waveform includes a pseudo peak.

FIG. 10 is a diagram showing a procedure for lead error detection.

FIG. 11 is a block diagram showing a fixed magnetic disk device of a second embodiment.

12 is a waveform diagram showing voltages at points A to D in FIG.

FIG. 13 is a block diagram showing a part of a fixed magnetic disk device of a third embodiment.

FIG. 14 is a waveform diagram showing voltages at points A to E in FIG.

FIG. 15 is a circuit diagram showing a reference voltage generating means of a modified example.

FIG. 16 is a circuit diagram showing a reference voltage generating means of another modification.

[Explanation of symbols]

 32, 33 comparator 34 reference voltage generating means S1 switch

Claims (2)

[Claims] 1. A disk device for reading the data from a recording medium disk in which the data is written in a track including a plurality of sectors, wherein the disk rotating means and the disk write means write the data in the disk. Read means for reading the data, a differentiation circuit coupled to the reading means and differentiating the read output waveform obtained from the reading means, and a differentiation circuit coupled to the differentiation circuit and obtained from the differentiation circuit. A peak detection pulse forming circuit that forms a peak detection pulse indicating a peak of the read output waveform in synchronization with a time point when the differentiated output crosses a reference voltage level approximately halfway between the maximum value and the minimum value of the differentiated output; A voltage level set between the peak level in the normal read output waveform obtained from the reading means and the reference voltage level. Reference voltage generating means for selectively generating a plurality of different reference voltages; voltage comparing means having one input terminal coupled to the signal reading means and the other input terminal coupled to the reference voltage generating means; The peak detection pulse is located in the period of the output pulse which is coupled to the peak detection pulse forming circuit and the voltage comparison means and indicates that the read output waveform obtained from the voltage comparison means crosses the reference voltage. And a read pulse forming means formed so as to output a read pulse corresponding to the peak detection pulse only when the read pulse forming means is connected to the read pulse forming means. An error detecting means for detecting whether or not it has been read, and at least in response to a signal indicating the error obtained from the error detecting means. The scanning by the reading means is controlled so as to re-read the data of the sector in which an error has occurred, and the reference voltage is set so that the time width during which the reference voltage crosses the read output waveform becomes long during the re-reading. Disk device having a control means for controlling the level of the disk. 2. The disk is a magnetic disk, the reading means comprises a magnetic head and a means for outputting a differential signal from the magnetic head, and the differentiating circuit is a positive signal obtained from the differential signal output means. A circuit having first and second output terminals for respectively forming and outputting a differential output of a phase reading output and a negative phase reading output, wherein the peak detection pulse forming circuit is for applying the reference voltage level. Peak detection reference voltage level applying means, a first peak detection comparator coupled to the first output terminal and the peak detection reference voltage level applying means, the second output terminal and the beak detection A second peak detecting comparator coupled to the reference voltage level applying means, and the first peak detecting comparator and the second peak detecting comparator, And a peak detection pulse generation circuit for generating a peak detection pulse indicating a peak of the positive phase and negative phase read outputs in synchronism with the leading edges of the output pulses of the first and second peak detection comparators. The voltage comparison means has a positive phase comparator having one input terminal coupled to the positive phase output terminal of the differential signal output means and the other input terminal coupled to the reference voltage generation means, and one input terminal. 2. The disk device according to claim 1, wherein the differential signal output means is connected to a reverse phase output terminal, and the other input terminal is a reverse phase comparator connected to the reference voltage generating means.