JPH06176503A - Disk device - Google Patents

Abstract

PURPOSE:To surely detect data on a disk of a fixed magnetic disk device. CONSTITUTION:A read pulse forming circuit 18 is connected to a PLL circuit 24, where a data window pulse is formed. A variable delay circuit 27 is connected between the PLL circuit 24 and a data pulse extracting circuit 25. The data window pulse is shifted by changing a delay time of the variable delay circuit 27 at the time of retrying based on a data error, so that the data pulse is tried to be extracted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fixed magnetic disk device (HDD) or a disk device similar thereto, and more particularly to a disk device capable of surely detecting data.

[0002]

2. Description of the Related Art A recording medium disk of a fixed magnetic disk device has a large number of tracks (cylinders), and a predetermined track format is written in advance on each track. The track format includes a number of sectors, each sector including an ID field and a data field. ECC (Error Correction Co
de) data or CRC (Cyclic Redundancy Check)
Since the data and parity bits are written, error checking and error correction can be performed based on the ECC data or CRC data and parity bits. When an uncorrectable error is detected, the error sector is read again (retry). However, even if the peak shift of the read output waveform is significantly generated, or if the waveform distortion is significantly generated, or if the amplitude is significantly decreased due to a defect or recording defect of the disk, a retry is performed. It becomes impossible to read the data accurately.

Therefore, it is an object of the present invention to provide a disk device which can read data accurately.

[0004]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a plurality of sectors included in a track.
The main data and the error from the recording medium disc in which the main data composed of a plurality of bits and the error check data composed of a single bit or a plurality of bits for checking a read error of the main data are written according to an array of bit cells of a predetermined time A disc device for reading check data to obtain an output corresponding to the main data, the reading device for reading the main data and the error check data from the disc; Based on the output of the reading means corresponding to the data and the error check data, a read pulse train in which the data pulses corresponding to the main data and the error check data are respectively arranged in the center of a plurality of bit cells arranged in series. Forming lead pulse A data window pulse coupled to a circuit and the read pulse forming circuit, each having a first value corresponding to a central region of the plurality of bit cells and having a second value between the central regions. A data window pulse forming circuit formed based on a pulse train, a data pulse extraction coupled to the read pulse forming circuit and the data window pulse forming circuit, and extracting the data pulse of the read pulse train based on the data window pulse A circuit and a data pulse extraction circuit, and obtains reproduction main data and reproduction error check data corresponding to the main data and the error check data recorded on the disc based on the data pulse, and the reproduction main Based on the playback error check data In response to a signal indicating an error obtained from the error detection means, a position shift means for changing the relative positional relationship between the read pulse train and the data window pulse on the time axis. Control means for controlling the reading means so as to read again at least the sector in which an error has occurred, and for controlling the position shifting means so as to change the position on the time axis of the data window pulse relative to the read pulse train. The present invention relates to a disk device equipped with.

[0005]

The operation and effect of the invention is as follows.
Acts as a window for extracting data.
In the present invention, when a read error occurs, the data window pulse is shifted relative to the read pulse on the time axis, or the read pulse is shifted relative to the data window pulse on the time axis. As a result, there is a possibility of extracting the data pulse that could not be extracted due to the peak shift, and the probability of occurrence of the read error decreases.

[0006]

First Embodiment Next, a fixed magnetic disk device according to an embodiment of the present invention will be described with reference to FIGS. Figure 1
In, the recording medium magnetic disk 1 is non-detachably coupled to the disk motor 2. The motor 2 rotates the disk 1 at a high speed and at a constant speed. The magnetic head 3 as a reading means is composed of a core 4 and a coil 5, and is supported by an arm 6. The arm 6 is coupled to a head moving device 7 for moving the head 3 at the tip of the arm 6 in the radial direction of the disk 1 and positioning it on a predetermined track.

The disk 1 has a large number of concentric tracks (cylinders) 8, and data is recorded on each track 8 according to a predetermined track format. There are many formats for one track (43 in this example)
2, each sector 9 includes an ID field 10 and a data field 11 as schematically shown in FIG. 2, and the ID field 10 includes an address signal recording area 12
And a CRC data recording area 13 are provided. The data field 11 is provided with a main data (information) recording area 14 and a CRC recording area 15. In addition to FIG. 2, one sector 9 is provided with a region and a gap in which a signal for tracking servo, a synchronizing signal, etc. are written, but these are omitted in the drawing. The track format and the main data are written in the MFM system, and are accompanied by clock information. A parity bit (check bit) is added to each data.

Referring again to FIG. 1, the coil 5 of the head 3 is connected to the differential amplifier circuit 16 as the differential signal output means and also to the write circuit WT. The relative scanning motion between the disk 1 and the head 3 causes a pair of output lines 17 a, 17 of the differential amplifier circuit 16.
In FIG. 5B, the normal phase read output waveform shown in FIG. 5A and the reverse phase read output waveform shown in FIG. 5B which is the phase inversion waveform are obtained. In FIGS. 5A and 5B, the output of 4-bit logic "1" of the MFM method is shown in principle.

The read pulse forming circuit 18 coupled to the differential output lines 17a and 17b detects the peak of the waveforms of FIGS. 5A and 5B and outputs the read pulse detected at this peak. The peaks of the waveforms in FIGS. 5A and 5B correspond to the magnetization reversal positions on the disk 1. As shown in FIG. 3, the read pulse forming circuit 18 of FIG. 1 includes a differential type differentiating circuit 19, a zero cross detection pulse forming circuit 20,
Gate pulse forming circuit 21, AND gate 22, M
And an MV (mono multivibrator) 23. The differential type differentiating circuit 19 differentiates the positive-phase and negative-phase read output waveforms shown in FIGS. 5A and 5B, respectively, and FIGS.
The positive phase and negative phase differential outputs shown in FIG.
a and 19b. The zero cross detection pulse forming circuit 20 coupled to the pair of output lines 19a and 19b of the differentiating circuit 19 includes a zero cross comparator.
(C) Detects a time point at which the positive-phase and negative-phase differential outputs shown in (D) cross zero or a reference voltage level in the vicinity thereof, and generates a zero-crossing detection pulse shown in FIG. To do. Since the zero cross of the differential output in FIGS. 5C and 5D corresponds to the peak of the read output waveform in FIGS. 5A and 5B, the pulse in FIG. 5E is called a peak detection pulse. You can also Gate pulse forming circuit 2 connected to the pair of read output lines 17a and 17b
Reference numeral 1 includes a pair of comparators and slices the read output waveforms of FIGS. 5A and 5B to generate a gate pulse including the vicinity of the peak as shown in FIG. 5F. The AND gate 22 is connected to the zero-cross detection pulse forming circuit 20 and the gate pulse forming circuit 21 and generates a coincident output of both pulses. This enables highly accurate peak detection (zero cross detection). MMV23 is AND gate 2
It is triggered by the output of 2 and generates a read pulse having a constant time width as shown in FIG.

Referring again to FIG. 1, the read pulse forming circuit 18 is connected with a PLL (phase lock loop) circuit 24, a data pulse extracting circuit 25 and a clock pulse extracting circuit 26 as a data window pulse forming circuit. There is. The PLL circuit 24 is connected to the data pulse extraction circuit 25 and the clock pulse extraction circuit 26 via the variable delay circuit 27 as the shift means according to the present invention. When a read pulse of the MFM method shown in FIG. 6A is generated from the read pulse forming circuit 18, the PLL circuit 24 generates a data window pulse shown in FIG. 6B in response to this. This data window pulse is input to the data pulse extraction circuit 25 via the variable delay circuit 27 as the shift means. The data pulse Pd included in the read pulse of FIG.
Data is extracted as shown in FIG. 6C by the data extraction circuit 25 including a gate. Further, the data window pulse is inverted by the inverter (NOT circuit) 28 and becomes the clock window pulse of FIG. 6 (D), which is input to the clock pulse extraction circuit 26. The clock pulse extraction circuit 26 extracts the clock pulse Pc included in the read pulse train of FIG. 6A and outputs the clock pulse train of FIG. 6E.

The read data (RD) forming circuit 29 is shown in FIG.
Read data corresponding to the read pulse Pd of (C) is formed. The clock (CK) forming circuit 30 forms a clock corresponding to the clock pulse Pc of FIG. 6 (E).

The ECC circuit (error check and correction circuit) 31 is connected to the data forming circuit 29 and the clock forming circuit 30 and detects a data error by a CRC check and a parity check of the read data. Also, correctable data is corrected based on the parity bit. The read data is output line 32 of the ECC circuit 31.
Can be obtained. Normally, the read data on the line 32 is output via a buffer memory (not shown). When the ECC circuit 31 detects a data error, it notifies the microcomputer 34 as a controller of an error detection signal through a line 33.

The microcomputer 34 controls the head moving device 7 so as to retry (reread) the error sector in response to the error detection signal, and changes the delay time of the variable delay circuit 27 connected via the line 35. .

FIG. 4 shows the data window pulse forming PLL circuit 24 and the variable delay circuit 27 of FIG. 1 in detail. P
The LL circuit 24 includes a phase comparator 41 and a low pass filter (L
PF) 42 and VCO (voltage controlled oscillator) 43, one input terminal of the phase comparator 41 is connected to the read pulse output line 18a, and the other input terminal is VCO4.
Connected to 3. Since the MFM read pulse train includes clock information, a data window pulse for extracting the data pulse Pd included in the read pulse train is generated at a predetermined cycle on the output line 44 of the PLL circuit 24 by a well-known principle. .

The variable delay circuit 27 comprises a series circuit of a plurality of inverters 45a, 45b, 45c ... 45n as delay elements, and switches S1, S2 ... Sn connected in parallel to the inverters 45a-45n. Switch S1 ~
The microcomputer 34 selectively turns on and off Sn.
Each of the inverters 45a to 45n is used as a delay element having a delay time of about 1.3 ns. During normal reading, only a switch of the n switches S1 to Sn is turned off to obtain a constant delay time Ta. This delay time Ta is set to position the data window pulse in the center of the bit cell. During the first retry when a data error is detected, the b switches S1 to Sn are turned off. At the time of the second retry when a data error is detected, c switches of the switches S1 to Sn are turned off. At this time, it is preferable to set b <a <c. Since the number of switches S1 to Sn turned off is proportional to the delay time, three types of delay times having a relationship of Tb <Ta <Tc corresponding to b <a <c can be obtained.

When the delay time in the variable delay circuit 27 is changed, the data window pulse shifts left or right on the time axis as shown in FIG. 7B. FIG. 7 illustrates the effect of shifting the data window pulse. When a data window pulse is generated at the position indicated by the solid line in FIG. 7B while the data pulse Pd is generated at the position shown in FIG. 7A, the data pulse extraction circuit 25 is generated as shown in FIG. 7C. Cannot be output. However, if the number of switches S1 to Sn turned off is set to b and the delay time is shortened, the data window pulse shifts to the left on the time axis as shown by the broken line in FIG. Data pulse Pd of No. 1 and the data pulse can be extracted as shown by the broken line in FIG. 7 (C). if,
Switch S1 when the data pulse cannot be extracted even if the data window pulse is shifted to the left (forward)
The number of OFF of .about.Sn is increased to c and the data window pulse is shifted to the right (lagging direction) to try to extract the data pulse. Also, if necessary, delay times of more than three stages are set, and data pulse extraction is attempted. This increases the possibility that the data pulse can be extracted by the retry even when the read output waveform in FIGS. 5A and 5B has a peak shift.
Since the clock window pulse for extracting the clock pulse also changes by switching the delay time of the variable delay circuit 27, it can be similarly read.

[0017]

[Second Embodiment] A fixed magnetic disk drive according to a second embodiment of the present invention will be described below with reference to FIGS. However, in FIG. 9, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The disk 1 of FIG. 9 is substantially the same as that of FIG. 1, but the number of sectors of one track is changed to 63, and ECC (Error) is used instead of the CRC recording area 15 of FIG.
A correction recording data recording area is provided. The track format and main data are 1-7.
It is written by the RLL method.

In FIG. 9, the variable delay circuit 27a is connected to the read pulse form circuit 18, the first delay output line indicated by B is connected to the PLL circuit 24, and the second delay output line indicated by C is a delay circuit. -Connected to the pulse extraction circuit 25. The data pulse extraction circuit 25 includes a PLL circuit 24.
The output line indicated by D is also connected. The data pulse extraction circuit 25 is connected to the 1-7 decoder 29a and the clock generator 26a. Clock generator
The data 26a forms the clock for the decoder 29a based on the data pulse and the standard clock 1 on line 30a. The 1-7 decoder 29a is a 1-7 RLL type decoder.
The data is converted into data according to NRZ, for example. The ECC circuit 31 performs error check correction based on the ECC data. The standard clock 2 is applied to the ECC circuit 31 via the line 30b.

Output line A of read pulse forming circuit 18
Signal is delayed by the variable delay circuit 27a, and the first delayed signal on the line B is sent to the PLL circuit 24 and to the line C.
The second delayed signal is input to the data pulse extraction circuit 25. In the variable delay circuit 27a, as shown in FIG.
There are n delay elements, and the signal passing through the n / 2 delay elements on the left half side is output to the line B. When a read pulse of the 1-7 RLL system shown in FIG. 11A is generated from the read pulse forming circuit 18, this is generated by the variable delay circuit 27a.
It is delayed by and is input from the line B to the PLL circuit 24. The PLL circuit 24 generates the data window pulse shown in FIG. 11D in response to the pulse of the line B. On the other hand, the pulse on the line C via the variable delay circuit 27a as the shift means is input to the data pulse extraction circuit 25 together with the data window pulse on the line D.
The data pulse Pd contained in the read pulse shown in FIG. 11C is extracted as shown in FIG. 11E by the data pulse extraction circuit 25 including an AND gate, for example. The extracted data pulse is 1-7 together with the phase-shifted standard clock in the clock generator 26a.
The read data is input to the decoder 29a and read data is formed according to a well-known principle.

The variable delay circuit 27a of FIG. 9 is constructed as shown in FIG. That is, the variable delay circuit 27 comprises a series circuit of a plurality of delay elements 45a, 45b, 45c ... 45n, and switches S1, S2 ... Sn connected in parallel to the delay elements 45a to 45n. Switches S1 to Sn
Is selectively turned on / off by a microcomputer (controller) 34. Each delay element 45a to 45n has a delay time of about 1.3 ns. In FIG. 10, m = n /
There is a relationship of 2. During normal reading, a specific switch Sx of the n switches S1 to Sn is turned on to obtain a predetermined delay time Tx. This delay time Tx is set to position the data window pulse at the center of the bit cell. First when a data error is detected
At the time of retry, the specific switch Sx among the switches S1 to Sn is turned on. At the time of the second retry when a data error is detected, the specific switch Sz among the switches S1 to Sn is turned on. Specific switches Sx, Sy, Sz
Gives the delay times Tx, Ty and Tz. These are Ty <
Tx <Tz.

When the delay time in the variable delay circuit 27a is changed, the data pulse shifts left or right on the time axis as shown in FIG. FIG. 12 illustrates the effect of shifting the data pulse. FIG. 12 (B)
When a data pulse is generated at the position shown by the solid line in FIG. 12A while the data window pulse is generated at the position shown in FIG. 12, the output of the data pulse extraction circuit 25 cannot be obtained as shown in FIG. 12C. . However, if the switch to be turned on is set to Sy and the delay time is shortened, the data pulse shifts to the left on the time axis as shown by the broken line in FIG. I will
It becomes possible to extract the data pulse as shown by the broken line in FIG. If the data pulse cannot be extracted even if the data window pulse is shifted to the left (leading direction), the ON switch is set to Sz and the data pulse is shifted to the right (lagging direction) to try to extract the data pulse. Also, if necessary, delay times of more than three stages are set, and data pulse extraction is attempted. This increases the possibility that the data pulse can be extracted by the retry even when the peak shift of the read output waveform of FIGS. 13A and 13B occurs.

FIG. 11 shows the states A to E in FIG. Further, FIG. 13 shows the states of points A to G in FIG. 3 at the time of recording by the 1-7 RLL system in the same format as FIG.

[0024]

MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible. (1) As shown in FIG. 8, the data window pulse obtained from the PLL circuit 24 is sent to the data pulse extraction circuit 25 as it is, and the read pulse of the read pulse line 18 a is sent via the variable delay circuit 27 to the data pulse extraction circuit 25.
The delay time of the variable delay circuit 27 may be switched at the time of retry. In this case, the data pulse Pd of FIG. 7A moves on the time axis and coincides with the data window pulse. (2) When the variable delay of the clock window pulse is unnecessary, the output of the PLL circuit 24 can be connected to the inverter 28 without the variable delay circuit 27. (3) It is also applicable to the case of recording / reproducing data by the FM system or various other systems. (4) The error check data may be either CRC data or parity bit. (5) The present invention can be applied to a magneto-optical disk device, a floppy disk device and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing a fixed magnetic disk device according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a format of tracks on a disc.

FIG. 3 is a diagram showing the read pulse forming circuit of FIG. 1 in detail.

FIG. 4 is a block diagram showing in detail the PLL circuit and the variable delay circuit of FIG.

5 is a waveform diagram showing voltages at points A to G in FIG.

FIG. 6 is a waveform diagram showing voltages at points A to E in FIG.

FIG. 7 is a waveform diagram showing the relationship between the input and output of the data pulse extraction circuit.

FIG. 8 is a block diagram showing a part of a modified magnetic disk device.

FIG. 9 is a block diagram showing a fixed magnetic disk device of a second embodiment.

10 is a block diagram showing the delay circuit of FIG. 9. FIG.

FIG. 11 is a waveform diagram showing states of points A to E in FIG.

12 is a waveform diagram showing the relationship between the input and output of the data pulse extraction circuit in FIG.

13 is a waveform diagram showing states of points A to G in FIG. 3 when the read pulse forming circuit of the circuit in FIG. 9 is the same as that in FIG.

[Explanation of symbols]

 24 PLL circuit 25 Data pulse extraction circuit 27 Variable delay circuit

Claims (1)

[Claims] 1. A bit cell having a predetermined time length in which a plurality of sectors included in a track have main data of a plurality of bits and error check data of a single or a plurality of bits for checking a read error of the main data. A disk device for reading the main data and the error check data from a recording medium disk written according to the arrangement of to obtain an output corresponding to the main data, wherein the main data and the error check data are output from the disk. A reading unit for reading, and the main data and the central unit of a plurality of bit cells arranged in series based on an output of the reading unit, which is coupled to the reading unit and corresponds to the main data and the error check data. The data pulse corresponding to the error check data is that. It is a read pulse forming circuit for forming the placed read pulse train, coupled to said read pulse forming circuit takes a first value each corresponding to the central region of the plurality of bit cells,
A data window pulse forming circuit for forming a data window pulse having a second value between the central regions based on the read pulse train; and a data pulse forming circuit coupled to the read pulse forming circuit and the data window pulse forming circuit, A data pulse extracting circuit for extracting the data pulse of the read pulse train based on a data window pulse; and the main data and the error recorded on the disc based on the data pulse, the data pulse extracting circuit being coupled to the data pulse extracting circuit. Error detection means for obtaining reproduction main data and reproduction error check data corresponding to the check data and detecting an error of the reproduction main data based on the reproduction error check data, and a time axis of the read pulse train and the data window pulse Change the relative position above Position shift means for controlling the reading means so as to reread at least the sector in which an error has occurred in response to a signal indicating an error obtained from the error detecting means, and the relative to the read pulse train. A disk device comprising: control means for controlling the position shift means so as to change the position of the data window pulse on the time axis.