JP2560597B2 - Data conversion disk unit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion disk device such as a fixed (hard) magnetic disk device (HDD).

[0002]

2. Description of the Related Art A recording medium disk of a fixed magnetic disk device has a large number of tracks as disclosed in, for example, Japanese Unexamined Patent Publication No. 1-143085, and each track is a track.
It has a vosector and a data sector repeatedly. Track data, servo burst for tracking servo, and the like are recorded in each servo sector.

A typical conventional fixed magnetic disk drive is
It has a rotation detecting device composed of a frequency generator (FG) that generates sector pulses corresponding to the servo sectors when the disk rotates. This rotation detecting device is used not only for the constant speed rotation control of the disk but also for generating the sector pulse.

[0004]

By the way, the FG may not be provided for downsizing and cost reduction. In this case, the position of the sector must be determined by reading the gap having a predetermined width provided in the servo sector with the head. However, an error may occur in reading the gap by the head. Since the sector pulse is used as a read / write reference, if a sector pulse is accidentally generated, all the controls are disturbed and normal data reading and writing becomes impossible. Further, at the time of writing the data, the data already written may be destroyed.

Therefore, an object of the present invention is to provide a disk device capable of accurately determining a sector based on the reading of a servo sector.

[0006]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a recording medium disc having a large number of tracks, a rotating means for the disc, and scanning of the tracks of the disc to read data. A signal converting head for writing / writing, an amplifier circuit connected to the head, and a read pulse for forming a read pulse corresponding to the data recorded on the disk based on the output of the amplifier circuit. A pulse forming circuit and a de-pulse connected to the head.
Write circuit for writing data, head moving means for moving the head in the direction of intersection of the tracks, means for indicating a target track for positioning the head, and detection of the track on which the head is located. And a means for controlling the head moving means so as to eliminate the difference between the detected track obtained from the track detecting means and the target track, and each track of the disk is A servo sector and a data sector are repeatedly arranged, and the servo sector has a gap of at least a non-data recording area of a predetermined width and an address for discriminating the plurality of tracks. In the data conversion disk drive having the track data area, the output from the read pulse forming circuit is used. Check whether at least the gap is at a predetermined position and whether or not the track data is read, the gap is at a predetermined position, and the track data is read. The present invention relates to a data conversion disk device characterized by further comprising sector check means for generating a signal indicating that the servo sector has been correctly read. It is to be noted that a sector pulse is generated as described in claim 2 and a window (window) pulse which is delayed by one sector scanning time from the sector pulse is generated. It is desirable to generate.

[0007]

In the present invention, the sector detection error is reduced because the sector is detected in consideration of the reading of track data without depending on the gap. When the window pulse is used as described in claim 2, the sector detection accuracy is further improved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A fixed magnetic disk drive according to an embodiment of the present invention will be described with reference to FIGS. In FIG.
A recording medium magnetic disk 1 having high rigidity is fixed to a hub 2, and the hub 2 is connected to a disk motor 3. Mode
The disk 3 rotates the disk 1 at a high speed and at a constant speed. The magnetic head 5 is supported by an arm 6, and the arm 6 is connected to the voice coil motor 4. The voice coil motor 4 is a known one composed of a magnet and a coil, and the arm 6 is moved in an arc shape by an electric current flowing through the coil, and the head 5 at the tip of the arm 6 is moved in the radial direction of the disk 1. It works as a moving device for moving the head. The head 5 is connected to a write (write) circuit 7 and a read amplifier circuit incorporating an AGC circuit.

The disk 1 has a large number of concentric tracks (cylinders) TR, and each track TR has data recorded in a predetermined track format. The track format includes a large number (43 in this example) of sectors. Each sector has a data sector DS and a servo area or a servo sector SV shown by hatching in FIG. The servo sectors SV of each track TR are arranged at the same angular position extending radially of the disk 1.

FIG. 2A is a diagram for explaining a sector by expanding a part of the track TR. Each sector S0,
S1 ... is a sector sector SV0, SV1 ...
It consists of tusectors D0, D1 ... Each servo sector S
As shown in FIG. 2B, V0, SV1 ...
G1 (non-magnetized region), AGC (automatic gain control) reference signal region B1, and second gap G
2, a track data area B2, a well-known tracking servo burst area B3, and a post angle B4. The first gap G1 is provided next to a buffer area (magnetization area) called a pad (PAD) provided at the end of the previous data sector D42, and is 2 bytes of main data of the data sector. (16 bits) Transfer time (2 μse
It has a width corresponding to c). The AGC reference signal area B1 is an area in which a reference signal for controlling a well-known AGC circuit in the well-known lead amplification circuit 8 connected to the head 5 of FIG. It has a recording length corresponding to the data transfer time (16 μsec). The second gap G2 is arranged between B1 and B2 and has a recording length corresponding to 1 byte of main data transfer time (1 .mu.sec).

The track data area B2 is, as shown in FIG. 2C, a preamble A1, a sub-track data area A2, and a main track data (track number) area Tn.
o and a postamble A3. Preamble A
1 has a record length corresponding to the main data transfer time of 2 bytes. The sub-track data area A2 is provided with index data In and track zero detection data as shown in FIG.
Area for recording the data T and the guard band data GB respectively, and the writing areas for In, T and GB are 1/2 each.
It has a width corresponding to the main data transfer time (0.5 μsec) of a byte and is accompanied by a noise guard signal CK. The noise guard signal CK is a signal indicating logic 1 and is 1/2
This corresponds to the main data transfer time (0.5 μsec) of a byte. The length of the sub-track data area A2 corresponds to 3 .mu.sec.

The index data In indicates the start of the track, that is, the sector zero S0, and is data for distinguishing the sector zero S0 from the remaining sectors S1 to S42. The index data In of the sector zero S0 is used. -In is a logical 0, and the index data I of the remaining sectors S1 to S42 is
n is a logical one.

Track zero detection data T is track zero T.
This is the data for detecting 0 separately from other tracks, and in this embodiment, from track zero (T0) to track 3
4 tracks up to (T3) and track zero (T0)
It is a logical 0 in the guard band tracks T-1 to T-37 on the outer peripheral side, and a logical 1 in the track 4 to the innermost track. Combination of track zero detection data T and main track code Tno even if track zero detection data is 0 in tracks T1, T2, T3 and guard band tracks other than track zero T0. The position of track zero T0 can be determined by.

The guard band data area GB is for identifying the outer peripheral area of the track zero, and is the sixth guard band track T-6 to the thirty seventh guard band on the outer peripheral side of the track zero T0. A logical 0 is written in the hard band track T-37, and a logical 1 is written in the fifth guard band track T-5 to track zero T0 and in the innermost track from track T1.

In the main track data area Tno, as shown in FIG. 2D, 6-bit (C0 to C5) data (track identification signal) accompanied by a noise guard signal CK is provided. It is recorded. The noise guard signal CK is arranged immediately before each track data bit C0 to C5.
The track identification signal (data) consisting of 6 bits (C0 to C5) follows the Gray code. Each bit C0 to C5 has a width corresponding to the main data transfer time of 1/2 byte. Therefore,
The length of the main track data area Tno is 6 μsec.
The postamble area A3 has a length of 4 .mu.sec and eight logic 1s are recorded.

FIG. 5A shows the sector S0 of the track T0.
7 shows a positive phase output waveform of the lead amplification circuit 20 when a part of the data is scanned by the head. G1, B1 in FIG.
G2, B2, A1, CK, and In respectively correspond to those shown by the same reference numerals in FIG. 3 from area B1
A two-period sine wave or an approximate sine wave is obtained. The preamble A1 consists of a signal for four cycles of a sine wave or an approximate sine wave. The index data In is a logic 0 arranged after the noise guard signal CK having one cycle of a sine wave and has the same time width as CK. Other track data
Is also recorded.

The postamble B4 has a length of 4 μsec and generates eight sine waves. Therefore, if the servo sector is reproduced correctly, a sine wave corresponding to the postamble B4 is obtained at this end.

In the tracking servo signal area B3, the servo burst A offset to one side from the center of the track is provided.
And the Boverst B offset to the other side are recorded by a known method.

The data sector DS has an ID field and a data field.
Main field (data) is recorded in the data field.

Referring again to FIG. 1, the amplifier circuit 8 is a relay.
It is connected to the pulse forming circuit 9 and the position signal forming circuit 10. The read pulse forming circuit 9 forms a read pulse by shaping the waveform of the reproduction output and sends it to the controller 12 through the line 13. The read pulse forming circuit 9 includes a differentiating circuit and a comparator to detect the peak of the waveform shown in FIG. 5 (A) and generate the read pulse shown in FIG. 5 (B). Circuit. Since the read pulse corresponds to recording, it can be used as read information (data).

The position signal forming circuit 10 includes a controller 1
2 is used to extract the servo bursts A and B in the servo signal area B3 shown in FIG. 2 (B) by the timing signal given on the line 13 to form the signal (position signal) of the difference between the two. This is sent to the head control circuit 14 via a line 15. The controller 12 performs various signal processing based on the read pulse given on the line 11, and the head 5
To the head control circuit 14 by the line 16, the AGC amplifier circuit 8 is supplied by the line 17 with the extraction timing signal of the AGC reference signal area B1, and the write circuit 7 is supplied by the line 18 by the line 18. A write enable signal (write enable signal) is given. The seek signal is determined based on the difference between the target track given from the line 19 to the controller 12 and the track detected based on the read pulse given from the line 11.

The head control circuit 14 forms a control signal on the basis of the seek signal given from the line 16 at the time of seek and the signal indicating the moving speed of the head 5 obtained at the output line 21 of the speed sensor 20. The voice coil motor 4 is controlled via the drive circuit 22, and at the time of tracking control, the head 5 is controlled so as to match the center of the track based on the output of the position signal forming circuit 10. The control circuit 14 is substantially the same as the well-known circuit disclosed in Japanese Patent Application Laid-Open No. 1-143085, so detailed description thereof will be omitted.

FIG. 3 shows the controller 12 of FIG. 1 in principle. This controller 12 has a flip-flop 30,
Timing signal forming circuit 31, track data detecting circuit 32, main data extracting circuit 33, seek data generating circuit 3
4, a sector pulse generation circuit 35, and a write enable signal generation circuit 36. The trigger type flip-flop 30 is connected to the read pulse line 11 and has an output state which alternately changes in response to the read pulse shown in FIG. 5B, and is provided for detecting track data. ing. The track data detection circuit 32 is connected to the flip-flop 30, and based on the timing signal provided from the timing signal forming circuit 31 on the line 37, the data in the track data area B2 of FIG. It is extracted and sent to the seek data generating circuit 34. Main data extraction circuit 33
Is connected to the read pulse forming circuit 9 and extracts the data of the data sector DS by the timing signal given from the timing signal forming circuit 31 on the line 38.

The sector pulse generating circuit 35 is newly provided according to the present invention, and the read pulse line 1 is provided.
Connected to 1. The sector pulse generation circuit 35 generates a sector pulse based on the detection of the servo sector SV. The details will be described later.

The write enable signal generating circuit 36 is connected to the sector pulse generating circuit 35 by a line 39. The write pulse signal generating circuit 36 determines whether or not the internally generated window pulse and the sector pulse given from the line 39 are coincident with each other and discriminates. 18
And a write enable signal (write enable signal) is generated.

As shown in FIG. 4 in principle or functionally, the sector pulse generation circuit 35 has a first gap G1 detection circuit 41 connected to the lead-valve line 11, an AGC start end detection circuit 42, and an AGC end detection. A latch having a circuit 43, a second gearup G2 detection circuit 44, a track data start end detection circuit 45, and a track data end detection circuit 46, and holding the outputs of the detection circuits 41 to 46. AND gates 53 to which outputs of the circuits 47 to 52, latch circuits 47 to 52 are input, a sector pulse generating monomultivibrator (MMV) 55 connected to the AND gate 53, and AND And a latch reset circuit 56 connected to the gate 53.

The first gap G1 detecting circuit 41 includes a counter for counting the clock of a clock generator (not shown), and judges whether or not the period during which the read pulse is not generated is about 2 .mu.sec. At times, a signal indicating that it is the first gap G1 shown in FIG. 2B is output.
The latch circuit 47 in the next stage holds the gap detection output at t1 in FIG. 5C and outputs it.

The AGC leading edge detecting circuit 42 starts its operation in response to the gap detection of the first gap G1 detecting circuit 41, and the AGC reference is determined by whether or not a lead pulse is input within a certain time from the gap detecting time t1. Determine if there is a signal. If the AGC reference signal is accurately read, a read pulse is generated as shown in FIG. 5B at a time t2 after a fixed time has elapsed from the end of the gap, and an AGC leading edge detection pulse is obtained. The AGC start edge detection pulse is a latch circuit 48.
And the AGC leading edge detection signal which rises to a high level at t2 is obtained as shown in FIG.

The AGC leading edge detecting circuit 43 includes a counter for counting the read pulse in response to the output of the AGC leading edge detecting circuit 42, and 32 reading pulses generated when the AGC reference signal area B1 is normally reproduced. It is determined whether 31 read pulses other than the first read pulse are generated within a predetermined time, and when the 31 read pulses are counted, an AGC end detection pulse is generated. The AGC end detection pulse is held by the latch circuit 49 at the next stage, and a high level AGC end detection signal is obtained at time t3 as shown in FIG.

The second gap G2 detecting circuit 44 is composed of a counter, starts counting clocks in response to the detection pulse of the AGC end detecting circuit 43, and is based on the fact that a read pulse does not occur within about 1 μsec. To detect the second gap G2. This detection pulse is held by the latch circuit 50, and a high level second gap detection signal is output at t4 as shown in FIG.

The track data start end detection circuit 45 starts its operation in response to the output pulse of the G2 detection circuit 44, and generates a track data start end detection pulse when a read pulse is generated within a fixed time. A preamble A1 is provided at the beginning of the track data area B2, and when read normally, a read pulse is always generated following the second gap. This detection pulse is held by the latch circuit 51, and as shown in (G) of FIG. 5, a start end detection signal of track data which becomes high level at time t5 is generated.

The track data end detecting circuit 46 includes a read pulse detecting circuit 46a, a window forming circuit 46b, and
It consists of an AND gate 46c. The read pulse detection circuit 46a extracts the read pulse generated in the track data area B2 in response to the output pulse of the track data start end detection signal 45. The window pulse forming circuit 46b is connected to the AGC leading edge detecting circuit 42 in this embodiment, and generates the window pulse shown in FIG. 5H at t6, which is a certain time Te after the generation time t2 of the AGC leading edge detecting pulse. To do. The window pulse forming circuit 46b is composed of a timer and a monomultivibrator, and the timer measures only Te (about 31.75 μsec) from t2,
Width Tw in mono-multi vibrator synchronized with the end of Te
A pulse of (about 0.25 μsec) is generated. AND game
The gate 46c is connected to the read pulse detecting circuit 46a and the window pulse forming circuit 46b, and generates a track data start edge detecting pulse when the outputs of both of them simultaneously become high level. The latch circuit 52 latches this output and generates a track data end detection signal which becomes high level at time t7 as shown in FIG.

The AND gate 53 has six latch circuits 47.
.About.52 and outputs signals for converting from low level to high level at t7 as shown in FIG. 5 (J) in response to the outputs of all the latch circuits 47-52 being at high level at the same time. . The fact that a high level output is obtained from the AND gate 53 means that the head 5 has accurately read the data of the servo sector SV.

A timer 54 connected to the AND gate 53
Starts timing in synchronization with the time t7 when the AND gate 53 changes from low level to high level, and when the time Ta is measured, triggers the MMV55 to generate a sector pulse from the MMV55.

In this embodiment, a write enable signal generation circuit 36 for further increasing the sector detection accuracy and generating a write enable signal is provided. The write enable signal generating circuit 36 has a window pulse generating circuit 60 as shown in FIG. The window pulse generating circuit 60 includes a clock generator 61 and first and second counters 62 and 63. The reset terminal R of the first counter 62 is connected to the sector pulse line 39, and the input terminal C is connected to the clock generator 61. The first counter 62 functions as a timer, and the sector pulse shown in (A) of FIG. 7 corresponds to the MMV5 of FIG.
5 is reset every time it is generated, and the measurement of the constant time Tb is started from here, and a pulse indicating the elapse of Tb within the constant time shown in FIG. 7B is generated. The input terminal C of the second counter 63 is connected to the clock generator 61, the activation terminal ST is connected to the output terminal of the first counter 62, and the reset terminal R is connected to the sector pulse line 39. As a result, the second counter 63 starts counting clocks in synchronization with the rising of the output pulse of the first counter 62 and generates the window pulse WP at the time when the predetermined time Tc is counted. The time width of the window pulse WP generated from the second counter 63 is set to a predetermined Td. However, when the sector pulse of FIG. 7A is generated while the window pulse WP is being generated, the window pulse of FIG. 7C disappears in synchronization with the rising edge of this sector pulse. This operation is shown in the section from t1 to t4 in FIG. That is, counting of the predetermined time Tb by the first counter 62 starts in synchronization with the rising edge of the sector pulse of t1 shown in FIG. 7A, and at time t2, the pulse of the pulse of FIG. Is generated, the second counter 63 is responsive to this.
When the Tc counting is completed at t3 when the counting of the predetermined time Tc is started, the window pulse WP shown in FIG. 7C is generated from the second counter 63. This wind pulse WP is t3
Although it will be generated until a predetermined time Td elapses from the time point, when the sector pulse of FIG. 7A is generated at the time point t4,
The wind pulse WP falls to a low level. On the other hand, FIG.
No sector pulse is generated during the generation period of the window pulse WP in the section t6 to t7 in (C). That is, the counting of the predetermined time Tb from t4 is executed by the first counter 62, the counting of the predetermined time Tc is executed from the time t5, and the window pulse of the time width Td is generated from the time t6 to the time t7. Since the sector pulse is generated at t8 after t7, the window pulse WP is not reset. Therefore, the wind pulse WP
Has a time span of Td. Note that Tb, Tc, and Td are, of course, set shorter than the sector pulse period (mutual time interval) of FIG.

One input terminal of the coincidence detection circuit 64 is connected to the second counter 63 for generating the window pulse WP, and the other input terminal is connected to the sector pulse line 39. The coincidence detection circuit 64 forms a pulse obtained by delaying the sector pulse of FIG. 7A and the window pulse WP of FIG. 7C by a minute time, and the delayed pulse and FIG.
When the sector pulse of (A) coincides, the coincidence detection pulse shown in (D) of FIG. 7 is generated.

The mismatch detection circuit 65 has one input terminal connected to the window pulse generation counter 63 and the other input terminal connected to the sector pulse line 39 in order to detect a mismatch between the sector pulse and the window pulse WP. Has been done. The mismatch detection circuit 65 generates a mismatch detection pulse shown at t7 in FIG. 7E when the sector pulse shown in FIG. 7A and the window pulse WP shown in FIG. 7C do not match. To do.

The flip-flop 68 controls the write enable. The set terminal S is connected to the match detection circuit 64 and the reset terminal R is connected to the mismatch detection circuit 6.
Connected to 5. Therefore, as shown in (F) of FIG. 7, a high level output is generated in synchronization with the coincidence detection pulse of (D) of FIG. 7 and reset by the non-coincidence detection pulse.

The SR flip-flop 69 determines the read / write period in the servo sector SV and the data sector DS. The set terminal S is connected to the sector pulse line 39 and the reset terminal R is the first. 1 is connected to the output terminal of the counter 62. As a result, the signal shown in FIG. 7G is generated from the flip-flop 69.

One input terminal of the AND gate 70 is connected to the flip-flop 68, and the other input terminal is connected to the flip-flop 69. Therefore, a write enable signal indicating read / write permission in the sector (SV + DS) is generated from here.

[0041]

MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible. (1) Six inputs are given to the AND gate 53 of FIG. 4, but the sector pulse may be formed based on one or an arbitrary plurality of detection signals selected from these inputs. Moreover, more conditions can be added to the generation of the sector pulse. (2) In FIG. 4, each of the detection circuits 41 to 46 is shown independently for easy understanding, but it may be configured to share a counter or the like. Similarly, in the write enable signal generation circuit 36 of FIG. 6, many parts can be configured in common. (3) The present invention can be applied to a magneto-optical disk recording / reproducing device.

[0042]

As is apparent from the above, according to the invention of each claim, it becomes possible to accurately detect the sector.

[Brief description of drawings]

FIG. 1 is a block diagram showing a fixed magnetic disk drive according to an embodiment of the present invention.

FIG. 2 is a diagram showing a format of tracks on a disc.

3 is a block diagram showing in detail the controller of FIG. 1. FIG.

FIG. 4 is a block diagram showing in detail the sector pulse generation circuit of FIG.

5 is a waveform diagram showing an output of the amplifier circuit of FIG. 1 and states of points B to J of FIG.

6 is a block diagram showing in detail the write enable signal generating circuit of FIG.

FIG. 7 is a waveform diagram showing states of points A to I in FIG.

[Explanation of symbols]

 1 disk 35 sector pulse generation circuit 36 write enable signal generation circuit

Claims (2)

(57) [Claims] 1. A recording medium disc having a large number of tracks, a rotating means for the disc, and scanning / reading of data by scanning the disc tracks.
A signal conversion head for writing, an amplifier circuit connected to the head, and a read pulse for forming a read pulse corresponding to the data recorded on the disk based on the output of the amplifier circuit.
A pulse forming circuit, a write circuit for writing data connected to the head, a head moving means for moving the head in the crossing direction of the tracks, and a target track for positioning the head. Means, track detecting means for detecting the track on which the head is located, and means for controlling the head moving means so as to eliminate the difference between the detected track obtained from the track detecting means and the target track. And each track of the disk has a servo sector and a data sector.
Data sectors are repeatedly arranged, and the servo sector is a track data area in which a gap having at least a non-data recording area and having a predetermined width and an address for distinguishing the plurality of tracks are written. In a data conversion disk device including: a check whether at least the gap is at a predetermined position based on the output of the read pulse forming circuit, and whether the track data is read. And a sector check means for generating a signal indicating that the servo sector has been correctly read when the track data is read and the gap is at a predetermined position. Data conversion disk device. 2. The sector check generating means generates sector pulse indicating sector detection in response to at least the gap being at a predetermined position and the track data being read, and sector pulse generating means, Window pulse generating means for generating a window pulse which is substantially coincident with a pulse obtained by delaying a sector pulse by one sector scanning time for scanning one servo sector and one data sector by the head; Means for generating a signal for permitting reading and / or writing of data in the sector when the sector pulse generated next to the sector pulse which is the basis of the generation of the data and the window pulse match. 2. The data conversion disk device according to claim 1, wherein: