JPH07176140A - Disk shaped recording medium - Google Patents

Abstract

PURPOSE:To quickly and correctly find tracks by writing a noise guard signal between bits constituting a track discriminating signal. CONSTITUTION:The seeking of a target track in the case the present position of a head 5 is unknown is performed based on a track zero T0 as a reference. A disk 1 starts rotating in accordance with a power source throwing or a calibration command and also the calibration command is generated from a microcomputer 19 to position the head 5 at the track T0. On the other hand, track recognizing signals are recorded on respective tracks and the noise guard signal is written between bits constituting the track discriminating signal. Next, the head 5 is moved toward the target track and reads out the track discriminating signal. When a track jumping is generated, a correction is applied by comparing a real moving amount and a predicted moving amount at every read out. When the target track is detected, the head 5 is positioned at the track.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk-shaped recording medium used in a data conversion device such as a fixed (hard) magnetic disk device, and more specifically, to a target track (cylinder) seek (search) quickly and quickly. The present invention relates to a disc-shaped recording medium that can be accurately performed.

[0002]

2. Description of the Related Art If a track number (address) is written in advance on each track (cylinder) of a disk-shaped recording medium, a target track can be sought based on this track number. However, if different track numbers are written to all of a large number of tracks, the number of digits (bits) of the track number will inevitably increase, and the track number (address) can be quickly changed while moving the head in the radial direction of the recording medium disk. Reading becomes difficult.

As a method for solving this problem, for example, a method of dividing a large number of tracks into groups and writing the same track identification signal to each group as disclosed in Japanese Patent Laid-Open No. 1-143085 is known. There is. According to this method, since the number of tracks included in one group is reduced, the recording track length of the track identification signal is shortened,
A quick seek is possible.

[0004]

In the method disclosed in the above publication, tracks are distinguished by the difference in the number of magnetized regions. Therefore, in a track with few magnetized regions, noise (non-specific magnetized region) in the non-magnetized region may be regarded as the magnetized region of the track identification signal. Further, in the conventional method, there is a possibility that a non-magnetized region between the magnetized regions of the track identification signal may be erroneously detected as a gap (non-magnetized region) at a specific position in the track format.

Therefore, it is an object of the present invention to provide a disk-shaped recording medium which allows a track to be known quickly and accurately.

[0006]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a disk-shaped disc having a large number of concentric tracks for recording and / or reproducing data by relative scanning motion with a signal conversion head. In the recording medium, the plurality of tracks are divided into a plurality of groups, and a track identification signal is recorded on each track of each group by a predetermined code so that the head can read the signal. The track identification signals are the same as each other, and a noise guard signal is written between bits constituting the track identification signal. Note that the track identification signal is a Gray code.
Is desirable.

[0007]

When the noise guard signal is recorded between each bit of the track identification signal, there is no continuous non-recorded area. Even if noise is placed in a narrow area between the noise guard signals, the regular noise guard signal can read the track identification signal with the influence of the noise reduced. The noise guard signal also has a function of preventing the peak shift of the reproduced waveform of data. Further, when the Gray code is adopted, the track identification signal only changes by 1 bit when the track moves to the adjacent side, and therefore a large detection error of the track data does not occur.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a fixed magnetic disk device according to an embodiment of the present invention will be described with reference to FIGS. In FIG. 1, a recording medium magnetic disk 1 having high rigidity is fixed to a hub 2, and the hub 2 is connected to a disk motor 3.
The motor 3 rotates the disk 1 at a high speed and at a constant speed. The magnetic head 5 is supported by the arm 6, and the arm 6 is coupled to the voice coil motor 4. Voice coil motor 4
Is a known device including a magnet and a coil, and functions as a head moving device that moves the arm 6 in an arc shape by a current flowing through the coil and moves the head 5 at the tip of the arm 6 in the radial direction of the disk 1. The head 5 is connected to a write circuit 7 and a read amplifier circuit 8 having a built-in AGC circuit, respectively.

The disk 1 has a large number of concentric tracks (cylinders) TR, and data is recorded on each track TR in a predetermined track format. The track format includes a large number (43 in this example) of sectors, and each sector has a large number (43 in this example) of servo areas or servo sectors SV shown in FIG. 1 in addition to the data sector DS. . The servo sectors SV of each track TR are arranged at the same angular position extending radially of the disk 1.

FIG. 2A is a diagram for explaining a sector by expanding a part of the track TR. Each sector S0,
S1 ... Comprises servo sectors SV0, SV1 ... And data sectors D0, D1. Each servo sector SV0, SV1
Is a first gap (non-magnetized area) G1, an AGC (automatic gain control) reference signal area B1, a second gap G2, a track data area B2, as shown in FIG. It comprises a well-known tracking servo burst area B3 and a postamble B4. The first gap G1 is a buffer area (magnetization area) called a pad (PAD) provided at the end of the previous data sector D42.
It is provided next to, and has a width corresponding to the transfer time (2 μsec) of 2 bytes (16 bits) of the main data of the data sector. The AGC reference signal area B1 is an area in which a reference signal for controlling a well-known AGC circuit in the well-known read amplification circuit 8 connected to the head 5 of FIG. It has a recording length corresponding to the time (16 μsec). The second gap G2 is arranged between B1 and B2 and has a recording length corresponding to the main data transfer time (1 μsec) of 1 byte.

As shown in FIG. 2C, the track data area B2 includes a preamble A1, a sub-track data area A2, and a main track data (track number) area Tno.
And a postamble A3. Preamble A1
Has a record length corresponding to the main data transfer time of 2 bytes. The sub-track data area A2 includes index data In, track zero detection data T and guard band data GB, respectively, as shown in FIG. In,
The writing areas of T and GB each have a width corresponding to the main data transfer time (0.5 μsec) of 1/2 byte, and are written together with the noise guard signal CK. The noise guard signal CK is a signal indicating logic 1, and has a time width corresponding to the main data transfer time (0.5 μsec) of 1/2 byte.

The index data In indicates the start of a track, that is, the sector zero S0, and is data for distinguishing the sector zero S0 from the remaining sectors S1 to S42. The index data In of the sector zero S0 is a logical value. 0
And the index data In of the remaining sectors S1 to S42 is logical one.

Track zero detection data T is track zero T
This is the data for detecting 0 separately from other tracks, and in this embodiment, it is track 0 (T0) to track 3
4 tracks up to (T3) and track zero (T0)
It is a logical 0 in the guard band tracks T-1 to T-37 on the outer peripheral side, and a logical 1 in the track 4 to the innermost track. Even in the tracks T1, T2, T3 other than the track zero T0 and the guard band track, even if the track zero detection data is 0, the position of the track zero T0 can be determined by the combination with the main track data Tno. .

The guard band data area B2 is for identifying the outer peripheral area of the track zero, and the sixth guard band track T-6 to the 37th guard band track T on the outer peripheral side of the track zero T0. A logical 0 is written at -37, and a logical 1 is written from the fifth guard band track T-5 to track zero T0 and from the track T1 to the innermost track.

The main track data area Tno is 6-bit (C0 to C5) data accompanied by a noise guard signal CK as shown in FIG. 2D. The noise guard signal CK is arranged immediately before each track data bit C0 to C5. The track identification signal consisting of 6 bits (C0 to C5) complies with the Gray code. Each bit C0 to C5 has a width corresponding to the main data transfer time of 1/2 byte.

FIG. 11A shows the sector S of the track T0.
The positive phase output waveform of the read amplifier circuit 8 when the track data area B2 at 0 is scanned by the head 5 is shown. Figure 11
A1, In, T0, GB, and Tno in (A) of FIG.
It corresponds to A1, In, T, GB and Tno in (C). The preamble A1 is composed of a signal for four cycles of a sine wave or an AC waveform similar to this. The index data In is a logic 0 arranged after the noise guard signal CK consisting of one cycle of the AC waveform and has the same time width as CK. Track zero detection data T is AC waveform 1
It is a logic 0 arranged after the noise guard signal CK consisting of a cycle and has the same time width as CK. The guard band data GB is a logic 1 which is arranged after the noise guard signal CK having one cycle of the AC waveform and has one cycle of the AC waveform, and has the same time width as CK. Each bit C0 to C5 of the track data Tno is a logic 0 arranged after the noise guard signal consisting of one cycle of the AC waveform and has the same time width as CK.

FIG. 3 shows track data bits C0 to C5 in which a large number of tracks TR of the disk 1 of FIG. 1 are divided into a plurality of track groups, and sub-track code signals In, T, GB which are added regardless of the groups. And noise guard signal (CK)
Will be omitted. In this embodiment, the number of tracks in one group is 64.
The tracks T0 to T63 are divided into the first track group, and the tracks T64 to T127 are divided into the second track group. As is apparent from FIG. 3, the track data C0 to C5 from the first track to the last track in each group are arranged with logical 0s and 1s according to the Gray code. As in FIG. 3, the LSB C0 is the first and the MSB
Each code is shown in the arrangement of (C0 C1 C2 C3 C4 C5) with C5 of the last being, for example, (0) is (000000) for T0, T64 and T128, and (1 for T1 and T65 and T129).
00000). Gray code is well known 10
Only one bit changes when the value is one smaller or one larger in the base number, and the remaining bits are the same.

Referring again to FIG. 1, the amplifier circuit 8 is configured as a differential amplifier circuit, is connected to the read data forming circuit 11 by the positive phase output line 9 and the negative phase output line 10, and has the positive phase output. It is connected to the position signal forming circuit 12 by a line 9. The read data forming circuit 11 forms a read pulse by waveform shaping of the reproduction output and outputs it to the line 13, and further forms read data based on the read pulse and outputs it to the line 14. Details of the read data forming circuit 11 will be described later. The read pulse output line 13 is connected to the timing signal generation circuit 15. The read data output line 14 is a track tape.
The data detection circuit 16 and the main data extraction circuit 17 are connected. The track data detection circuit 16 extracts the track data signals In, T, GB, C0 to C5 contained in the read data according to the timing signal given from the timing signal generation circuit 15 on the line 18 and then the microprocessor. That is, the microcomputer 19 is notified. Details of the track data detection circuit 16 will be described later.

The main data extraction circuit 17 extracts main data from the timing signal generation circuit 15 based on the timing signal given on the line 20 to extract the main data.
Send to 9.

The position signal (tracking control signal) forming circuit 12 includes a line 21 from the timing signal generating circuit 15.
The known servo bursts A and B are extracted by the timing signal given by
The signal (position signal) indicating the deviation from the center of the
Send to.

The timing signal generating circuit 15 has a line 33.
Sends a signal for controlling the read data forming circuit 11. This control signal corresponds to the write enable signal and is a signal for switching the detection level of data. The timing signal generation circuit 15 generates more control signals, which are omitted in FIG.

The microcomputer 19 controls the positioning of the head 5 on the target track designated by the track command signal given by the line 23. Therefore, the microcomputer 19 is connected to the control circuit 27 via the 8-bit seek data line 24, the D / A converter 25, and the line 26, and is also controlled by the seek direction signal line 28 and the mode instruction signal line 29. It is connected to the circuit 27. The seek data on the line 24 corresponds to the amount of head movement required to move the head 5 to the target track by the voice coil motor 4.
It is bit data and includes seek speed information. The D / A converter 25 sends the seek data to the head 5
Is converted into an analog signal corresponding to the moving speed of and is sent to the control circuit 27. In the positioning mode after the seek is completed, the D / A converter 25 generates a position indication reference signal (for example, zero volt).

The seek direction signal on the line 28 is for distinguishing whether the head 5 is moved inward or outward of the disk 1.

The mode instruction signal on the line 29 is a signal for distinguishing between the seek mode and the positioning (tracking) mode.

The speed sensor 30 includes a speed detecting coil which moves in a magnetic field together with the coil of the voice coil motor 4 and generates a voltage corresponding to the moving speed and moving direction of the head 5, and controls the speed signal via the line 31. It is given to the circuit 27. The output line of the control circuit 27 is connected to the voice coil motor 4 via the drive circuit 32. Details of the control circuit 27 will be described later.

[0026]

[Read Data Forming Circuit] FIG. 4 shows the read data forming circuit 11 of FIG. 1 in detail, and FIGS. 5 and 6 show A to O of FIG.
Indicates the state of dots. The pair of differential output lines 9 and 10 of the amplifier circuit 8 are connected to a differential type differential circuit 43 via coupling capacitors 41 and 42. Assuming that a logic 1 track identifying signal is recorded after the noise guard signal, the differentiating circuit 43 generates a pair of lines 9, 10
The reproduced signals shown in (A) and (B) of FIG. 5 obtained from the above are differentiated to generate the outputs shown in (C) and (D) of FIG. The differential-type waveform shaping circuit 44 connected to the pair of output lines of the differentiating circuit 43 uses the zero-volt comparator to generate the differential waveforms of (C) and (D) of FIG. 5 as square waves shown in (E) and (F) of FIG. To shape. A pair of output lines 9 and 1 of the amplifier circuit 8
0 branch lines 45, 46 are coupled capacitors 47, 4
A differential type gate pulse forming circuit 49 is connected via 8. The gate pulse forming circuit 49 shapes the waveform including the peaks shown in FIGS. 5A and 5B and sends the square waves shown in FIGS. 5G and 5H to the lines 50 and 51. This gate pulse forming circuit 49 has a control line 52, in which the output line 33 of the timing signal forming circuit 15 of FIG. 1 is a NOT circuit 53 and resistors 54, 55, 5.
6 and a power supply terminal 57 are connected via a signal level setting circuit 58. Details of the gate pulse forming circuit 49 will be described later. Gate pulse output lines 50, 5
1 is connected to the set terminal S and the reset terminal R of the RS flip-flop 59. This flip-flop 59
The output lines 60 and 61 of the positive phase and the negative phase of FIG.
The square wave pulse shown in (J) is obtained. One input terminal of the first NOR gate 62 is connected to one output line 63 of the waveform shaping circuit 44, and the other input terminal is connected to the positive phase output line 60 of the flip-flop 59.
One input terminal of the second NOR gate 65 is connected to the other output line 64 of the waveform shaping circuit 44, and the other input terminal is connected to the negative phase output line 61 of the flip-flop 59. The set terminal S of the RS flip-flop 66 is connected to the first NOR gate 62, and the reset terminal R is connected to the output line 60 of the flip-flop 59. The set terminal S of the RS flip-flop 67 is connected to the second NOR gate 65, and the reset terminal R is connected to the negative phase output line 61 of the flip-flop 59. Therefore, the square waves shown in (K) and (L) of FIG. 5 are obtained from the output terminals Q of the two flip-flops 66 and 67. One and the other input terminals of the OR gate 68 are connected to the output terminals of the two flip-flops 66 and 67, respectively. Therefore, the square wave shown in FIG. 5M is obtained from the OR gate 68. The mono-multivibrator (MMV) 69 is connected to the OR gate 68 and outputs the read pulse shown in (N) of FIG. 5 in response to the leading edge (rising edge) of the pulse of (M) in FIG. The output terminal of the MMV 69 is connected to the trigger input terminal T of the trigger type flip-flop 70, and is also connected to the timing pulse generation circuit 15 of FIG. The flip-flop 70 is triggered by the leading edge of the read pulse shown in FIG.
The square wave read data shown in (O) is output to the line 14. In this embodiment, the output pulse of the flip-flop 70 rises corresponding to the negative peak of the positive phase signal shown in FIG. In order to execute this, a flip-flop control circuit 70a is connected to the MMV 69, and this output line is connected to the reset terminal R of the flip-flop 70. The control circuit 70a has a built-in counter and keeps the flip-flop 70 in a reset state until counting 5 (odd number) read pulses from the beginning of the track data area.

FIG. 6 shows the states of points A to O of FIG. 4 when noise is present in the originally logical 0 section in the track data write area between the noise guard signals. Corresponding to the positive peak and the negative peak of the first noise guard signal, as shown in (N) of FIG.
2 occurs. The read pulse P3 is generated as shown in (N) of FIG. 6 even in response to the positive noise on the data area. However, the read pulse corresponding to the positive peak of the noise guard signal area next to the data area is not generated. That is, the flip-flop 66 of FIG. 4 enters the set state in the noise generation section, and this set state is maintained until the next negative half cycle of the noise guard signal arrives, which corresponds to the positive peak generated after the noise. Generation of a read pulse is blocked. As a result, read data can be read without being affected by noise. Even when reading the read data based on the positive peak, if the noise guard signal is arranged between the bits of the data, the noise guard signal serves as a buffer and the data is read. The shift of the positive peak of the bit indicating the data is reduced. Therefore, the noise guard signal can be called a peak shift prevention and noise guard signal.

[0028]

[Gate Pulse Forming Circuit] FIG. 7 shows the gate pulse forming circuit 49 of FIG. 1 in detail, and FIG. 8 shows the states of points A to E of FIG. The pair of input lines 45 and 46 of the gate pulse forming circuit 49 of FIG. 7 are connected to the differential amplifier 71, and the pair of differential output lines 72 and 73 are connected to the first and second comparators 74 and 75. It is also connected to the differential amplifier 76. A pair of differential output lines 72, 7
In FIG. 3, the positive phase output and the negative phase output shown in FIGS. 8A and 8B are obtained with the same DC bias voltage Vc. The differential amplifier 76 produces an output corresponding to the difference between the signals of FIGS. 8A and 8B. The full-wave rectifier circuit 77 connected to the differential amplifier 76 inputs the full-wave rectified output to the non-inverting amplifier circuit 78 via the resistor 78. The amplifier circuit 79 includes an operational amplifier 80 and resistors 81 and 82, and outputs the output corresponding to the input to the line 83 as shown in FIG. 8C. Line 33 is connected through resistor 84 to adjust the input level of amplifier 80. . A control signal corresponding to the write enable signal (data sector write / read enable signal) generated by the timing signal generating circuit 15 of FIG. 1 is input to the line 33. As a result, the DC component of the output of the amplifier circuit 79 shown in FIG. 8C changes. In this embodiment, the DC component of the waveform of FIG. 8C in which the write / read enable signal (write enable signal) of the data sector is generated on the line 13 of FIG. Shift the waveform up. Conversely, when it does not occur, the DC component is reduced and the waveform is returned to the position indicated by the solid line. That is, the DC component is increased during the period when the main data is read and written, and the DC component is reduced when the control signal such as track data and servo burst is read. This allows an accurate reading of the control signal. Since the output line 83 of the amplifier circuit 79 is connected to the input terminals of the two comparators 74 and 75,
The signals shown in (A) and (B) of FIG. 8 and the signal shown in (C) of FIG. 8 are compared, and when the waveform of FIG. 8C is larger than the waveform of FIG. (D) square wave is line 5
8 is output to 0, and the square wave shown in FIG. 8 (E) is sent to the line 51 during a period in which the waveform in FIG. 8 (C) is higher than the waveform in FIG. 8 (B). The waveforms of (D) and (E) of FIG. 8 correspond to the waveforms of (G) and (H) of FIG.

[0029]

[Control Circuit] The control circuit 27 of FIG. 1 is formed as shown in FIG. The control circuit 27 uses the position control error amplifier 8
1 and a speed control error amplifier 82. One input terminal of the position control error amplifier 81 is connected to the position signal line 22 via the switch 83, and the other input terminal is connected via the contact a of the switch 84 or via the contact b of the inverting circuit 85 and the switch 84. Is connected to the output line 26 of the D / A converter 25 of FIG. Speed control error amplifier 82
One input terminal is connected to the speed signal line 31 via the switch 86, the other input terminal is connected to the output terminal of the error amplifier 81 in the previous stage, and the output terminal is connected to the voice coil via the drive circuit 32 of FIG. It is connected to the motor 4.
The switch 84 is controlled by the seek direction signal on the line 28, and the contact b is turned on when the seek direction signal indicates the movement of the head 5 from the inner circumference to the outer circumference of the disk 1 (for example, high level). In the state (for example, low level) indicating that the head 5 is moved from the outer circumference to the inner circumference, the contact a is turned on. The switch 83 is controlled by the mode instruction signal on the line 29. When the mode instruction signal indicates the seek mode, that is, the speed control mode (for example, high level), the switch 83 is turned off, and when the mode instruction signal indicates the position control (tracking control) (for example, low level), the switch 83 is turned on. Turn on. The switch 86 is controlled by the NOT circuit 87 connected to the line 29, operates in the opposite manner to the switch 83, and is turned on at the seek time.

[0030]

[Data reading] When the disk 1 is rotated at a constant speed to cause a relative scanning motion between the disk 1 and the head 5, a reproduction signal shown in FIG. 11A corresponding to the recording data of the track format shown in FIG. Is obtained. Assuming now that a signal reproduced from the track data area of the servo sector is inputted to the read data forming circuit 11, a read pulse shown in a bar shape in FIG. 11B is obtained on the output line 13. The read data shown in FIG. 11C is obtained on the output line 14. The read pulse shown in FIG. 11B is generated at a position corresponding to the positive peak and the negative peak of the reproduced signal shown in FIG. In this embodiment, the start time of the track data area B2 is determined based on the detection of the first and second gaps G1 and G2 of the servo sector in the track format of FIG. The read data forming circuit 11 inputs a read pulse to the flip-flop 70 as shown in FIG. 4 to form data as shown in FIG. 11 (C). At this time, in the present embodiment, the read pulse corresponding to the negative peak generated later out of the positive peak and the negative peak representing logic 1 is used as data. In FIG. 11, all logic 1's correspond to one cycle of the AC waveform, so that even-numbered read pulses correspond to negative peaks. Therefore, the flip-flop control circuit 70a connected to the output line of the MMV69 of FIG. 4 measures the time until the fifth to fifth read pulses of the preamble A1 are counted by the built-in counter, and masks the five read pulses. Flip-flop 7 for
0 is applied to the reset terminal R. As a result, the flip-flop 70 becomes operable after the fifth read pulse is generated, the sixth read pulse corresponding to the negative peak is triggered, the output of the flip-flop 70 rises to a high level, and the next positive peak is reached. It falls with the read pulse corresponding to. The operation in which the flip-flop 70 rises by the read pulse generated after the two read pulses indicating the logic 1 is performed in the area of the sub-track data A2 and the area of the main track data Tno. The same is done in the data sector. Since there is always a positive peak before the negative peak, the positive peak exerts a buffering effect, and the displacement of the position of the negative peak due to noise is small. That is, if noise is added to the logic 0 region (non-magnetized region) before the positive peak, the position of the positive peak may be displaced, but the possibility of reaching the position of the negative peak is low. Therefore, accurate data reading can be performed.

Track data extraction pulses shown in FIG. 11D are generated on the output line 18 of the timing signal generating circuit 15 of FIG. 1, and track data In, T, GB and C are generated.
0 to C5 are extracted.

By the way, one bit of the data relating to the control of the track data of the servo sector is 1/2 of the main data.
It is written using the byte length. Therefore, the control (servo) data is recorded relatively stably. On the other hand, the main data of the data sector is 1 / of the control data.
It is recorded in a time width of 4 and is relatively unstable. If the comparison level of the waveform shaping is set low so that the main data can be detected sufficiently, as in the conventional device, the control data detection accuracy becomes poor. For example, when detecting a gap in a servo sector,
The function of the AGC circuit of the amplifier circuit 8 in FIG. 1 causes the waveform after the gap to spread in the gap direction, and when this is waveformd by the comparator, the time point at the end of the gap becomes inaccurate and the gap is accurately detected. Becomes impossible. Therefore, in this embodiment, the data of the line 13 is
The positive / negative input level of the comparators 74 and 75 in FIG. 7 is switched using the write / read enable signal (write enable signal) of the tasector. This level changes as shown by a solid line and a dotted line in FIG. 8C, and in the servo sector, the width of the window (window) pulse shown in FIGS. 8D and 8E is narrowed to improve the detection accuracy. Even if the detection accuracy in the servo sector is increased, the control data is stably recorded, so that the peak can be detected sufficiently.

[0033]

[Seek operation] When the current position of the head 5 is unknown, the seek of the target track (target track) is performed with reference to the track zero T0. In response to the power-on or the recalibration command, the disk 1 starts rotating,
A recalibration command is issued from the microcomputer 19 and the head 5 is positioned at the track zero T0 by a known method. That is, a direction signal for moving the head 5 in the outer peripheral direction of the disk 1 is given from the microcomputer 19 to the line 28, and data for moving the head 5 to the track zero T0 is sent to the line 24. Whether or not the head 5 is at the track zero T0 position is determined by the fact that the track zero detection data T included in the sub track code area A2 of FIG. 2 is logical zero and the data C0 to C5 of the main track code Tn0. Is located on the first track of the track group (0000
00).

Next, the head 5 is moved to the target track designated by the line 23 in FIG. The number of tracks that the head 5 has crossed is important for detecting the target track. There are roughly two types of typical calculation methods for the number of track groups traversed by the head 5. First, as disclosed in Japanese Patent Laid-Open No. 1-143085, the head 5 is moved in the radial direction of the disk 1 at a speed at which a track identification signal can be read at least once in each track group. Is the way. According to this method, it is possible to always recognize in which track group the head is located. In the second method, as disclosed in Japanese Patent Laid-Open No. 3-73477, a predetermined speed control signal for moving the head 5 to a target track is determined in advance, and the head 5 is moved based on this. However, the actual movement amount and the predicted movement amount are compared every time the track identification signal is read, and the jumping of the track group occurs between the Nth time of reading the track identification signal and the N + 1th time of reading the track identification signal. This is a method of moving the head 5 by judging whether it has occurred. In this method, when the skipping of the track group occurs, the number of passing track groups is corrected.

FIG. 12 shows the first seek method. That is, as shown in FIG. 10, while the head 5 diagonally traverses the track TR and moves 64 tracks (one track group), the track identification signal is read at least once, for example, to move to the target track T180. It is shown. In FIG. 12, tracks T15, T40, T80, T
Readings are being executed at 120, T160, T175 and T180. In general, it will pass the target track T180,
Control for returning to T180 is executed again, but for ease of explanation, it is shown that the head is positioned here when the target track T180 is detected. Based on each reading of the track identification signal, the microcomputer 19 receives decimal numbers 15, 40, 17, 57, 33,
Gray code track data corresponding to 48 and 53 are sent. The microcomputer 19 knows the change of the track group based on the change of the track data. That is, when the subsequent track data becomes smaller than the previous track data, it is determined that the track group has changed. Figure 1
In No. 2, it is assumed that the microcomputer 19 detects the change of the track group twice, and when the track data becomes 53, the head 5 is located on the target track. The microcomputer 19 multiplies the number of passed tracks by 64 tracks, and further adds the current track data to this to know the current track position. That is, the target track can be known by the calculation of 2 × 64 + 53 = 180.

When the track position of the head 5 is already known, the head is moved from the current track toward the target track without any recalibration operation. The operation in this case is also substantially the same as the operation in FIG.

[0037]

MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible. (1) The noise guard signal can be set to a plurality of cycles (a plurality of sets) instead of one cycle of the reproduced waveform, that is, one set of the positive direction magnetization area and the reverse direction magnetization area. Further, one bit of the track identification signal can be set to a plurality of cycles instead of one cycle of the AC of the reproduced waveform. When one bit is represented in a plurality of cycles in this way, the second read pulse after the second read pulse may be used as the data read timing without using the second read pulse in this 1-bit period. (2) The present invention can be applied to the case where the track identification signal is recorded by binary data (digital signal) of various codes other than the Gray code. (3) In order to discriminate the track group, a signal indicating the group address can be recorded in each track group. (4) The track zero detection signal can be written only in track zero T0. (5) The present invention can be applied to a magneto-optical recording / reproducing disk device. (6) In FIG. 1, the timing signal generation circuit 15,
Track identification signal detection circuit 16 and data extraction circuit 17
Is shown independently, but this is used as a controller
It can be formed into a C block. Further, these can be included in the microcomputer 19.

[0038]

As is apparent from the above, according to the present invention, it is possible to prevent or reduce interference due to noise.

[Brief description of drawings]

FIG. 1 is a block diagram showing a fixed magnetic disk device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a format of a track on a disc.

FIG. 3 is a diagram showing writing of track identification data to a track.

FIG. 4 is a diagram showing the read data forming circuit of FIG. 1 in detail.

5 is a waveform diagram showing a state of points A to O in FIG.

FIG. 6 is a waveform diagram showing states of points A to O in FIG. 4 when noise is generated.

FIG. 7 is a circuit diagram showing the gate pulse forming circuit of FIG. 4 in detail.

8 is a waveform diagram showing the states of points A to E in FIG.

9 is a block diagram showing the control circuit of FIG. 1. FIG.

FIG. 10 is a diagram showing the locus of the head during a seek.

11 is a waveform chart showing a state of each part of FIG.

FIG. 12 is a diagram for explaining a seek operation.

[Explanation of symbols]

 1 disk 4 voice coil motor 5 head 11 read data forming circuit

Claims (2)

[Claims] 1. A disk-shaped recording medium having a number of concentric tracks for recording and / or reproducing data by relative scanning motion with a signal conversion head, wherein the plurality of tracks are divided into a plurality of groups. A track identification signal is recorded by a predetermined code on each track of each group so that the head can read the track identification signal of each group, and the track identification signal of each group is the same. A disc-shaped recording medium, wherein a noise guard signal is written between bits constituting an identification signal. 2. The disc-shaped recording medium according to claim 1, wherein the predetermined code is a Gray code.