JP2600152B2 - Block address detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital audio tape recorder (DAT), a digital video tape recorder, etc.
The present invention relates to a block address detection circuit that detects an accurate block address from a data sequence when digital data transmitted in units of blocks is added with regularly changing block addresses indicating the order of each block.

[Prior art and its problems] In a DAT for recording / reproducing a digital audio signal, digital data transmitted in block units is added with a regularly changing block address indicating the order of each block. I try to transmit. In this case, for example, a synchronization signal 8 bits, an ID code 8 bits, a block address 8 bits, a parity 8 bits, and data 32
Recording / playback is performed with × 8 bits as one block. In the above data configuration, parity is for ID code and block address, and data is
It consists of digital audio in M and an error correction code.

The block address included in the block data is extremely important for reproduction data processing such as de-interleaving. However, if the block address itself is erroneously reproduced, the error is returned to increase. Therefore, high reliability is required for the block address. If the Bunlock address is incorrect due to dropout or random noise during reproduction, the reproduced data will be lost. Conventionally, interpolation is performed using the regularity of block addresses. That is, the difference between the previous block address and the current block address is obtained, and the block address is rewritten so that the difference becomes a constant value. In this case, the difference is detected without knowing the reliability of the previous block address value itself, and the current block address value is estimated and interpolated. Therefore, a highly reliable block address cannot be obtained. There was a problem.

[Object of the Invention] The present invention has been made in view of the above circumstances, and is intended for a case where digital data transmitted in block units are added with regularly changing block addresses indicating the order of each block. In the above, the reliability of estimation of the block address value is improved, and when the block address value becomes uncertain due to a random error and a burst error in the reproduced data, the determination control is performed so as not to use the block data. Accordingly, it is an object of the present invention to provide a block address detection circuit capable of preventing erroneous correction in a next-stage error correction process.

SUMMARY OF THE INVENTION The present invention detects an accurate block address from a data sequence transmitted in a form in which a regularly changing block address indicating the order of each block is added to digital data transmitted in block units. A first means for holding a parity check result of a previously transmitted block address and a parity check result of a currently transmitted block address in a block address detection circuit, and a previously transmitted or estimated block address and a currently transmitted block address. Second for judging regularity with block address
Means for detecting that the block address has been correctly and stably detected from the data obtained by the first and second means since the start of the data transmission; and A fourth means for detecting a burst error of the data sequence, and a block address transmitted this time as the first block address in the data sequence. After the stable state is detected by the third means, the previous value is used. And a sixth means for determining whether to adopt the block address output from the fifth means based on the results of the first to fourth means. Means are provided.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the tape recording state and recording format in the DAT will be described with reference to FIGS. FIG. 1 shows a tape recording state. On the magnetic tape 1, recording tracks 2a, 2b,... Inclined at a certain angle are formed corresponding to recording / reproducing heads. A track format shown in FIG. 2A is formed on each of the storage tracks 2a, 2b,. This track format is composed of an 8-block first subcode area SUB-
It comprises a PCM area of 1, 128 blocks, a second servo code area SUB-2 of 8 blocks, and the like. A tone signal is assigned to the PCM area, and a recording time, a song number, and the like are assigned to the subcode areas SUB-1, SUB-2.

The block format of the PCM data stored in the PCM area is, as shown in FIG. 2B, an 8-bit SYNC pattern, an 8-bit ID code, an 8-bit block address, an 8-bit parity, It consists of 256 bits (32 symbols) of PCM data.

Furthermore, the block format of the above SUB code is
As shown in FIG. 7C, the data includes an 8-bit SYNC pattern, an 8-bit ID code, an 8-bit block address / ID code, an 8-bit parity, and 256-bit (32 symbols) sub-code data. As shown in FIGS. 2 (b) and 2 (c)
As the block address in the PCM block format and the SUB block format, a regularly changing value indicating the order of each block is set for digital data transmitted in block units.

Next, the overall schematic configuration will be described with reference to FIG.
In the figure, reference numeral 11 denotes a symbol separation circuit, which is reproduced by a reproduction head, and further, digital reproduction demodulation data PD demodulated by a demodulation circuit is input via a terminal 12, and
The data bit clock PCK is input via the terminal 13. The data bit clock PCK is created by a PLL circuit (not shown) using the reproduced digital data. The symbol separation circuit 11 separates the serially input reproduced demodulated data PD into 10-bit symbol units and outputs the resulting data to the 10-8 conversion circuit 14, and performs a sync pattern detection operation. Signal is symbol counter 15, bit counter 16, sync loss counter 17
To each of the reset terminals R. Then. 10-8 above
The conversion circuit 14 receives the 10 sent from the symbol separation circuit 11
Converts data in bit units to data in 8-bit units,
Output to the parity check circuit 18 and the address selection circuit 19. This address selection circuit 19 latches the block address value and outputs the most significant bit MSB to the data area detection circuit 2.
In addition to the output to 3, the presence or absence of continuity with the previously adopted address value is checked, an address value with a high probability of being correct is selected and latched, and output to the address / data switching circuit 20 and the final address detection circuit 21. . On the other hand, the parity check circuit 18 checks the ID added next to the sync pattern and the parity added to the block address, and then converts the data to the address / data switching circuit 20.
When a parity error is detected, the detection signal PNG is output to the address determination circuit 22 and the data area detection circuit 23.

The bit counter 16 counts the bit clock transmitted via the terminal 13 and generates a carry signal every time 10 bits are counted, and the clock terminal CK of the symbol counter 15 and the sync protection gate generation circuit 24 And the timing signal generation circuit 25. The symbol counter 15 is a counter that detects a unit of one block with 36 symbols, generates a carry signal every 36 counts, and generates a clock signal CK of the sync loss counter 17, a sync protection gate generation circuit 24, and a timing signal generation circuit. twenty five
To enter. The sync protection gate generation circuit 24 outputs a sync protection gate signal of a predetermined width to the symbol separation circuit 11, and a sync pattern to be detected for each block is
It is designed to prevent detection at positions other than where it should be.
The sink loss counter 17 is a symbol counter.
The output pulse of 15 is counted and the sync pattern protection gate release signal GC is output to the sync protection gate generation circuit 24 and the burst error detection circuit 26, but in the state where the normal reproduction data is obtained, the signal from the symbol separation circuit 11 is output. The counter is always reset at a fixed interval by the sync detection signal, and the count base is set so that the release signal GC is not output. The sync loss counter 17 outputs a sync pattern protection gate release signal GC when a burst error occurs in a portion where data is not recorded or in a data area, and a burst error detection circuit as a signal for detecting a burst error. 26, and controls the sync protection gate signal in the sync protection gate generation circuit 24 to be a high level signal.

The timing signal generation circuit 25 is synchronized with the 8-bit parallel data after the 10-8 conversion based on the timing of each block and each symbol transmitted from the symbol counter 15 and the bit counter 16. Generates various timing signals. That is, the reset timing signal RST is output to the data area detection circuit 23 at the timing when the data of the symbol 0 is output in one block, and the parity check / latch timing signal PL is output to the address determination circuit 22 at the output timing of the parity data. Selects the block address / latch timing signal BL at the output timing of the block address.
19, and a parity timing signal PT which is at a high level during a period in which the parity is output after the PL output.
It outputs to the T generation circuit 29, the address selection circuit 19, and the address / data switching circuit 20, and also outputs a data clock DCLK synchronized with the output timing of each symbol data to a memory control unit (not shown) at the next stage. The data area detection circuit 23 and the burst error detection circuit 2
6. The window signal PCMWD and the window signal SUB sent from the servo circuit (not shown) via the terminals 27 and 28 are supplied to the final address detection circuit 21 and the address determination circuit 22.
WD is input. Then, the final address detection circuit 21
Operates in three places: a SUB area (1), a PCM area, and a SUB area (2). When the last block address is detected for each area, the block end signal LB becomes a high level, and becomes a low level at the end of the area. Output to the data area detection circuit 23. When the data area detection circuit 23 detects a reproduction data area from each of the input signals,
(Data start signal) Outputs the generation enable signal EN to the DST generation circuit 29. Further, the address determination circuit 22 includes:
Parity check signal PN from parity check circuit 18
Based on G and the block address continuous signal CONT from the address selection circuit 19, etc., a stable state is detected and an incorrect address value is corrected, and the initial flag IF and the stable state detection signal STA are output to the burst error detection circuit 26. At the same time, the initial flag IF is set to the address selection circuit 19
And outputs a DST generation stop signal DE2 to the DST generation circuit 29 when an abnormality in the block address is detected. The burst error detection circuit 26 performs a burst error detection process from each of the input signals, and outputs a DST generation stop signal DE1 to the DST generation circuit 29 when a burst error is detected. After the DST generation circuit 29 receives the DST generation enable signal EN from the data area detection circuit 23 and enters the DST generation enable state, the DST generation stop signal DE1
While DE2 is not supplied, the timing signal P
A data start signal DST is generated in synchronization with T and output to the memory control unit.

Next, details of the data area detection circuit 23, the burst error detection circuit 26, the address determination circuit 22, and the address selection circuit 19 in the above embodiment will be described.

FIG. 4 shows details of the data area detection circuit 23. The reset timing signal RST sent from the timing signal generation circuit 25 and the end block signal LB from the final address detection circuit 21 are input to the AND circuit 231, and the parity NG signal PNG from the parity check circuit 18 is input via the inverter 230. The output of the AND circuit 231 is input to an inverting input terminal of the AND circuit 232. Further, a window signal PCMWD and a window signal SUBWD supplied to the input terminals 27 and 28 in FIG. Further, the window signal SUBWD is input to the AND circuit 234. The parity NG signal PNG is further input to the AND circuit 234 via the inverter 230, and the most significant bit MSB of the block address sent from the address selection circuit 19 is input to the AND circuit 234. The signal is input to the AND circuit 232 via the OR circuit 235. Also,
The window signal PCMWD is input to the AND circuit 236. The parity NG signal PNG sent from the parity check circuit 18 is further supplied to the AND circuit 236 by the inverter 2.
MS input of the above and the above block address
B is input via the inverter 237, and the output signal is input to the AND circuit 232 via the OR circuit 235. The output signal of the AND circuit 232 is latched by the latch circuit 238 in synchronization with the clock pulse φ, and the latch output is input to the AND circuit 231 and the OR circuit 235, and the third signal is output as the DST generation enable signal EN. It is sent to the DST generation circuit 29 and the address determination circuit 22 in the figure. The data area detection circuit 23 detects a data area from the window signal PCMWD, the window signal SUBWD and other signals as shown in the timing chart of FIG. 5, and outputs a DST generation enable signal EN. Details will be described later.

FIG. 6 shows details of the burst error detection circuit 26. The sync pattern protection gate release signal GC sent from the sync loss counter 17 is input to the AND circuit 261 and sent from the address determination circuit 22. The coming initial flag IF is input to the inverting input terminal of the AND circuit 261. Further, the stable state detection signal STA from the address determination circuit 22 is input to the inverting input terminal of the AND circuit 262, and the window signal PCMWD and the window signal SUBWD are input to the AND circuit 262 via the OR circuit 263 and the AND circuit 264. Is done. Then, the output signals of the AND circuits 261 and 262 are sent to the latch circuit 266 via the OR circuit 265. The latch circuit 266 latches the input signal in synchronization with the clock pulse φ, inputs the input signal to the AND circuit 264, and outputs the same as the DST generation stop signal DE1 to the DST generation circuit 29 in FIG.

In the configuration of the burst error detection circuit 26 described above, when the read head is brought into contact with the recording track 2a of the magnetic tape 1 shown in FIG. 1 and reading thereof is started, the PCM data area is read from the servo circuit (not shown). Show window signal PCM
The window signal SUBWD indicating the WD and SUB data areas is input to the OR circuit 263, and the output signal of the OR circuit 263 becomes the data window signal shown in FIG. This data window signal is a signal corresponding to the track format shown in FIG. 2A, that is, a first SUB code area SUB-1, a PCM data area, and a second SUB code area SUB.
When -2 is read, the level is high, and the others are at the low level. Then, the gate control of the AND circuit 264 is performed by the data window signal.

On the other hand, a sync pattern protection gate release signal GC shown in FIG. 7B is sent to the AND circuit 261 from the sync loss counter 17 in FIG. This sync pattern protection gate release signal GC is a low level signal during the data reproduction period unless a burst error has occurred due to dropout or the like in the read data. Is no longer detected, so that the burst error occurrence portion goes high as shown in FIG. 7 (b). Also, AND circuit 261
The initial flag IF input to the inverting input terminal is always at the high level when the sync pattern protection gate release signal GC is at the high level as shown in FIG. Therefore, the output of the AND circuit 261 is held at a low level.
The stable state detection signal STA sent from the address determination circuit 22 to the AND circuit 262 normally has a signal waveform in which the initial flag IF is inverted as shown in FIG. Is generated, the level becomes low during that time. The AND circuit 262 is supplied with a “0” signal from the AND circuit 264 except when dropout occurs, and the gate is closed, and the output signal is “0”. In a state where a burst error has not occurred, the outputs of the AND circuits 261 and 262 are “0”, and the “0” signal is held in the latch circuit 266, so that the DST generation stop signal DE1 is not output. A burst error occurs in the data read from the magnetic tape, and as shown in FIG. 7 (b), for example, the sync pattern is not detected several times in the PCM area and the sync pattern protection gate release signal GC becomes "1" (high level). ), Since the initial flag IF is “0” at this time, the output of the AND circuit 261 becomes “1” and is sent to the latch circuit 26 via the OR circuit 265. This latch circuit 266
Latches the input signal "1" in synchronization with the clock pulse φ, and outputs the DST generation stop signal DE1 as shown in FIG.
To the DST generation circuit 29 and to the AND circuit 264. At this time, since the data window signal is “1”, the output of the AND circuit 264 becomes “1”, and the gate of the AND circuit 262 is opened. During the occurrence of the burst error, since the stable state detection signal STA is at the low level, the output of the AND circuit 262 becomes “1” and is sent to the latch circuit 266 via the OR circuit 265. Therefore, until the burst error is eliminated and the stable state detection signal STA returns to the normal high level, the “1” signal is latched by the latch circuit 266, and the DST generation stop signal DE1 is held at the “1” signal level and the DST The generation circuit 29 is prohibited from generating the data start signal DST.

FIG. 8 shows the details of the address determination circuit 22, and the parity NG signal sent from the parity check circuit 18.
PNG is input to the latch circuit 221. This latch circuit 22
1 latches the parity NG signal PNG in synchronization with the fall of the parity check / latch timing signal PL, and outputs the latched data to the parity check / latch timing signal PL.
Latch circuit 222 latches in synchronization with the rise of PL. The data latched by the latch circuits 221 and 222 are input to the decoder 223 together with the block address continuous signal CONT sent from the address selection circuit 19 and directly through the inverters 224, 225 and 226, respectively. The decoder 223 has 6-bit output lines l1 to l6, inputs the output of the l1 line to the set terminal S of the flip-flop 228 and the reset terminal R of the flip-flop 2212, and outputs the output of the l2 line to the AND circuit 229. Through or circuit 2
210, the outputs of l3 and l4 are input to the OR circuit 2210, and the OR circuit 2211 is input to the reset terminal R of the flip-flop 228, and the outputs of the l5 and l6 lines are output to the OR circuit 221.
3 and to the OR circuit 2210 via the AND circuit 2214. Also, the window signal PCMWD and the window signal SUB
The output of the NOR circuit 2215 to which WD is input is the OR circuit 2215.
The signal is input to the reset terminal R of the flip-flop 228 via 11. Then, the output of the flip-flop 228 is used as the stable state detection signal STA as the burst error detection circuit 26.
Sent to The flip-flop 2212 is set by the rising edge of the signal of the NOR circuit 2215 to which both the window signal PCMWD and the window signal SUBWD are input. The output of the flip-flop 2212 is output as an initial flag IF, input to the inverting input terminal of the AND circuit 229, and further input to the OR circuit 2210 via the AND circuit 2214. The output signal of this OR circuit 2210 is DS
It is sent to the DST generation circuit 29 as a T generation stop signal DE2.

In the configuration of the address determination circuit 22 described above, the latch 221 stores the parity NG for the current block address.
The signal PNG is latched and the parity NG signal PNG for the previous block address is latched in the latch circuit 222. Then, as shown in FIG.
The DST generation stop signal D according to a combination of the present and previous parity NG signals PNG latched in 2, the block address continuous signal CONT sent from the address selection circuit 19, and the initial flag IF output from the flip-flop 2212.
The output of E2 is determined. That is, the flip-flop 22
If 12 is set and the initial flag IF is "1", the parity NG signal of the current block address
If PNG is "1", the DST generation stop signal DE2 is output regardless of whether the block address continuous signal CONT is "0" or "1". When the initial flag IF is “0”, the parity NG signal PNG of the previous block address is “1”, the parity NG signal PNG of the current block address and the block address continuous signal CONT are “0”, and , Parity NG signal PN for the previous and current block addresses
When both G are “1”, the DST generation stop signal DE2 is output.

As described above, in the determination of the block address in the address determination circuit 22, the initial flag IF, the parity NG signal PNG of the previously read block address, the parity NG signal PNG of the current block address, the previous block address and the current block Continuity with the address,
Are used. The above-mentioned initial flag IF is “1” at the start of the data area, and is in a stable good state (the previous parity and the current parity are OK).
Where the address is continuous) is at least 1
This signal is "0" when it occurs twice. At the start of data detection, the read address has only the correctness / incorrectness information of the parity. However, once the stable state is established, the interpolation based on the continuity of the block address can be used. The concept of ensuring the reliability of the address value is different between "1" and "0". Also, the parity NG signal PNG of the previous and current block addresses of
This is a result of checking parity added to two symbols of the D code. Further, the above indicates whether or not there is continuity between the block address used last time and the block address read this time. If the value is the backward or jump from the previously adopted value, it can be determined that the current read value or the previously adopted value is abnormal.

FIG. 10 shows the details of the address selection circuit 19, and the 8-bit data sent from the 10-8 conversion circuit 14 in FIG. This latch circuit 191
Latches the input data in synchronization with the falling edge of the block address / latch timing signal BL from the timing signal generation circuit 25, inputs the input data to the comparison circuit 192, and outputs the tri-state buffer 194 via the tri-state buffer 193. And an 8-bit latch circuit 195. The latch circuit 191 outputs the most significant bit MSB of the latch data to the data area detection circuit 23 in FIG. The operation of the tri-state buffer 193 is controlled by the output of the OR circuit 1910 to which both the initial flag IF and the DST generation stop signal DE1 output when a burst error is detected, and the tri-state buffer 194 is operated by the parity timing signal PT. Controlled. Then, the latch circuit 195 latches the input data in synchronization with the rise of the block address / latch timing signal BL. The latch data of the latch circuit 195 is the half adder 1
After “+1” by 96, the latch circuit 199 is synchronized with the fall of the block address / latch timing signal BL.
, And the latched data is input to the comparison circuit 192 and the tri-state buffer 197. The comparison circuit 192 is composed of the latch data of the latch circuit 191 and the latch circuit.
The block address is compared with the latch data of 199, and a block address continuous signal CONT is output according to the comparison result. That is,
The comparison circuit 192 determines that there is continuity when the current block address latched by the latch circuit 191 is equal to the “previous block address + 1” latched by the latch circuit 199. A "0" signal is output as no signal. On the other hand, the tri-state buffer 197
Is controlled by an initial flag IF and a DST generation stop signal DE1 provided via an OR circuit 1910 and an inverter 198, and its output signal is sent to a latch circuit 195 and a tristate buffer 194. The signal output from the tri-state buffer 194 is used as a block address and the address / data switching circuit shown in FIG.
20 and the final address detection circuit 21.

Next, the overall operation of the above embodiment will be described. In FIG. 3, a symbol separation circuit 11 reproduces the recording data of the magnetic tape 1 by a reproduction head, further divides the serial digital data PD demodulated by a demodulation circuit into symbol units of 10 bits, and forms a 10-bit parallel data. As data
Output to the 10-8 conversion circuit 14. This 10-8 conversion circuit 14
Converts the data divided every 10 bits into 8-bit symbol data, and outputs it to the parity check circuit 18 and the address selection circuit 19. The parity check circuit 18 checks the parity added to the ID data and the block address as shown in FIGS. 2 (b) and 2 (c). The parity NG signal PNG serving as the level is output to the address determination circuit 22 and the data area detection circuit 23, and the data is output to the address / data switching circuit 20. The address / data switching circuit 20 is configured to store the data output from the parity check circuit 18 and the address selection circuit 19
Is switched by the arity timing signal PT from the timing signal generation circuit 25 and output. The address / data switching circuit
The data output from 20 is the data clock DCLK output from the timing signal generation circuit 25 as shown in FIG.
And a data start signal D output from the DST generation circuit 29.
It is sent to the memory control circuit together with ST.

Further, the symbol separation circuit 11 performs an operation of detecting a sync pattern recorded at the head position of the PCM block and the SUB block with respect to the reproduced demodulated data.
The bit counter 16 and the sync loss counter 17 are reset. After being reset by the sync pattern detection signal, the bit counter 16 counts up by the PLL clock PCK, generates a pulse signal indicating a symbol unit every 10 bits, and outputs a symbol counter 15, a sync protection gate generation circuit. 24 and timing signal generation circuit
Output to 25. The symbol counter 15 counts the output pulse of the bit counter 16 and generates a pulse signal indicating one block every 36 counts, and sends the pulse signal to the sync loss counter 17, the sync protection gate generation circuit 24 and the timing signal generation circuit 25. Output. The timing signal generation circuit 25 generates various timing signals synchronized with the 8-bit parallel data after the 10-8 conversion based on the pulse signals output from the bit counter 16 and the symbol counter 15 to detect the data area. Circuit 23, address determination circuit 22, address selection circuit 19, address / data switching circuit
Output to 20 mag.

The data area detection circuit 23 shown in detail in FIG. 4 detects the reproduction period of the data area when the window signal PCMWD or the window signal SUBWD sent from the servo circuit is input, and as shown in FIG. Outputs DST generation enable signal EN. The condition for judging that the data area reproduction period has been detected is that the parity is OK in the window signal and the most significant bit MSB of the block address at that time (“0” in the PCM data area, “1” in the SUB data area) ") And each window signal PCMWD, window signal
This is one of the enable conditions for generating DST when the timing of SUBWD matches. By satisfying the above condition, the output of the AND circuit 234 or the AND circuit 236 becomes “1”, and the “1” signal is output from the AND circuit 232. The output "1" signal of the AND circuit 232 is latched by the latch circuit 238, and this latch signal is sent to the DST generation circuit 29 as the DST generation enable signal EN. The DST generation enable signal EN is circulated and held by the latch circuit 238 via the OR circuit 235 and the AND circuit 232.

The condition for stopping the output of the DST generation enable signal EN is that the parity is OK, the last block address is detected, and the start timing (reset timing signal RST) of the 32 symbol data of the block. When the above condition is satisfied, the output of the AND circuit 231 becomes "1", the gate of the AND circuit 232 closes, and the "0" signal is latched by the latch circuit 238. As shown in FIG.
The generation enable signal EN falls. When the last block address cannot be detected due to a burst error or the like, the DST generation enable signal EN falls when the window signals PCMWD and SUBWD become "0" as shown in FIG. 5 (f). Then, the DST generation enable signal EN output from the data area detection circuit 23 is sent to the DST generation circuit 29 and the address determination circuit 22.

The address decision circuit 22 sets the flip-flop 2212 by the output of the NOR circuit 2215 to which both the window signals PCMWD and SUBWD are input, as shown in detail in FIG. 8, and sets the initial flag IF to the "1" signal level. Go up.
Therefore, the initial flag IF is always "1" at the time of starting reproduction of the first block of each data area. In this state, data reading is started and the latch circuits 222, 22
When the pit signal NG for the previous block address and the current block address is latched at 1, and the block address continuous signal CONT is supplied from the address selection circuit 19, the decoder 223 checks these states.
When it is determined that the respective parities of the previous block address and the current block address are correct and that there is continuity between the previous block address and the current block address, the output of the l1 line of the decoder 223 becomes “1”, and the flip-flop 2212 is reset and flip-flop 22
8 is set. As a result, the initial flag IF becomes "0" and the stable state detection signal STA becomes "1". The initial flag IF is "1" at the start of data reproduction, and once a stable good state is detected, the initial flag IF remains "0" until the end of the data area. In addition, the stable state detection signal
The STA becomes “0” when both the previous parity check and the current parity check are incorrect, and becomes “1” when the stable state is restored again.
And the signal fluctuates according to the result of the parity check. Thus, the address determination circuit 22 determines whether the previous and current parity NG signals PNG, initial flag IF
When the combination shown in FIG. 9 is obtained from the block address continuous signal CONT, the OR circuit 2210 outputs the DST generation stop signal DE2. The address selection circuit 19 shown in detail in FIG. 10 is a timing signal generation circuit.
When a block address / latch timing signal BL is supplied from 25, the latch circuit 191 latches the current block address sent from the 10-8 conversion circuit 14 at the falling edge. Here, at the start of reproduction of the first block of each data area, the initial flag IF provided from the address determination circuit 22 is at the "1" signal level. While this initial flag IF is "1", the tri-state buffer
193 turns on, tri-state buffer 197 turns off,
The block address previously held in the latch circuit 191 is latched by the latch circuit 195 as the previous block address via the tristate buffer 193 at the rise of the block address / latch timing signal BL. Also, once the stable state is established, the initial flag IF
Becomes "0" signal level, the tri-state buffer 193 is turned off and the tri-state buffer 197 is turned on. At this time, the block address held in the latch circuit 195 is set to "+1" by the half adder and the latch circuit is turned on. 199
After that, the data is latched by the latch circuit 195 as the previous block address via the tri-state buffer 197. As described above, the current block address is latched by the latch circuit 191, and the previous block address is latched by the latch circuit 195.

Then, after the previous block address latched by the latch circuit 195 is incremented by “1” by the half adder 196 and latched by the latch circuit 199, the current block address latched by the latch circuit 191 is compared with the current block address by the comparator 192. If they match, a block address continuous signal CONT is output to the address determination circuit 22. If they do not match, the block address continuous signal CONT is held at the "0" signal level. Then, when the parity timing signal PT is sent from the timing signal generation circuit 25, the tristate buffer 194 is turned on, and the block address latched by the latch circuit 191 or the latch circuit is selected according to the initial flag IF. Is output as the current block address. That is, when the initial flag IF is "1", the tri-state buffer 193 is turned on, the block address held in the latch circuit 191 is taken out via the tri-state buffers 193 and 194, and the address / data switching is performed as the current block address. Sent to the circuit 20. When the initial flag IF is “0”, the tri-state buffer 197 is turned on, and the block address latched by the latch circuit 195 is “+1” by the half adder 196.
After being latched by the latch circuit 199, it is taken out via the tri-state buffers 197 and 194 and sent to the address / data switching circuit 20 as the current block address.
The address selection circuit 19 sets the initial flag IF to "1".
In this case, the tri-state buffer 193 is turned on, the currently read address latched by the latch circuit 191 is adopted, and the tri-state buffer 194 outputs the block address. After that, when a good stable state is detected and the initial flag IF once becomes "0", the tri-state buffer 197 is turned on thereafter, and the previous block address held in the latch circuit 195 is added to the half adder 196. +1 is latched by the latch circuit 199 and output from the tri-state buffer 194. When the initial flag IF becomes "0", a special state is set thereafter.
That is, as long as a burst error does not occur, whether a reliable block address and data of 32 symbols are used or discarded depends on the occurrence of the data start signal DST. Therefore, once the stability condition is satisfied,
The reverse of the address value is prevented from occurring, and unreliable data is discarded early so that the error correction processing at the next stage can be reliably performed.

More specifically, when the initial flag IF is "1" as shown in FIG. 9, the address determination circuit 22 starts the data. At this time, if the parity of the address read this time is OK, the DST is stopped. The signal DE2 is not output, and the DST generation circuit 29 generates the data start signal DST. Next, after the initial flag IF is set to "0" and a reliable address is detected, the following determination processing is performed.

If the previous parity is NG and the current parity is OK and there is no address continuity, it is determined that the block address which was NG last time is incorrect.

Irrespective of the continuity of the block addresses, if the previous and current parities are consecutively NG, it is determined that the parity is abnormal.

In the above two cases, the data start signal DST
And stop throwing the suspect data block.
That is, one series of the error correction code added to the data symbol is in the data block direction, and the code is completed for two blocks. In this case, even if the suspicious data is used only for one block, it can be detected that the data is erroneous by the error correction code. However, if the suspicious data block is used for two consecutive blocks and the address value is incorrect, Erroneous correction is performed by the error correction processing circuit, and abnormal sounds are generated in the reproduced sound. Therefore, when two suspicious data blocks are consecutive, the address determination circuit 22 prohibits the output of the data start signal DST by the DST generation stop signal DE2 and does not use the data block.

Then, the block address to be adopted once passes the stable state (when the parity of two blocks is OK and the address value has continuity in succession) and the initial flag is passed.
When the IF becomes “0”, the tri-state buffer 197 turns on, the previous block address holding the latch circuit 195 is incremented by “+1” by the half adder 196, and is latched by the latch circuit 199. Tri-state buffer
It is output to the address / data switching circuit 20 as the current block address via 1971 and 194. With the above processing, the backward movement of the adopted block address is reliably prevented.

However, if a burst error (approximately 3 blocks or more in width and 100 μsec or more in time) occurs in the reproduced data, and the reproduced data clock is corrected by the PLL circuit, even if the initial flag IF is “0”, the previous address is not reached. A difference occurs between the value of "+1" and the read address, and thereafter, a normal address may not be obtained even if the burst error ends. However, such a situation is prevented by the burst error detection circuit 26 shown in detail in FIG.

In the burst error detection circuit 26, a window signal PCMWD indicating a PCM data area and a window signal SUBWD indicating a SUB data area shown in FIG. Given. When the initial flag IF (FIG. 7 (c)) given to the AND circuit 261 becomes "0" and is in a stable state, a burst error is generated by the sync pattern protection gate release signal GC (FIG. 7 (b)). Detect the occurrence of The sync pattern protection gate release signal GC becomes "1" signal level when the sync pattern cannot be detected several times in the protection gate due to the occurrence of dropout or the like, and opens the gate of the AND circuit 261. As a result, the output signal of the AND circuit 261 becomes "1" and is latched by the latch circuit 266 via the OR circuit 265. This latch signal is used as the DST generation stop signal DE1 shown in FIG.
Sent to This DST generation stop signal DE1 is shown in FIG.
While the stable state detection signal STA shown in (1) is at the “0” level, it is circulated and held by the latch circuit 266 via the AND circuits 264 and 262 and the OR circuit 265. Then, when the burst error ends and the stable state detection signal STA becomes the “1” level again, the gate of the AND circuit 262 closes, “0” is latched by the latch circuit 26, and the DST generation stop signal DE1 is released. .

The DST generation stop signal DE1 is input to the OR circuit 1910 of the address selection circuit 19 together with the initial flag IF as shown in FIG. 10, and during a burst error, the tristate buffer 193 is turned on by the DST generation stop signal DE1. Is done. Therefore, the block address reproduced from the tape is output by the tristate buffer 194, and the reproduced block address value is latched in the latch circuit 195 as the previous block address.
When the stable state is reached again, the DST generation stop signal D
E1 is released, the tri-state buffer 197 is turned on, and the correct block address is output from the tri-state buffer 194.

Then, the DST generation circuit 29, based on the DST generation enable condition from the burst error detection circuit 26, the address determination circuit 22, and the data area detection circuit 23, generates data synchronized with the parity timing signal PT from the timing generation circuit 25. Generates a start signal DST and outputs it to the memory control unit.

On the other hand, when the parity timing signal PT given from the timing signal generation circuit 25 is "0", the address / data switching circuit 20 selects and outputs the data from the parity check circuit 18 and outputs the parity timing signal PT. When "1", the block address from the address selection circuit 19 is selected and output. This address / data switching circuit 20
Are sent to the memory controller together with the data clock DCLK output from the timing signal generation circuit 25. The memory control unit operates when a data start signal DST is given from the DST generation circuit 29 as shown in FIG. 11, and writes data to a memory area specified by a block address value in synchronization with a data lock DCLK. Perform

[Effects of the Invention] As described above in detail, according to the present invention, digital data transmitted in block units are transmitted in a form in which a regularly changing block address indicating the order of each block is added. A block address detection circuit for detecting a block address from a data sequence, a first means for holding a parity check result of a previously transmitted block address and a parity check result of a currently transmitted block address, and Second means for judging the regularity between the block address and the block address transmitted this time, and the block address being correctly and stably obtained from the data obtained by the first and second means after data transmission is started. Means for detecting that the data has been detected, and a burst in the transmitted data sequence. A fourth means for detecting an error, and a block address transmitted this time is output as the first block address in the data sequence. After the stable means is detected by the third means, a value based on the previous value is used. Fifth means for outputting a value guessed this time, and sixth for judging and controlling whether to adopt the block address output from the fifth means based on the results of the first to fourth means. Means to improve the reliability of the estimation of the block address value, and when the block address value becomes uncertain due to a random error or a burst error in the reproduced data, the block data is not adopted. By performing the determination control described above, it is possible to prevent erroneous correction in the next-stage error correction processing.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention. FIG. 1 shows a track forming state on a magnetic tape, FIG. 2 shows a track format and a block format, and FIG.
FIG. 4 is a block diagram showing the overall circuit configuration, FIG. 4 is a block diagram showing details of the data area detection circuit, and FIG.
FIG. 6 is a timing chart for explaining the operation of the data area detection circuit shown in FIG. 6, FIG. 6 is a block diagram showing details of the burst error detection circuit, and FIG. 7 explains the operation of the burst error detection circuit shown in FIG. FIG. 8 is a block diagram showing details of the address determination circuit, FIG. 9 is a diagram showing the operation of the address determination circuit shown in FIG. 8, and FIG. 10 is a block showing details of the address selection circuit. FIG. 11 is a timing chart showing a data transfer state. 1 ... magnetic tape, 2a, 2b ... recording track, 11 ... symbol separation circuit, 12 ... reproduction demodulation data input terminal, 13 ...
... PLL clock input terminal, 14 ... 10-8 conversion circuit, 15 ...
... Symbol counter, 16 ... Bit counter, 17 ... Sync loss counter, 18 ... Parity check circuit, 19 ...
... Address selection circuit, 20 ... Address / data switching circuit, 21 ... Last address detection circuit, 22 ... Address determination circuit, 23 ... Data area detection circuit, 24 ... Sink protection gate generation circuit, 25 ... Timing Signal generator, 26…
... Burst error detection circuit, 27, 28 ... Window signal input terminal, 29 ... DST generation circuit.

Claims (1)

(57) [Claims] A block address detection circuit for detecting a block address from a data sequence transmitted in a form in which a regularly changing block address indicating the order of each block is added to digital data transmitted in block units. A first means for holding a parity check result of the transmitted block address and a parity check result of the currently transmitted block address, and determining whether the previously transmitted or estimated block address is equal to the currently transmitted block address. A second means for judging the regularity, and a third means for detecting that the block address has been correctly and stably detected from the data obtained by the first and second means since the data transmission was started. Fourth means for detecting a burst error in a transmitted data sequence, and a data system The block address of the initial output block address to be transmitted this time in, the third
The fifth means for outputting a value obtained by measuring the current value based on the previous value after the stable state is detected by the means,
A block address detection circuit comprising: a sixth means for determining and controlling whether to adopt the block address output from the fifth means based on a result of the fourth means.