JPS61190755A - Address circuit - Google Patents

Abstract

PURPOSE:To generate a correct address and prevent a transmission error using an ID code, by loading the cord from a latch circuit and generating the address by the output of a counter except it, when a control circuit detects correctly the address. CONSTITUTION:An address cord 21 latched by the latch circuit 4 of an address circuit is taken into the control circuit 7, and a decision circuit of the circuit 4 decides whether the code 21 is correct or not by an output of a parity check circuit 5. When this code 21 is correct, a multiplexer circuit 8 is switched to the circuit 4 side, and the code is loaded to a count circuit 6 by a load pulse 14. Further, except is, an address 12 is generated by the output of the count circuit 6. Then, the ID code is correctoly decided, the correct address 12 is generated, and an influence by the transmission error caused by the drop out, etc. is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a digital processing circuit in a PCM playback device, and particularly to an address circuit thereof.

[Background of the invention]

In a PCM playback device, as a means for generating an address for playback digital data, Japanese Patent Application Laid-Open No. 58-12520
It is explained in issue 8.

However, such address generation means is required to generate a correct address more quickly and to have faster recovery characteristics when an error is detected.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an address circuit that correctly generates an address when a signal is lost due to dropout or the like during playback.

[Summary of the invention]

In the present invention, the continuity of the address code and the detection conditions of the parity check circuit are changed by the output of the detection circuit that detects the beginning of the data, and the present invention is composed of a means for generating an address from the address code and a counter that receives a synchronization signal as input. It also has other address generation means, and outputs this code when it correctly detects the address code.
Then, this counter is loaded, and in other cases, the address is read from the output of this counter.

[Embodiments of the invention]

An embodiment of the present invention is shown in FIG. 1 below.

In FIG. 1, 1 is a synchronization detection protection circuit, 2 is a timing circuit for operating each circuit based on a synchronization signal, and 3 is a timing circuit for operating each circuit based on a synchronization signal.
4 is an S/P conversion circuit for converting input serial data into parallel data; 4 is a latch circuit for temporarily storing the address code in the data; 5 is an address code, S, and an identification circuit to be described later. This is a parity check circuit for detecting errors in the code (hereinafter abbreviated as ID code).6 is a counter circuit that counts up by +1 for each block to generate an address, and 7 is a parity check circuit for detecting errors in the detected address code. A control circuit 8 controls whether or not to perform protection, and 8 outputs a detected address code 21 and a protection output 22 according to a control signal from the control circuit 7.
This is a multiplexer circuit that switches between and outputs. 1
2 is the generated address output, 13 is the switching output of the multiplexer, and 14 is the load input of the counter.

Here, the control circuit 7 is constituted by a circuit shown in FIG. In FIG. 2, 40 is a latch circuit for latching the address code 21 latched by the latch circuit 4, 41 is an addition circuit for adding +1 to the latched value, and 42 is the addition value and the next latched value. a comparison circuit for detecting matching of address codes; 43;
44 is a flag circuit for temporarily storing the result of the parity check and the detection state of the synchronization code, and 44 is a data area detection circuit that counts the number of undetectable synchronization signals and considers data undetectable when a predetermined number or more of undetectable signals occur. circuit, 4
5 is a determination circuit that determines whether the address code is correct based on the outputs of the comparison circuit 42, the flag circuit 43, and the data area detection circuit 44, and generates a control signal to protect the address; This is an 18th sync detection circuit that detects a synchronization signal.

FIG. 3 shows the reproduced signal. The reproduced signal is an intermittent signal as shown in the figure. This signal is further divided into a plurality of block signals, and each block signal includes a 5 sync signal 60, an ID signal 61 for identification, a code unique to each block, and an address signal that steps up one by one from the beginning ( The AD multiplied signal 62, for example, is MOD2 of the ID code 61 and AD code 62, and is composed of a parity code 63 and a data code 64 for detecting errors in these two codes during reproduction.

The present invention will be explained in detail below. When reproducing the intermittent fg signal shown in Fig. 3, the beginning of the data is detected correctly,
Data 64 must be captured in order. For this reason, in this embodiment, correct address generation is performed based on the synchronization detection state using the continuity of the address code and the parity code.

First, a signal is input and a flag signal 10 indicating whether a synchronization signal is detected is obtained. This signal enters the discrimination circuit 7 and outputs a flag indicating that the 15th ync detection circuit has detected the 15th ync detection signal 50 first.

The ID code 61, address code 62, parity code 63, and data 64 recorded after the synchronization signal 60 sequentially enter the S/P conversion circuit 3, and then the address code enters the latch circuit 4, the ID code 61, and the address code 62. , the parity code 63 is input to the parity circuit 5.

The address code 21 latched by the latch circuit 4 will be input to the control circuit 7. After the address code 21 is latched by the latch circuit 4o, it will be 1+1 by the adder circuit 41.
The output of the adder circuit 41 and the address code 21 are input to the comparison circuit 42, and it is checked whether these two codes match.
sent to. During normal playback, the address code is stepped up one by one for each block, so the outputs of the comparison circuit always match, making it possible to check the continuity of the address code.

On the other hand, the output 23 of the parity check circuit 5 is also
is input. Here, when the determination circuit 45 can check the parity check output and the continuity of the address code, it determines that the address code taken into the latch circuit 4 is correct, and switches the multiplexer circuit 8 to the latch circuit 4 side, and also switches the multiplexer circuit 8 to the latch circuit 4 side. Load this address code with load pulse 14.

On the other hand, when one or both of the two inputs entering the discrimination circuit 45 are NG, the multiplexer circuit 8
The address is generated by switching the address to the counter circuit 6 configured to count up one by one for each block. However, the continuity of the address code cannot be checked using the first detected block signal. If the same pattern as the synchronization signal is mistakenly detected in an area where no data is recorded due to noise, dropouts within the recording area, etc. There is a problem with protection when signal loss occurs. Therefore, two types of protection are performed in the 15th sync detection circuit and the data area detection circuit.

Regarding the first detected address code 21, the comparison circuit 42 does not check the continuity of the address code, but makes a determination based on the parity check output 23. In other words, when the first synchronization is detected, the 18th YNC output 50 is output, and based on this output, the discrimination circuit 45 does not check the continuity of the address code for a certain period of time, but performs a parity check. The determination is made based only on the output 23. When the parity check circuit 5 detects no error, the determination circuit 45 determines that the address code 21 taken into the latch 4 is correct. As a result, the latch circuit 4 side is selected in the multiplexer circuit 8, and the address output 21 is loaded into the counter circuit 6.

Further, if an error is detected by the parity check, the determination circuit 45 determines that the address code 21 is incorrect. As a result, the protection output 22 is selected in the multiplexer circuit 8. Furthermore, in the counter circuit 6, the address output 21 is not loaded;
The previous value is counted up by +1. In other words, the first
Since the protection counter circuit 6 has been reset before the first synchronization detection is performed, the output corresponding to the first synchronization pulse becomes 1o", and the address output is 1o".
A value of 0" is output.

As described above, for the first synchronization pulse, the continuity of the address code is not checked, and if no error is detected as a result of the parity check, the address code is output as an address, and the address code is output as an address. When detected, the output of the counter 6 is output as an address, thereby generating a correct address from the first data.

Next, the operation of address protection when a synchronization signal is detected outside the data area due to noise or the like will be described.

In FIG. 4, 80 is a synchronization detection output erroneously detected outside the data area. 81 shows the operation of a conventional address protection circuit.

Start address protection operation based on synchronization detection output 80,
The address protection operation continues until synchronization is detected in the data area.

As a result, the first address code of 2 cannot be read into the data area, and the value "n" generated based on the synchronization detection output 80 is output, causing an address error. Ta.

Reference numeral 82 shows the address output 21 of the address protection circuit of this embodiment. The data area detection circuit 44 in FIG. 2 detects that a predetermined number or more of synchronization failures occur consecutively and inputs the detected number to the determination circuit 45.

The determination circuit 45 determines whether the address code has already been detected from the comparison circuit 42 and the parity check output 23, and if it is outside the data area, resets the counter 6 and the 15th sync detection circuit 46, and detects the synchronization signal. It enters a standby state until

On the other hand, if it occurs due to signal loss within the data area, the 15th sync detection time v! By resetting only r46 and setting it to immediately capture the address code based on the result of the parity check circuit when the synchronization signal is obtained again, the recovery of address generation is accelerated.

As a result, address generation is performed again from the point where the synchronization signal is detected next, so that data is written to the correct address.

As described above, according to the present invention, the first address protection has the same protection capability as before, and in the continuous detection state of data, by checking the parity and the continuity of the address code, All address code errors can be detected and correct address protection can be performed. Furthermore, by detecting the data area, it is possible to prevent address errors due to incorrect synchronization codes outside the data area.

FIG. 5 shows another embodiment according to the present invention.

The same symbols as in FIG. 1 have the same functions. 90 is the address output selected by the multiplexer 8 and the control circuit 7
This is a multiplexer circuit that switches between the initial address 91 generated in the above and uses it as a preset input for count 6.

92 is a switching signal generated by the control circuit 7.

In this embodiment, the output of the data area detection circuit 44 allows
The counter circuit 6 is loaded with an arbitrary preset value outside the data area. This means that when the AD code starts from an arbitrary address address, for example, address 1128, the start address of the counter is set to 1128.
28". This is the determination circuit 4.
5, when it is determined that the area is outside the data area, the initial address 91 is set to 1128", the multiplexer 90 is switched to the initial address 91 side, and the counter circuit 6 is placed in the load state. In this way, the counter circuit is loaded from an arbitrary address. It is possible to start it.

FIG. 6 shows another embodiment according to the present invention.

In FIG. 6, the same symbols as in FIG. 1 have the same functions.

In FIG. 6, 95 is an ID code check circuit, 96
is the ID code check output.

The ID code check circuit has the configuration shown in FIG.
Reference numeral 97 indicates n latch circuits, and 98 indicates a matching circuit for the outputs of the n twisted code latch circuits 97.

FIG. 8 shows the configuration of the control circuit 7, and the same reference numerals as in FIG. 2 have the same functions. 100 is an AD code correction circuit.

This embodiment takes advantage of the fact that the ID code does not change for each block, and detects whether the code has the same value continuously, thereby correcting errors in the address code and generating addresses. It is.

The ID code is a code indicating arrangement conditions, etc., and usually the same code is always input. As shown in FIG. 7, ID codes are sequentially loaded into n latch circuits for each block. This code is checked by a matching circuit 98 to determine whether or not n consecutive ID codes match, and then inputted to the control circuit 7 through a code check output 96.

On the other hand, when the parity check circuit 5 detects that there is an error in the address code, the correction circuit 100 corrects the address code. This is because the parity code is generated from the AD code and ID code, and the I
If the D code is known by the ID check circuit 95, the address code can be determined from the parity code and the ID code. However, in this case, in order to avoid erroneous correction of the address code, the corrected address code is checked for continuity in the comparison circuit 42-2 and inputted to the determination circuit 45.

Even when the discrimination circuit detects an error in the output of the parity check circuit, if the corrected address code has continuity, the multiplexer 90 is switched to the corrected address side and the corrected address is loaded into the counter 6.

By using the ID code in this way, it is possible to generate a more accurate address.

〔Effect of the invention〕

According to the present invention, it is possible to generate more accurate addresses despite errors during transmission caused by dropouts and the like.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a control circuit according to an embodiment of the present invention, FIG. 3 is a diagram showing a reproduced intermittent signal, and FIG. A diagram showing an example of the operation according to the invention, FIG. 5 is a circuit diagram showing another embodiment according to the invention, FIG. 6 is a circuit diagram showing still another embodiment according to the invention, and FIG. 7 is a circuit diagram showing a correction circuit. A circuit diagram showing an example, FIG. M8 is a circuit diagram showing an example of a discrimination circuit. 1...Synchronization detection protection circuit 2...Timing circuit 3
...87P conversion circuit W&4...Latch circuit 5...Parity check circuit

Claims (1)

[Claims] 1. Data is divided into blocks, and each block is recorded with a block synchronization signal, a block address code, and a parity code for detecting errors in the block address code. In an address circuit that generates a block address from a reproduced signal, there is a synchronization circuit that detects a block synchronization signal, an address code circuit that takes in a block address code, a parity check circuit that performs a parity check, and a block output that counts the output of the synchronization circuit. a first address circuit that generates an address, a second address circuit that generates a block address using the address code circuit, and a comparison circuit that compares whether the output of the address code circuit is stepped up or stepped down; a first synchronization signal detection circuit that is set by the synchronization signal first detected by the synchronization circuit; a discrimination circuit that receives the outputs of the comparison circuit, the first synchronization signal detection circuit, and the parity check circuit; It consists of a switching circuit that switches the outputs of the first address circuit and the second address circuit, and the discrimination circuit switches the switching circuit to the second address circuit when there is no error in the outputs of the parity check circuit and the comparison circuit. When an error is detected, the switching circuit selects the first address circuit and outputs the block address. and the discrimination circuit generates an address by controlling a switching circuit using the output of the parity check circuit until the first synchronization signal detection circuit detects the first synchronization signal. circuit. 2. In claim 1, the discrimination circuit comprises:
It has a counter circuit that counts the number of undetectable synchronization circuits and a comparison circuit that compares the output of the counter circuit, and when the counted value of the counter circuit exceeds a predetermined value, the first synchronization detection circuit and the An address circuit characterized in that it resets first and second address circuits. 3. The address according to claim 1, wherein the parity check circuit inputs the corrected address code to a comparison circuit of the discrimination circuit and generates an address from the corrected address code. circuit.